Cross Reference: /gem5/tests/quick/se/00.hello/ref/power/linux/o3-timing/stats.txt

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stats.txt (10352:5f1f92bf76ee)	stats.txt (10409:8c80b91944c5)
1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18857500 # Number of ticks simulated 5final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks	1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000019 # Number of seconds simulated 4sim_ticks 18857500 # Number of ticks simulated 5final_tick 18857500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 41326 # Simulator instruction rate (inst/s) 8host_op_rate 41320 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 134509153 # Simulator tick rate (ticks/s) 10host_mem_usage 232584 # Number of bytes of host memory used 11host_seconds 0.14 # Real time elapsed on the host	7host_inst_rate 98075 # Simulator instruction rate (inst/s) 8host_op_rate 98051 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 319158839 # Simulator tick rate (ticks/s) 10host_mem_usage 285824 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host
12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 71 # Per bank write bursts 45system.physmem.perBankRdBursts::1 42 # Per bank write bursts 46system.physmem.perBankRdBursts::2 55 # Per bank write bursts 47system.physmem.perBankRdBursts::3 58 # Per bank write bursts 48system.physmem.perBankRdBursts::4 53 # Per bank write bursts 49system.physmem.perBankRdBursts::5 61 # Per bank write bursts 50system.physmem.perBankRdBursts::6 52 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 9 # Per bank write bursts 53system.physmem.perBankRdBursts::9 28 # Per bank write bursts 54system.physmem.perBankRdBursts::10 1 # Per bank write bursts 55system.physmem.perBankRdBursts::11 0 # Per bank write bursts 56system.physmem.perBankRdBursts::12 0 # Per bank write bursts 57system.physmem.perBankRdBursts::13 0 # Per bank write bursts 58system.physmem.perBankRdBursts::14 4 # Per bank write bursts 59system.physmem.perBankRdBursts::15 0 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 18724000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation	12sim_insts 5792 # Number of instructions simulated 13sim_ops 5792 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21952 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 6464 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28416 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21952 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21952 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 343 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 101 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 444 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 1164099165 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 342781387 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1506880552 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 1164099165 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 1164099165 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 1164099165 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 342781387 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1506880552 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.readReqs 444 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 444 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 28416 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 28416 # Total read bytes from the system interface side 40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side 41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue 42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one 43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write 44system.physmem.perBankRdBursts::0 71 # Per bank write bursts 45system.physmem.perBankRdBursts::1 42 # Per bank write bursts 46system.physmem.perBankRdBursts::2 55 # Per bank write bursts 47system.physmem.perBankRdBursts::3 58 # Per bank write bursts 48system.physmem.perBankRdBursts::4 53 # Per bank write bursts 49system.physmem.perBankRdBursts::5 61 # Per bank write bursts 50system.physmem.perBankRdBursts::6 52 # Per bank write bursts 51system.physmem.perBankRdBursts::7 10 # Per bank write bursts 52system.physmem.perBankRdBursts::8 9 # Per bank write bursts 53system.physmem.perBankRdBursts::9 28 # Per bank write bursts 54system.physmem.perBankRdBursts::10 1 # Per bank write bursts 55system.physmem.perBankRdBursts::11 0 # Per bank write bursts 56system.physmem.perBankRdBursts::12 0 # Per bank write bursts 57system.physmem.perBankRdBursts::13 0 # Per bank write bursts 58system.physmem.perBankRdBursts::14 4 # Per bank write bursts 59system.physmem.perBankRdBursts::15 0 # Per bank write bursts 60system.physmem.perBankWrBursts::0 0 # Per bank write bursts 61system.physmem.perBankWrBursts::1 0 # Per bank write bursts 62system.physmem.perBankWrBursts::2 0 # Per bank write bursts 63system.physmem.perBankWrBursts::3 0 # Per bank write bursts 64system.physmem.perBankWrBursts::4 0 # Per bank write bursts 65system.physmem.perBankWrBursts::5 0 # Per bank write bursts 66system.physmem.perBankWrBursts::6 0 # Per bank write bursts 67system.physmem.perBankWrBursts::7 0 # Per bank write bursts 68system.physmem.perBankWrBursts::8 0 # Per bank write bursts 69system.physmem.perBankWrBursts::9 0 # Per bank write bursts 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry 78system.physmem.totGap 18724000 # Total gap between requests 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 444 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 240 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::5 1 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see 107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see 108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see 109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see 110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see 111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see 112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see 125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see 133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see 134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see 135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see 136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see 137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see 138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see 139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see 140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see 141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see 142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see 143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see 144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see 157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see 158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see 159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see 160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see 161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see 162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see 163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see 164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see 165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see 166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see 167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see 168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see 169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see 170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see 171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see 172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see 173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see 174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see 175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see 176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see 177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see 178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see 179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see 180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see 189system.physmem.bytesPerActivate::samples 79 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 333.772152 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 192.283764 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 349.893315 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 30 37.97% 37.97% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 17 21.52% 59.49% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 8 10.13% 69.62% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 4 5.06% 74.68% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 3.80% 78.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 2.53% 81.01% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 1.27% 82.28% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 3 3.80% 86.08% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 11 13.92% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 79 # Bytes accessed per row activation
203system.physmem.totQLat 3609000 # Total ticks spent queuing 204system.physmem.totMemAccLat 11934000 # Total ticks spent from burst creation until serviced by the DRAM	203system.physmem.totQLat 3635500 # Total ticks spent queuing 204system.physmem.totMemAccLat 11960500 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers	205system.physmem.totBusLat 2220000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 8128.38 # Average queueing delay per DRAM burst	206system.physmem.avgQLat 8188.06 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst	207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 26878.38 # Average memory access latency per DRAM burst	208system.physmem.avgMemAccLat 26938.06 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.77 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 356 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 42171.17 # Average gap between requests 224system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states	209system.physmem.avgRdBW 1506.88 # Average DRAM read bandwidth in MiByte/s 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 211system.physmem.avgRdBWSys 1506.88 # Average system read bandwidth in MiByte/s 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 214system.physmem.busUtil 11.77 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.77 # Data bus utilization in percentage for reads 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.82 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 356 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 80.18 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 223system.physmem.avgGap 42171.17 # Average gap between requests 224system.physmem.pageHitRate 80.18 # Row buffer hit rate, read and write combined 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
230system.membus.throughput 1506880552 # Throughput (bytes/s)
231system.membus.trans_dist::ReadReq 397 # Transaction distribution 232system.membus.trans_dist::ReadResp 397 # Transaction distribution 233system.membus.trans_dist::ReadExReq 47 # Transaction distribution 234system.membus.trans_dist::ReadExResp 47 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)	230system.membus.trans_dist::ReadReq 397 # Transaction distribution 231system.membus.trans_dist::ReadResp 397 # Transaction distribution 232system.membus.trans_dist::ReadExReq 47 # Transaction distribution 233system.membus.trans_dist::ReadExResp 47 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 888 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 888 # Packet count per connected master and slave (bytes)
237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 28416 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)	236system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28416 # Cumulative packet size per connected master and slave (bytes) 237system.membus.pkt_size::total 28416 # Cumulative packet size per connected master and slave (bytes) 238system.membus.snoops 0 # Total snoops (count) 239system.membus.snoop_fanout::samples 444 # Request fanout histogram 240system.membus.snoop_fanout::mean 0 # Request fanout histogram 241system.membus.snoop_fanout::stdev 0 # Request fanout histogram 242system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 243system.membus.snoop_fanout::0 444 100.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 246system.membus.snoop_fanout::min_value 0 # Request fanout histogram 247system.membus.snoop_fanout::max_value 0 # Request fanout histogram 248system.membus.snoop_fanout::total 444 # Request fanout histogram
241system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) 242system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 243system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 22.1 # Layer utilization (%) 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2332 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 661 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage 253system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. 254system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. 255system.cpu.dtb.read_hits 0 # DTB read hits 256system.cpu.dtb.read_misses 0 # DTB read misses 257system.cpu.dtb.read_accesses 0 # DTB read accesses 258system.cpu.dtb.write_hits 0 # DTB write hits 259system.cpu.dtb.write_misses 0 # DTB write misses 260system.cpu.dtb.write_accesses 0 # DTB write accesses 261system.cpu.dtb.hits 0 # DTB hits 262system.cpu.dtb.misses 0 # DTB misses 263system.cpu.dtb.accesses 0 # DTB accesses 264system.cpu.itb.read_hits 0 # DTB read hits 265system.cpu.itb.read_misses 0 # DTB read misses 266system.cpu.itb.read_accesses 0 # DTB read accesses 267system.cpu.itb.write_hits 0 # DTB write hits 268system.cpu.itb.write_misses 0 # DTB write misses 269system.cpu.itb.write_accesses 0 # DTB write accesses 270system.cpu.itb.hits 0 # DTB hits 271system.cpu.itb.misses 0 # DTB misses 272system.cpu.itb.accesses 0 # DTB accesses 273system.cpu.workload.num_syscalls 9 # Number of system calls 274system.cpu.numCycles 37716 # number of cpu cycles simulated 275system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 276system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 277system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss 278system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed 279system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered 280system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken 281system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked 282system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing 283system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 284system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 285system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 286system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched 287system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 288system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle 306system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle 307system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle 308system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked 309system.cpu.decode.RunCycles 1951 # Number of cycles decode is running 310system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking 311system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing 312system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch 313system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction 314system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode 315system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode 316system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing 317system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle 318system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking 319system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst 320system.cpu.rename.RunCycles 1916 # Number of cycles rename is running 321system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking 322system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename 323system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 324system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full 325system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 326system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed 327system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made 328system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups 329system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 330system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 331system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing 332system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 333system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 334system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer 335system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. 336system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 337system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 338system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 339system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) 340system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ 341system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued 342system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued 343system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling 344system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph 345system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed 346system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle 363system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 364system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available 365system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available 366system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available 370system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available 371system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available 372system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 373system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available 374system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available 375system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available 376system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available 377system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available 378system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available 379system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 393system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available 394system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available 395system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 396system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 397system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 398system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued 399system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued 400system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued 401system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued 402system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued 403system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued 404system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued 405system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued 406system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued 407system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued 408system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued 409system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued 410system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued 411system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued 412system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued 413system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued 427system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued 428system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued 429system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 430system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 431system.cpu.iq.FU_type_0::total 9108 # Type of FU issued 432system.cpu.iq.rate 0.241489 # Inst issue rate 433system.cpu.iq.fu_busy_cnt 251 # FU busy when requested 434system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) 435system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads 436system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes 437system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses 438system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 439system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes 440system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 441system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses 442system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 443system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores 444system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 445system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed 446system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 447system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 448system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed 449system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 450system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 451system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 452system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 453system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 454system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing 455system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking 456system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking 457system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ 458system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch 459system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions 460system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions 461system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions 462system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall 463system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall 464system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 465system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 466system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly 467system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute 468system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions 469system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed 470system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute 471system.cpu.iew.exec_swp 0 # number of swp insts executed 472system.cpu.iew.exec_nop 0 # number of nop insts executed 473system.cpu.iew.exec_refs 3329 # number of memory reference insts executed 474system.cpu.iew.exec_branches 1361 # Number of branches executed 475system.cpu.iew.exec_stores 1554 # Number of stores executed 476system.cpu.iew.exec_rate 0.230724 # Inst execution rate 477system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit 478system.cpu.iew.wb_count 8300 # cumulative count of insts written-back 479system.cpu.iew.wb_producers 4483 # num instructions producing a value 480system.cpu.iew.wb_consumers 7102 # num instructions consuming a value 481system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 482system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle 483system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back 484system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 485system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit 486system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 487system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted 488system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle 505system.cpu.commit.committedInsts 5792 # Number of instructions committed 506system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 507system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 508system.cpu.commit.refs 2007 # Number of memory references committed 509system.cpu.commit.loads 961 # Number of loads committed 510system.cpu.commit.membars 7 # Number of memory barriers committed 511system.cpu.commit.branches 1037 # Number of branches committed 512system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 513system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 514system.cpu.commit.function_calls 103 # Number of function calls committed. 515system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 516system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction 517system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction 518system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction 519system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction 520system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction 521system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction 522system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction 523system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction 524system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 545system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 546system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 547system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 548system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 549system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 550system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached 551system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 552system.cpu.rob.rob_reads 21861 # The number of ROB reads 553system.cpu.rob.rob_writes 21469 # The number of ROB writes 554system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself 555system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling 556system.cpu.committedInsts 5792 # Number of Instructions Simulated 557system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 558system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads 562system.cpu.int_regfile_reads 13743 # number of integer regfile reads 563system.cpu.int_regfile_writes 7176 # number of integer regfile writes 564system.cpu.fp_regfile_reads 25 # number of floating regfile reads 565system.cpu.fp_regfile_writes 2 # number of floating regfile writes	249system.membus.reqLayer0.occupancy 555500 # Layer occupancy (ticks) 250system.membus.reqLayer0.utilization 2.9 # Layer utilization (%) 251system.membus.respLayer1.occupancy 4160750 # Layer occupancy (ticks) 252system.membus.respLayer1.utilization 22.1 # Layer utilization (%) 253system.cpu_clk_domain.clock 500 # Clock period in ticks 254system.cpu.branchPred.lookups 2332 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1883 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 415 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 1931 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 661 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 34.230968 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 219 # Number of times the RAS was used to get a target. 262system.cpu.branchPred.RASInCorrect 31 # Number of incorrect RAS predictions. 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses 268system.cpu.dtb.write_accesses 0 # DTB write accesses 269system.cpu.dtb.hits 0 # DTB hits 270system.cpu.dtb.misses 0 # DTB misses 271system.cpu.dtb.accesses 0 # DTB accesses 272system.cpu.itb.read_hits 0 # DTB read hits 273system.cpu.itb.read_misses 0 # DTB read misses 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 9 # Number of system calls 282system.cpu.numCycles 37716 # number of cpu cycles simulated 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 285system.cpu.fetch.icacheStallCycles 7977 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13500 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2332 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 880 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 3710 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing 291system.cpu.fetch.MiscStallCycles 3 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs 292system.cpu.fetch.PendingTrapStallCycles 159 # Number of stall cycles due to pending traps 293system.cpu.fetch.IcacheWaitRetryStallCycles 22 # Number of stall cycles due to full MSHR 294system.cpu.fetch.CacheLines 1829 # Number of cache lines fetched 295system.cpu.fetch.IcacheSquashes 300 # Number of outstanding Icache misses that were squashed 296system.cpu.fetch.rateDist::samples 12303 # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::mean 1.097293 # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::stdev 2.503786 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::0 9940 80.79% 80.79% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::1 189 1.54% 82.33% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::2 216 1.76% 84.09% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::3 152 1.24% 85.32% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::4 247 2.01% 87.33% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::5 139 1.13% 88.46% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::6 253 2.06% 90.51% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::7 114 0.93% 91.44% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::8 1053 8.56% 100.00% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::total 12303 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.branchRate 0.061831 # Number of branch fetches per cycle 314system.cpu.fetch.rate 0.357938 # Number of inst fetches per cycle 315system.cpu.decode.IdleCycles 7389 # Number of cycles decode is idle 316system.cpu.decode.BlockedCycles 2550 # Number of cycles decode is blocked 317system.cpu.decode.RunCycles 1951 # Number of cycles decode is running 318system.cpu.decode.UnblockCycles 130 # Number of cycles decode is unblocking 319system.cpu.decode.SquashCycles 283 # Number of cycles decode is squashing 320system.cpu.decode.BranchResolved 336 # Number of times decode resolved a branch 321system.cpu.decode.BranchMispred 150 # Number of times decode detected a branch misprediction 322system.cpu.decode.DecodedInsts 11555 # Number of instructions handled by decode 323system.cpu.decode.SquashedInsts 471 # Number of squashed instructions handled by decode 324system.cpu.rename.SquashCycles 283 # Number of cycles rename is squashing 325system.cpu.rename.IdleCycles 7548 # Number of cycles rename is idle 326system.cpu.rename.BlockCycles 922 # Number of cycles rename is blocking 327system.cpu.rename.serializeStallCycles 607 # count of cycles rename stalled for serializing inst 328system.cpu.rename.RunCycles 1916 # Number of cycles rename is running 329system.cpu.rename.UnblockCycles 1027 # Number of cycles rename is unblocking 330system.cpu.rename.RenamedInsts 11189 # Number of instructions processed by rename 331system.cpu.rename.IQFullEvents 12 # Number of times rename has blocked due to IQ full 332system.cpu.rename.LQFullEvents 25 # Number of times rename has blocked due to LQ full 333system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 334system.cpu.rename.RenamedOperands 9624 # Number of destination operands rename has renamed 335system.cpu.rename.RenameLookups 18111 # Number of register rename lookups that rename has made 336system.cpu.rename.int_rename_lookups 18085 # Number of integer rename lookups 337system.cpu.rename.fp_rename_lookups 26 # Number of floating rename lookups 338system.cpu.rename.CommittedMaps 4998 # Number of HB maps that are committed 339system.cpu.rename.UndoneMaps 4626 # Number of HB maps that are undone due to squashing 340system.cpu.rename.serializingInsts 27 # count of serializing insts renamed 341system.cpu.rename.tempSerializingInsts 27 # count of temporary serializing insts renamed 342system.cpu.rename.skidInsts 351 # count of insts added to the skid buffer 343system.cpu.memDep0.insertedLoads 2013 # Number of loads inserted to the mem dependence unit. 344system.cpu.memDep0.insertedStores 1831 # Number of stores inserted to the mem dependence unit. 345system.cpu.memDep0.conflictingLoads 52 # Number of conflicting loads. 346system.cpu.memDep0.conflictingStores 29 # Number of conflicting stores. 347system.cpu.iq.iqInstsAdded 10314 # Number of instructions added to the IQ (excludes non-spec) 348system.cpu.iq.iqNonSpecInstsAdded 63 # Number of non-speculative instructions added to the IQ 349system.cpu.iq.iqInstsIssued 9108 # Number of instructions issued 350system.cpu.iq.iqSquashedInstsIssued 73 # Number of squashed instructions issued 351system.cpu.iq.iqSquashedInstsExamined 4178 # Number of squashed instructions iterated over during squash; mainly for profiling 352system.cpu.iq.iqSquashedOperandsExamined 3333 # Number of squashed operands that are examined and possibly removed from graph 353system.cpu.iq.iqSquashedNonSpecRemoved 47 # Number of squashed non-spec instructions that were removed 354system.cpu.iq.issued_per_cycle::samples 12303 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::mean 0.740307 # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::stdev 1.567670 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::0 9185 74.66% 74.66% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::1 929 7.55% 82.21% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::2 638 5.19% 87.39% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::3 470 3.82% 91.21% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::4 430 3.50% 94.71% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::5 294 2.39% 97.10% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::6 241 1.96% 99.06% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::7 71 0.58% 99.63% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::8 45 0.37% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::total 12303 # Number of insts issued each cycle 371system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntAlu 10 3.98% 3.98% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntMult 0 0.00% 3.98% # attempts to use FU when none available 374system.cpu.iq.fu_full::IntDiv 0 0.00% 3.98% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.98% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.98% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.98% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatMult 0 0.00% 3.98% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.98% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.98% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.98% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.98% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.98% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.98% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.98% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMult 0 0.00% 3.98% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.98% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShift 0 0.00% 3.98% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.98% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.98% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.98% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.98% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.98% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.98% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.98% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.98% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.98% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.98% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.98% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemRead 122 48.61% 52.59% # attempts to use FU when none available 402system.cpu.iq.fu_full::MemWrite 119 47.41% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 405system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued 406system.cpu.iq.FU_type_0::IntAlu 5539 60.81% 60.81% # Type of FU issued 407system.cpu.iq.FU_type_0::IntMult 0 0.00% 60.81% # Type of FU issued 408system.cpu.iq.FU_type_0::IntDiv 0 0.00% 60.81% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 60.84% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 60.84% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 60.84% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatMult 0 0.00% 60.84% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 60.84% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 60.84% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 60.84% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 60.84% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 60.84% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 60.84% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 60.84% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 60.84% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMult 0 0.00% 60.84% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 60.84% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShift 0 0.00% 60.84% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 60.84% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 60.84% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 60.84% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 60.84% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 60.84% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 60.84% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 60.84% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 60.84% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 60.84% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 60.84% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 60.84% # Type of FU issued 435system.cpu.iq.FU_type_0::MemRead 1909 20.96% 81.80% # Type of FU issued 436system.cpu.iq.FU_type_0::MemWrite 1658 18.20% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 438system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 439system.cpu.iq.FU_type_0::total 9108 # Type of FU issued 440system.cpu.iq.rate 0.241489 # Inst issue rate 441system.cpu.iq.fu_busy_cnt 251 # FU busy when requested 442system.cpu.iq.fu_busy_rate 0.027558 # FU busy rate (busy events/executed inst) 443system.cpu.iq.int_inst_queue_reads 30781 # Number of integer instruction queue reads 444system.cpu.iq.int_inst_queue_writes 14531 # Number of integer instruction queue writes 445system.cpu.iq.int_inst_queue_wakeup_accesses 8273 # Number of integer instruction queue wakeup accesses 446system.cpu.iq.fp_inst_queue_reads 62 # Number of floating instruction queue reads 447system.cpu.iq.fp_inst_queue_writes 31 # Number of floating instruction queue writes 448system.cpu.iq.fp_inst_queue_wakeup_accesses 27 # Number of floating instruction queue wakeup accesses 449system.cpu.iq.int_alu_accesses 9325 # Number of integer alu accesses 450system.cpu.iq.fp_alu_accesses 34 # Number of floating point alu accesses 451system.cpu.iew.lsq.thread0.forwLoads 79 # Number of loads that had data forwarded from stores 452system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address 453system.cpu.iew.lsq.thread0.squashedLoads 1052 # Number of loads squashed 454system.cpu.iew.lsq.thread0.ignoredResponses 2 # Number of memory responses ignored because the instruction is squashed 455system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations 456system.cpu.iew.lsq.thread0.squashedStores 785 # Number of stores squashed 457system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 458system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 459system.cpu.iew.lsq.thread0.rescheduledLoads 1 # Number of loads that were rescheduled 460system.cpu.iew.lsq.thread0.cacheBlocked 8 # Number of times an access to memory failed due to the cache being blocked 461system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 462system.cpu.iew.iewSquashCycles 283 # Number of cycles IEW is squashing 463system.cpu.iew.iewBlockCycles 835 # Number of cycles IEW is blocking 464system.cpu.iew.iewUnblockCycles 80 # Number of cycles IEW is unblocking 465system.cpu.iew.iewDispatchedInsts 10377 # Number of instructions dispatched to IQ 466system.cpu.iew.iewDispSquashedInsts 18 # Number of squashed instructions skipped by dispatch 467system.cpu.iew.iewDispLoadInsts 2013 # Number of dispatched load instructions 468system.cpu.iew.iewDispStoreInsts 1831 # Number of dispatched store instructions 469system.cpu.iew.iewDispNonSpecInsts 54 # Number of dispatched non-speculative instructions 470system.cpu.iew.iewIQFullEvents 11 # Number of times the IQ has become full, causing a stall 471system.cpu.iew.iewLSQFullEvents 70 # Number of times the LSQ has become full, causing a stall 472system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations 473system.cpu.iew.predictedTakenIncorrect 69 # Number of branches that were predicted taken incorrectly 474system.cpu.iew.predictedNotTakenIncorrect 277 # Number of branches that were predicted not taken incorrectly 475system.cpu.iew.branchMispredicts 346 # Number of branch mispredicts detected at execute 476system.cpu.iew.iewExecutedInsts 8702 # Number of executed instructions 477system.cpu.iew.iewExecLoadInsts 1775 # Number of load instructions executed 478system.cpu.iew.iewExecSquashedInsts 406 # Number of squashed instructions skipped in execute 479system.cpu.iew.exec_swp 0 # number of swp insts executed 480system.cpu.iew.exec_nop 0 # number of nop insts executed 481system.cpu.iew.exec_refs 3329 # number of memory reference insts executed 482system.cpu.iew.exec_branches 1361 # Number of branches executed 483system.cpu.iew.exec_stores 1554 # Number of stores executed 484system.cpu.iew.exec_rate 0.230724 # Inst execution rate 485system.cpu.iew.wb_sent 8430 # cumulative count of insts sent to commit 486system.cpu.iew.wb_count 8300 # cumulative count of insts written-back 487system.cpu.iew.wb_producers 4483 # num instructions producing a value 488system.cpu.iew.wb_consumers 7102 # num instructions consuming a value 489system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ 490system.cpu.iew.wb_rate 0.220066 # insts written-back per cycle 491system.cpu.iew.wb_fanout 0.631231 # average fanout of values written-back 492system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 493system.cpu.commit.commitSquashedInsts 4587 # The number of squashed insts skipped by commit 494system.cpu.commit.commitNonSpecStalls 16 # The number of times commit has been forced to stall to communicate backwards 495system.cpu.commit.branchMispredicts 277 # The number of times a branch was mispredicted 496system.cpu.commit.committed_per_cycle::samples 11593 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::mean 0.499612 # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::stdev 1.370164 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::0 9440 81.43% 81.43% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::1 839 7.24% 88.67% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::2 524 4.52% 93.19% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::3 224 1.93% 95.12% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::4 167 1.44% 96.56% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::5 112 0.97% 97.52% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::6 115 0.99% 98.52% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::7 61 0.53% 99.04% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::8 111 0.96% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::total 11593 # Number of insts commited each cycle 513system.cpu.commit.committedInsts 5792 # Number of instructions committed 514system.cpu.commit.committedOps 5792 # Number of ops (including micro ops) committed 515system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 516system.cpu.commit.refs 2007 # Number of memory references committed 517system.cpu.commit.loads 961 # Number of loads committed 518system.cpu.commit.membars 7 # Number of memory barriers committed 519system.cpu.commit.branches 1037 # Number of branches committed 520system.cpu.commit.fp_insts 22 # Number of committed floating point instructions. 521system.cpu.commit.int_insts 5698 # Number of committed integer instructions. 522system.cpu.commit.function_calls 103 # Number of function calls committed. 523system.cpu.commit.op_class_0::No_OpClass 0 0.00% 0.00% # Class of committed instruction 524system.cpu.commit.op_class_0::IntAlu 3783 65.31% 65.31% # Class of committed instruction 525system.cpu.commit.op_class_0::IntMult 0 0.00% 65.31% # Class of committed instruction 526system.cpu.commit.op_class_0::IntDiv 0 0.00% 65.31% # Class of committed instruction 527system.cpu.commit.op_class_0::FloatAdd 2 0.03% 65.35% # Class of committed instruction 528system.cpu.commit.op_class_0::FloatCmp 0 0.00% 65.35% # Class of committed instruction 529system.cpu.commit.op_class_0::FloatCvt 0 0.00% 65.35% # Class of committed instruction 530system.cpu.commit.op_class_0::FloatMult 0 0.00% 65.35% # Class of committed instruction 531system.cpu.commit.op_class_0::FloatDiv 0 0.00% 65.35% # Class of committed instruction 532system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 65.35% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdAdd 0 0.00% 65.35% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 65.35% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdAlu 0 0.00% 65.35% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdCmp 0 0.00% 65.35% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdCvt 0 0.00% 65.35% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdMisc 0 0.00% 65.35% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdMult 0 0.00% 65.35% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 65.35% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdShift 0 0.00% 65.35% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 65.35% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 65.35% # Class of committed instruction 544system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 65.35% # Class of committed instruction 545system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 65.35% # Class of committed instruction 546system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 65.35% # Class of committed instruction 547system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 65.35% # Class of committed instruction 548system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 65.35% # Class of committed instruction 549system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 65.35% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 65.35% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 65.35% # Class of committed instruction 552system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 65.35% # Class of committed instruction 553system.cpu.commit.op_class_0::MemRead 961 16.59% 81.94% # Class of committed instruction 554system.cpu.commit.op_class_0::MemWrite 1046 18.06% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 557system.cpu.commit.op_class_0::total 5792 # Class of committed instruction 558system.cpu.commit.bw_lim_events 111 # number cycles where commit BW limit reached 559system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits 560system.cpu.rob.rob_reads 21861 # The number of ROB reads 561system.cpu.rob.rob_writes 21469 # The number of ROB writes 562system.cpu.timesIdled 245 # Number of times that the entire CPU went into an idle state and unscheduled itself 563system.cpu.idleCycles 25413 # Total number of cycles that the CPU has spent unscheduled due to idling 564system.cpu.committedInsts 5792 # Number of Instructions Simulated 565system.cpu.committedOps 5792 # Number of Ops (including micro ops) Simulated 566system.cpu.cpi 6.511740 # CPI: Cycles Per Instruction 567system.cpu.cpi_total 6.511740 # CPI: Total CPI of All Threads 568system.cpu.ipc 0.153569 # IPC: Instructions Per Cycle 569system.cpu.ipc_total 0.153569 # IPC: Total IPC of All Threads 570system.cpu.int_regfile_reads 13743 # number of integer regfile reads 571system.cpu.int_regfile_writes 7176 # number of integer regfile writes 572system.cpu.fp_regfile_reads 25 # number of floating regfile reads 573system.cpu.fp_regfile_writes 2 # number of floating regfile writes
566system.cpu.toL2Bus.throughput 1530637677 # Throughput (bytes/s)
567system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 571system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 573system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)	574system.cpu.toL2Bus.trans_dist::ReadReq 405 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadResp 404 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExReq 47 # Transaction distribution 577system.cpu.toL2Bus.trans_dist::ReadExResp 47 # Transaction distribution 578system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 699 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 204 # Packet count per connected master and slave (bytes) 580system.cpu.toL2Bus.pkt_count::total 903 # Packet count per connected master and slave (bytes)
574system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.tot_pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) 577system.cpu.toL2Bus.data_through_bus 28864 # Total data (bytes) 578system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)	581system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 22336 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 6528 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.pkt_size::total 28864 # Cumulative packet size per connected master and slave (bytes) 584system.cpu.toL2Bus.snoops 0 # Total snoops (count) 585system.cpu.toL2Bus.snoop_fanout::samples 452 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::1 452 100.00% 100.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 595system.cpu.toL2Bus.snoop_fanout::total 452 # Request fanout histogram
579system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) 580system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 581system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) 582system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) 583system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) 584system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 585system.cpu.icache.tags.replacements 0 # number of replacements 586system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use 587system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. 588system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 589system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. 590system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 591system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor 592system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy 593system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy 594system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 595system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 596system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 597system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 598system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses 599system.cpu.icache.tags.data_accesses 4007 # Number of data accesses 600system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits 601system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits 602system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits 603system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits 604system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits 605system.cpu.icache.overall_hits::total 1391 # number of overall hits 606system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 607system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 608system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 609system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 610system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 611system.cpu.icache.overall_misses::total 438 # number of overall misses 612system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles 613system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles 614system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles 615system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles 616system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles 617system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles 618system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) 619system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses 621system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses 622system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses 623system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses 624system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses 625system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses 626system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses 627system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses 628system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses 629system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses 630system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency 631system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency 632system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 633system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency 634system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency 636system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked 637system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 638system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 639system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 640system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked 641system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 642system.cpu.icache.fast_writes 0 # number of fast writes performed 643system.cpu.icache.cache_copies 0 # number of cache copies performed 644system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 645system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 646system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 647system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 648system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 649system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits 650system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 651system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 652system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 653system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 654system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 655system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses 656system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles 657system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles 662system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses 663system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses 664system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses 665system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses 666system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses 667system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 674system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 675system.cpu.l2cache.tags.replacements 0 # number of replacements 676system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use 677system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 678system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 679system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. 680system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 681system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor 682system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy 686system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 689system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 690system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses 691system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses 692system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 693system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 695system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 696system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 697system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits 698system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 699system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 700system.cpu.l2cache.overall_hits::total 7 # number of overall hits 701system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses 702system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 703system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses 704system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 705system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 706system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 707system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 708system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 709system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 710system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 711system.cpu.l2cache.overall_misses::total 445 # number of overall misses 712system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles 713system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles 714system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles 715system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles 716system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles 717system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles 718system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles 719system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles 720system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles 721system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles 722system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles 723system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) 724system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 725system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 726system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 727system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 728system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 729system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 730system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses 731system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses 732system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses 733system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses 734system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses 735system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses 736system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses 737system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 738system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 739system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 740system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 741system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses 742system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 743system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 744system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses 745system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency 746system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency 747system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency 748system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency 749system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency 750system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 751system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 752system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency 753system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 754system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 755system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency 756system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 757system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 758system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 759system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 760system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 761system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 762system.cpu.l2cache.fast_writes 0 # number of fast writes performed 763system.cpu.l2cache.cache_copies 0 # number of cache copies performed 764system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 765system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 766system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses 767system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 768system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 769system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 771system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 772system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 773system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 774system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 775system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles 776system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles 777system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles 778system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles 779system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles 780system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles 782system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles 783system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles 784system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles 785system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles 786system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses 787system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 788system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses 789system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 790system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 791system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 792system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 793system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses 794system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 795system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 796system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses 797system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency 798system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency 799system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency 800system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency 801system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 803system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 804system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 806system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 807system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 808system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 809system.cpu.dcache.tags.replacements 0 # number of replacements 810system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use 811system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. 812system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 813system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. 814system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 815system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor 816system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy 817system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy 818system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 819system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 820system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id 821system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 822system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 823system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 824system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits 825system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits 826system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits 827system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits 828system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits 829system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits 830system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits 831system.cpu.dcache.overall_hits::total 2261 # number of overall hits 832system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 833system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 834system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 835system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 836system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses 837system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses 838system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses 839system.cpu.dcache.overall_misses::total 452 # number of overall misses 840system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles 841system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles 842system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles 843system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles 844system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles 845system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles 846system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles 847system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles 848system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) 849system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) 850system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 851system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 852system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 853system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 854system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 855system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses 856system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses 857system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses 858system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses 859system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses 860system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses 861system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses 862system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses 863system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses 864system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency 865system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency 866system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency 867system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency 868system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 869system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency 870system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 871system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency 872system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked 873system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 874system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 875system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 876system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked 877system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 878system.cpu.dcache.fast_writes 0 # number of fast writes performed 879system.cpu.dcache.cache_copies 0 # number of cache copies performed 880system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 881system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 882system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits 883system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits 884system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 885system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 886system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 887system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 888system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 889system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 890system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 891system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 892system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 893system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 894system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 895system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses 896system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles 897system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles 898system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles 899system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles 900system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles 901system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles 902system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles 903system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles 904system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses 905system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses 906system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 907system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 908system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses 909system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses 910system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses 911system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses 912system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency 913system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency 914system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency 915system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency 916system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 917system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 918system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 919system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 920system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 921 922---------- End Simulation Statistics ----------	596system.cpu.toL2Bus.reqLayer0.occupancy 226000 # Layer occupancy (ticks) 597system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 598system.cpu.toL2Bus.respLayer0.occupancy 584250 # Layer occupancy (ticks) 599system.cpu.toL2Bus.respLayer0.utilization 3.1 # Layer utilization (%) 600system.cpu.toL2Bus.respLayer1.occupancy 162500 # Layer occupancy (ticks) 601system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 602system.cpu.icache.tags.replacements 0 # number of replacements 603system.cpu.icache.tags.tagsinuse 170.472010 # Cycle average of tags in use 604system.cpu.icache.tags.total_refs 1391 # Total number of references to valid blocks. 605system.cpu.icache.tags.sampled_refs 349 # Sample count of references to valid blocks. 606system.cpu.icache.tags.avg_refs 3.985673 # Average number of references to valid blocks. 607system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 608system.cpu.icache.tags.occ_blocks::cpu.inst 170.472010 # Average occupied blocks per requestor 609system.cpu.icache.tags.occ_percent::cpu.inst 0.083238 # Average percentage of cache occupancy 610system.cpu.icache.tags.occ_percent::total 0.083238 # Average percentage of cache occupancy 611system.cpu.icache.tags.occ_task_id_blocks::1024 349 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::0 194 # Occupied blocks per task id 613system.cpu.icache.tags.age_task_id_blocks_1024::1 155 # Occupied blocks per task id 614system.cpu.icache.tags.occ_task_id_percent::1024 0.170410 # Percentage of cache occupancy per task id 615system.cpu.icache.tags.tag_accesses 4007 # Number of tag accesses 616system.cpu.icache.tags.data_accesses 4007 # Number of data accesses 617system.cpu.icache.ReadReq_hits::cpu.inst 1391 # number of ReadReq hits 618system.cpu.icache.ReadReq_hits::total 1391 # number of ReadReq hits 619system.cpu.icache.demand_hits::cpu.inst 1391 # number of demand (read+write) hits 620system.cpu.icache.demand_hits::total 1391 # number of demand (read+write) hits 621system.cpu.icache.overall_hits::cpu.inst 1391 # number of overall hits 622system.cpu.icache.overall_hits::total 1391 # number of overall hits 623system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 624system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 625system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 626system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 627system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 628system.cpu.icache.overall_misses::total 438 # number of overall misses 629system.cpu.icache.ReadReq_miss_latency::cpu.inst 29787250 # number of ReadReq miss cycles 630system.cpu.icache.ReadReq_miss_latency::total 29787250 # number of ReadReq miss cycles 631system.cpu.icache.demand_miss_latency::cpu.inst 29787250 # number of demand (read+write) miss cycles 632system.cpu.icache.demand_miss_latency::total 29787250 # number of demand (read+write) miss cycles 633system.cpu.icache.overall_miss_latency::cpu.inst 29787250 # number of overall miss cycles 634system.cpu.icache.overall_miss_latency::total 29787250 # number of overall miss cycles 635system.cpu.icache.ReadReq_accesses::cpu.inst 1829 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.ReadReq_accesses::total 1829 # number of ReadReq accesses(hits+misses) 637system.cpu.icache.demand_accesses::cpu.inst 1829 # number of demand (read+write) accesses 638system.cpu.icache.demand_accesses::total 1829 # number of demand (read+write) accesses 639system.cpu.icache.overall_accesses::cpu.inst 1829 # number of overall (read+write) accesses 640system.cpu.icache.overall_accesses::total 1829 # number of overall (read+write) accesses 641system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.239475 # miss rate for ReadReq accesses 642system.cpu.icache.ReadReq_miss_rate::total 0.239475 # miss rate for ReadReq accesses 643system.cpu.icache.demand_miss_rate::cpu.inst 0.239475 # miss rate for demand accesses 644system.cpu.icache.demand_miss_rate::total 0.239475 # miss rate for demand accesses 645system.cpu.icache.overall_miss_rate::cpu.inst 0.239475 # miss rate for overall accesses 646system.cpu.icache.overall_miss_rate::total 0.239475 # miss rate for overall accesses 647system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68007.420091 # average ReadReq miss latency 648system.cpu.icache.ReadReq_avg_miss_latency::total 68007.420091 # average ReadReq miss latency 649system.cpu.icache.demand_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 650system.cpu.icache.demand_avg_miss_latency::total 68007.420091 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::cpu.inst 68007.420091 # average overall miss latency 652system.cpu.icache.overall_avg_miss_latency::total 68007.420091 # average overall miss latency 653system.cpu.icache.blocked_cycles::no_mshrs 404 # number of cycles access was blocked 654system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.icache.blocked::no_mshrs 5 # number of cycles access was blocked 656system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 657system.cpu.icache.avg_blocked_cycles::no_mshrs 80.800000 # average number of cycles each access was blocked 658system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.icache.fast_writes 0 # number of fast writes performed 660system.cpu.icache.cache_copies 0 # number of cache copies performed 661system.cpu.icache.ReadReq_mshr_hits::cpu.inst 88 # number of ReadReq MSHR hits 662system.cpu.icache.ReadReq_mshr_hits::total 88 # number of ReadReq MSHR hits 663system.cpu.icache.demand_mshr_hits::cpu.inst 88 # number of demand (read+write) MSHR hits 664system.cpu.icache.demand_mshr_hits::total 88 # number of demand (read+write) MSHR hits 665system.cpu.icache.overall_mshr_hits::cpu.inst 88 # number of overall MSHR hits 666system.cpu.icache.overall_mshr_hits::total 88 # number of overall MSHR hits 667system.cpu.icache.ReadReq_mshr_misses::cpu.inst 350 # number of ReadReq MSHR misses 668system.cpu.icache.ReadReq_mshr_misses::total 350 # number of ReadReq MSHR misses 669system.cpu.icache.demand_mshr_misses::cpu.inst 350 # number of demand (read+write) MSHR misses 670system.cpu.icache.demand_mshr_misses::total 350 # number of demand (read+write) MSHR misses 671system.cpu.icache.overall_mshr_misses::cpu.inst 350 # number of overall MSHR misses 672system.cpu.icache.overall_mshr_misses::total 350 # number of overall MSHR misses 673system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24058750 # number of ReadReq MSHR miss cycles 674system.cpu.icache.ReadReq_mshr_miss_latency::total 24058750 # number of ReadReq MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24058750 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.demand_mshr_miss_latency::total 24058750 # number of demand (read+write) MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24058750 # number of overall MSHR miss cycles 678system.cpu.icache.overall_mshr_miss_latency::total 24058750 # number of overall MSHR miss cycles 679system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for ReadReq accesses 680system.cpu.icache.ReadReq_mshr_miss_rate::total 0.191361 # mshr miss rate for ReadReq accesses 681system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for demand accesses 682system.cpu.icache.demand_mshr_miss_rate::total 0.191361 # mshr miss rate for demand accesses 683system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.191361 # mshr miss rate for overall accesses 684system.cpu.icache.overall_mshr_miss_rate::total 0.191361 # mshr miss rate for overall accesses 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 68739.285714 # average ReadReq mshr miss latency 686system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 68739.285714 # average ReadReq mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 688system.cpu.icache.demand_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 68739.285714 # average overall mshr miss latency 690system.cpu.icache.overall_avg_mshr_miss_latency::total 68739.285714 # average overall mshr miss latency 691system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 692system.cpu.l2cache.tags.replacements 0 # number of replacements 693system.cpu.l2cache.tags.tagsinuse 201.157905 # Cycle average of tags in use 694system.cpu.l2cache.tags.total_refs 7 # Total number of references to valid blocks. 695system.cpu.l2cache.tags.sampled_refs 397 # Sample count of references to valid blocks. 696system.cpu.l2cache.tags.avg_refs 0.017632 # Average number of references to valid blocks. 697system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 698system.cpu.l2cache.tags.occ_blocks::cpu.inst 169.317933 # Average occupied blocks per requestor 699system.cpu.l2cache.tags.occ_blocks::cpu.data 31.839972 # Average occupied blocks per requestor 700system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005167 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::cpu.data 0.000972 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_percent::total 0.006139 # Average percentage of cache occupancy 703system.cpu.l2cache.tags.occ_task_id_blocks::1024 397 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::0 213 # Occupied blocks per task id 705system.cpu.l2cache.tags.age_task_id_blocks_1024::1 184 # Occupied blocks per task id 706system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012115 # Percentage of cache occupancy per task id 707system.cpu.l2cache.tags.tag_accesses 4060 # Number of tag accesses 708system.cpu.l2cache.tags.data_accesses 4060 # Number of data accesses 709system.cpu.l2cache.ReadReq_hits::cpu.inst 6 # number of ReadReq hits 710system.cpu.l2cache.ReadReq_hits::cpu.data 1 # number of ReadReq hits 711system.cpu.l2cache.ReadReq_hits::total 7 # number of ReadReq hits 712system.cpu.l2cache.demand_hits::cpu.inst 6 # number of demand (read+write) hits 713system.cpu.l2cache.demand_hits::cpu.data 1 # number of demand (read+write) hits 714system.cpu.l2cache.demand_hits::total 7 # number of demand (read+write) hits 715system.cpu.l2cache.overall_hits::cpu.inst 6 # number of overall hits 716system.cpu.l2cache.overall_hits::cpu.data 1 # number of overall hits 717system.cpu.l2cache.overall_hits::total 7 # number of overall hits 718system.cpu.l2cache.ReadReq_misses::cpu.inst 344 # number of ReadReq misses 719system.cpu.l2cache.ReadReq_misses::cpu.data 54 # number of ReadReq misses 720system.cpu.l2cache.ReadReq_misses::total 398 # number of ReadReq misses 721system.cpu.l2cache.ReadExReq_misses::cpu.data 47 # number of ReadExReq misses 722system.cpu.l2cache.ReadExReq_misses::total 47 # number of ReadExReq misses 723system.cpu.l2cache.demand_misses::cpu.inst 344 # number of demand (read+write) misses 724system.cpu.l2cache.demand_misses::cpu.data 101 # number of demand (read+write) misses 725system.cpu.l2cache.demand_misses::total 445 # number of demand (read+write) misses 726system.cpu.l2cache.overall_misses::cpu.inst 344 # number of overall misses 727system.cpu.l2cache.overall_misses::cpu.data 101 # number of overall misses 728system.cpu.l2cache.overall_misses::total 445 # number of overall misses 729system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23649250 # number of ReadReq miss cycles 730system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4137750 # number of ReadReq miss cycles 731system.cpu.l2cache.ReadReq_miss_latency::total 27787000 # number of ReadReq miss cycles 732system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3745250 # number of ReadExReq miss cycles 733system.cpu.l2cache.ReadExReq_miss_latency::total 3745250 # number of ReadExReq miss cycles 734system.cpu.l2cache.demand_miss_latency::cpu.inst 23649250 # number of demand (read+write) miss cycles 735system.cpu.l2cache.demand_miss_latency::cpu.data 7883000 # number of demand (read+write) miss cycles 736system.cpu.l2cache.demand_miss_latency::total 31532250 # number of demand (read+write) miss cycles 737system.cpu.l2cache.overall_miss_latency::cpu.inst 23649250 # number of overall miss cycles 738system.cpu.l2cache.overall_miss_latency::cpu.data 7883000 # number of overall miss cycles 739system.cpu.l2cache.overall_miss_latency::total 31532250 # number of overall miss cycles 740system.cpu.l2cache.ReadReq_accesses::cpu.inst 350 # number of ReadReq accesses(hits+misses) 741system.cpu.l2cache.ReadReq_accesses::cpu.data 55 # number of ReadReq accesses(hits+misses) 742system.cpu.l2cache.ReadReq_accesses::total 405 # number of ReadReq accesses(hits+misses) 743system.cpu.l2cache.ReadExReq_accesses::cpu.data 47 # number of ReadExReq accesses(hits+misses) 744system.cpu.l2cache.ReadExReq_accesses::total 47 # number of ReadExReq accesses(hits+misses) 745system.cpu.l2cache.demand_accesses::cpu.inst 350 # number of demand (read+write) accesses 746system.cpu.l2cache.demand_accesses::cpu.data 102 # number of demand (read+write) accesses 747system.cpu.l2cache.demand_accesses::total 452 # number of demand (read+write) accesses 748system.cpu.l2cache.overall_accesses::cpu.inst 350 # number of overall (read+write) accesses 749system.cpu.l2cache.overall_accesses::cpu.data 102 # number of overall (read+write) accesses 750system.cpu.l2cache.overall_accesses::total 452 # number of overall (read+write) accesses 751system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.982857 # miss rate for ReadReq accesses 752system.cpu.l2cache.ReadReq_miss_rate::cpu.data 0.981818 # miss rate for ReadReq accesses 753system.cpu.l2cache.ReadReq_miss_rate::total 0.982716 # miss rate for ReadReq accesses 754system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 755system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 756system.cpu.l2cache.demand_miss_rate::cpu.inst 0.982857 # miss rate for demand accesses 757system.cpu.l2cache.demand_miss_rate::cpu.data 0.990196 # miss rate for demand accesses 758system.cpu.l2cache.demand_miss_rate::total 0.984513 # miss rate for demand accesses 759system.cpu.l2cache.overall_miss_rate::cpu.inst 0.982857 # miss rate for overall accesses 760system.cpu.l2cache.overall_miss_rate::cpu.data 0.990196 # miss rate for overall accesses 761system.cpu.l2cache.overall_miss_rate::total 0.984513 # miss rate for overall accesses 762system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 68747.819767 # average ReadReq miss latency 763system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 76625 # average ReadReq miss latency 764system.cpu.l2cache.ReadReq_avg_miss_latency::total 69816.582915 # average ReadReq miss latency 765system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79686.170213 # average ReadExReq miss latency 766system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79686.170213 # average ReadExReq miss latency 767system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 768system.cpu.l2cache.demand_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 769system.cpu.l2cache.demand_avg_miss_latency::total 70858.988764 # average overall miss latency 770system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 68747.819767 # average overall miss latency 771system.cpu.l2cache.overall_avg_miss_latency::cpu.data 78049.504950 # average overall miss latency 772system.cpu.l2cache.overall_avg_miss_latency::total 70858.988764 # average overall miss latency 773system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 774system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 775system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 776system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 777system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 778system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 779system.cpu.l2cache.fast_writes 0 # number of fast writes performed 780system.cpu.l2cache.cache_copies 0 # number of cache copies performed 781system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 344 # number of ReadReq MSHR misses 782system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 54 # number of ReadReq MSHR misses 783system.cpu.l2cache.ReadReq_mshr_misses::total 398 # number of ReadReq MSHR misses 784system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 47 # number of ReadExReq MSHR misses 785system.cpu.l2cache.ReadExReq_mshr_misses::total 47 # number of ReadExReq MSHR misses 786system.cpu.l2cache.demand_mshr_misses::cpu.inst 344 # number of demand (read+write) MSHR misses 787system.cpu.l2cache.demand_mshr_misses::cpu.data 101 # number of demand (read+write) MSHR misses 788system.cpu.l2cache.demand_mshr_misses::total 445 # number of demand (read+write) MSHR misses 789system.cpu.l2cache.overall_mshr_misses::cpu.inst 344 # number of overall MSHR misses 790system.cpu.l2cache.overall_mshr_misses::cpu.data 101 # number of overall MSHR misses 791system.cpu.l2cache.overall_mshr_misses::total 445 # number of overall MSHR misses 792system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19325250 # number of ReadReq MSHR miss cycles 793system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3474750 # number of ReadReq MSHR miss cycles 794system.cpu.l2cache.ReadReq_mshr_miss_latency::total 22800000 # number of ReadReq MSHR miss cycles 795system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3169250 # number of ReadExReq MSHR miss cycles 796system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3169250 # number of ReadExReq MSHR miss cycles 797system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19325250 # number of demand (read+write) MSHR miss cycles 798system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6644000 # number of demand (read+write) MSHR miss cycles 799system.cpu.l2cache.demand_mshr_miss_latency::total 25969250 # number of demand (read+write) MSHR miss cycles 800system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19325250 # number of overall MSHR miss cycles 801system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6644000 # number of overall MSHR miss cycles 802system.cpu.l2cache.overall_mshr_miss_latency::total 25969250 # number of overall MSHR miss cycles 803system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for ReadReq accesses 804system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 0.981818 # mshr miss rate for ReadReq accesses 805system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.982716 # mshr miss rate for ReadReq accesses 806system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 807system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 808system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for demand accesses 809system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for demand accesses 810system.cpu.l2cache.demand_mshr_miss_rate::total 0.984513 # mshr miss rate for demand accesses 811system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.982857 # mshr miss rate for overall accesses 812system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 0.990196 # mshr miss rate for overall accesses 813system.cpu.l2cache.overall_mshr_miss_rate::total 0.984513 # mshr miss rate for overall accesses 814system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 56178.052326 # average ReadReq mshr miss latency 815system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64347.222222 # average ReadReq mshr miss latency 816system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 57286.432161 # average ReadReq mshr miss latency 817system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67430.851064 # average ReadExReq mshr miss latency 818system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67430.851064 # average ReadExReq mshr miss latency 819system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 820system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 821system.cpu.l2cache.demand_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 822system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 56178.052326 # average overall mshr miss latency 823system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 65782.178218 # average overall mshr miss latency 824system.cpu.l2cache.overall_avg_mshr_miss_latency::total 58357.865169 # average overall mshr miss latency 825system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 826system.cpu.dcache.tags.replacements 0 # number of replacements 827system.cpu.dcache.tags.tagsinuse 64.061622 # Cycle average of tags in use 828system.cpu.dcache.tags.total_refs 2261 # Total number of references to valid blocks. 829system.cpu.dcache.tags.sampled_refs 102 # Sample count of references to valid blocks. 830system.cpu.dcache.tags.avg_refs 22.166667 # Average number of references to valid blocks. 831system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 832system.cpu.dcache.tags.occ_blocks::cpu.data 64.061622 # Average occupied blocks per requestor 833system.cpu.dcache.tags.occ_percent::cpu.data 0.015640 # Average percentage of cache occupancy 834system.cpu.dcache.tags.occ_percent::total 0.015640 # Average percentage of cache occupancy 835system.cpu.dcache.tags.occ_task_id_blocks::1024 102 # Occupied blocks per task id 836system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 837system.cpu.dcache.tags.age_task_id_blocks_1024::1 64 # Occupied blocks per task id 838system.cpu.dcache.tags.occ_task_id_percent::1024 0.024902 # Percentage of cache occupancy per task id 839system.cpu.dcache.tags.tag_accesses 5528 # Number of tag accesses 840system.cpu.dcache.tags.data_accesses 5528 # Number of data accesses 841system.cpu.dcache.ReadReq_hits::cpu.data 1554 # number of ReadReq hits 842system.cpu.dcache.ReadReq_hits::total 1554 # number of ReadReq hits 843system.cpu.dcache.WriteReq_hits::cpu.data 707 # number of WriteReq hits 844system.cpu.dcache.WriteReq_hits::total 707 # number of WriteReq hits 845system.cpu.dcache.demand_hits::cpu.data 2261 # number of demand (read+write) hits 846system.cpu.dcache.demand_hits::total 2261 # number of demand (read+write) hits 847system.cpu.dcache.overall_hits::cpu.data 2261 # number of overall hits 848system.cpu.dcache.overall_hits::total 2261 # number of overall hits 849system.cpu.dcache.ReadReq_misses::cpu.data 113 # number of ReadReq misses 850system.cpu.dcache.ReadReq_misses::total 113 # number of ReadReq misses 851system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses 852system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses 853system.cpu.dcache.demand_misses::cpu.data 452 # number of demand (read+write) misses 854system.cpu.dcache.demand_misses::total 452 # number of demand (read+write) misses 855system.cpu.dcache.overall_misses::cpu.data 452 # number of overall misses 856system.cpu.dcache.overall_misses::total 452 # number of overall misses 857system.cpu.dcache.ReadReq_miss_latency::cpu.data 8122250 # number of ReadReq miss cycles 858system.cpu.dcache.ReadReq_miss_latency::total 8122250 # number of ReadReq miss cycles 859system.cpu.dcache.WriteReq_miss_latency::cpu.data 22327496 # number of WriteReq miss cycles 860system.cpu.dcache.WriteReq_miss_latency::total 22327496 # number of WriteReq miss cycles 861system.cpu.dcache.demand_miss_latency::cpu.data 30449746 # number of demand (read+write) miss cycles 862system.cpu.dcache.demand_miss_latency::total 30449746 # number of demand (read+write) miss cycles 863system.cpu.dcache.overall_miss_latency::cpu.data 30449746 # number of overall miss cycles 864system.cpu.dcache.overall_miss_latency::total 30449746 # number of overall miss cycles 865system.cpu.dcache.ReadReq_accesses::cpu.data 1667 # number of ReadReq accesses(hits+misses) 866system.cpu.dcache.ReadReq_accesses::total 1667 # number of ReadReq accesses(hits+misses) 867system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses) 868system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses) 869system.cpu.dcache.demand_accesses::cpu.data 2713 # number of demand (read+write) accesses 870system.cpu.dcache.demand_accesses::total 2713 # number of demand (read+write) accesses 871system.cpu.dcache.overall_accesses::cpu.data 2713 # number of overall (read+write) accesses 872system.cpu.dcache.overall_accesses::total 2713 # number of overall (read+write) accesses 873system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.067786 # miss rate for ReadReq accesses 874system.cpu.dcache.ReadReq_miss_rate::total 0.067786 # miss rate for ReadReq accesses 875system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.324092 # miss rate for WriteReq accesses 876system.cpu.dcache.WriteReq_miss_rate::total 0.324092 # miss rate for WriteReq accesses 877system.cpu.dcache.demand_miss_rate::cpu.data 0.166605 # miss rate for demand accesses 878system.cpu.dcache.demand_miss_rate::total 0.166605 # miss rate for demand accesses 879system.cpu.dcache.overall_miss_rate::cpu.data 0.166605 # miss rate for overall accesses 880system.cpu.dcache.overall_miss_rate::total 0.166605 # miss rate for overall accesses 881system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71878.318584 # average ReadReq miss latency 882system.cpu.dcache.ReadReq_avg_miss_latency::total 71878.318584 # average ReadReq miss latency 883system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 65862.820059 # average WriteReq miss latency 884system.cpu.dcache.WriteReq_avg_miss_latency::total 65862.820059 # average WriteReq miss latency 885system.cpu.dcache.demand_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 886system.cpu.dcache.demand_avg_miss_latency::total 67366.694690 # average overall miss latency 887system.cpu.dcache.overall_avg_miss_latency::cpu.data 67366.694690 # average overall miss latency 888system.cpu.dcache.overall_avg_miss_latency::total 67366.694690 # average overall miss latency 889system.cpu.dcache.blocked_cycles::no_mshrs 597 # number of cycles access was blocked 890system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 891system.cpu.dcache.blocked::no_mshrs 6 # number of cycles access was blocked 892system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 893system.cpu.dcache.avg_blocked_cycles::no_mshrs 99.500000 # average number of cycles each access was blocked 894system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 895system.cpu.dcache.fast_writes 0 # number of fast writes performed 896system.cpu.dcache.cache_copies 0 # number of cache copies performed 897system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 898system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 899system.cpu.dcache.WriteReq_mshr_hits::cpu.data 292 # number of WriteReq MSHR hits 900system.cpu.dcache.WriteReq_mshr_hits::total 292 # number of WriteReq MSHR hits 901system.cpu.dcache.demand_mshr_hits::cpu.data 350 # number of demand (read+write) MSHR hits 902system.cpu.dcache.demand_mshr_hits::total 350 # number of demand (read+write) MSHR hits 903system.cpu.dcache.overall_mshr_hits::cpu.data 350 # number of overall MSHR hits 904system.cpu.dcache.overall_mshr_hits::total 350 # number of overall MSHR hits 905system.cpu.dcache.ReadReq_mshr_misses::cpu.data 55 # number of ReadReq MSHR misses 906system.cpu.dcache.ReadReq_mshr_misses::total 55 # number of ReadReq MSHR misses 907system.cpu.dcache.WriteReq_mshr_misses::cpu.data 47 # number of WriteReq MSHR misses 908system.cpu.dcache.WriteReq_mshr_misses::total 47 # number of WriteReq MSHR misses 909system.cpu.dcache.demand_mshr_misses::cpu.data 102 # number of demand (read+write) MSHR misses 910system.cpu.dcache.demand_mshr_misses::total 102 # number of demand (read+write) MSHR misses 911system.cpu.dcache.overall_mshr_misses::cpu.data 102 # number of overall MSHR misses 912system.cpu.dcache.overall_mshr_misses::total 102 # number of overall MSHR misses 913system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4203250 # number of ReadReq MSHR miss cycles 914system.cpu.dcache.ReadReq_mshr_miss_latency::total 4203250 # number of ReadReq MSHR miss cycles 915system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3795248 # number of WriteReq MSHR miss cycles 916system.cpu.dcache.WriteReq_mshr_miss_latency::total 3795248 # number of WriteReq MSHR miss cycles 917system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7998498 # number of demand (read+write) MSHR miss cycles 918system.cpu.dcache.demand_mshr_miss_latency::total 7998498 # number of demand (read+write) MSHR miss cycles 919system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7998498 # number of overall MSHR miss cycles 920system.cpu.dcache.overall_mshr_miss_latency::total 7998498 # number of overall MSHR miss cycles 921system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032993 # mshr miss rate for ReadReq accesses 922system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.032993 # mshr miss rate for ReadReq accesses 923system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.044933 # mshr miss rate for WriteReq accesses 924system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.044933 # mshr miss rate for WriteReq accesses 925system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for demand accesses 926system.cpu.dcache.demand_mshr_miss_rate::total 0.037597 # mshr miss rate for demand accesses 927system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037597 # mshr miss rate for overall accesses 928system.cpu.dcache.overall_mshr_miss_rate::total 0.037597 # mshr miss rate for overall accesses 929system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 76422.727273 # average ReadReq mshr miss latency 930system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 76422.727273 # average ReadReq mshr miss latency 931system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80749.957447 # average WriteReq mshr miss latency 932system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80749.957447 # average WriteReq mshr miss latency 933system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 934system.cpu.dcache.demand_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 935system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 78416.647059 # average overall mshr miss latency 936system.cpu.dcache.overall_avg_mshr_miss_latency::total 78416.647059 # average overall mshr miss latency 937system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 938 939---------- End Simulation Statistics ----------