1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000011 # Number of seconds simulated
4sim_ticks 11243500 # Number of ticks simulated
5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 73653 # Simulator instruction rate (inst/s)
8host_op_rate 73641 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 142731766 # Simulator tick rate (ticks/s)
10host_mem_usage 211540 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host
12sim_insts 5800 # Number of instructions simulated
13sim_ops 5800 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28736 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 449 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.read_hits 0 # DTB read hits
24system.cpu.dtb.read_misses 0 # DTB read misses
25system.cpu.dtb.read_accesses 0 # DTB read accesses
26system.cpu.dtb.write_hits 0 # DTB write hits
27system.cpu.dtb.write_misses 0 # DTB write misses
28system.cpu.dtb.write_accesses 0 # DTB write accesses
29system.cpu.dtb.hits 0 # DTB hits
30system.cpu.dtb.misses 0 # DTB misses
--- 303 unchanged lines hidden (view full) ---
334system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles
335system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses)
336system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses)
337system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses
338system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses
339system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses
340system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses
341system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses
342system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses
343system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses
344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency
345system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency
346system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency
347system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
348system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
349system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
350system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
351system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
352system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
353system.cpu.icache.fast_writes 0 # number of fast writes performed
354system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
366system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses
367system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles
368system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles
369system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles
370system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles
371system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles
372system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles
373system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses
374system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses
375system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses
376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency
377system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency
378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency
379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
380system.cpu.dcache.replacements 0 # number of replacements
381system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use
382system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks.
383system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks.
384system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks.
385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
386system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
414system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses)
415system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
416system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
417system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses
418system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses
419system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses
420system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses
421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses
422system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses
423system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses
424system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses
425system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency
426system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency
427system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency
428system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency
429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
430system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
432system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
433system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
434system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
435system.cpu.dcache.fast_writes 0 # number of fast writes performed
436system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 17 unchanged lines hidden (view full) ---
454system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles
455system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles
456system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles
457system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles
458system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles
459system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles
460system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles
461system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses
462system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses
463system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses
464system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses
465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency
466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency
467system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency
468system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency
469system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
470system.cpu.l2cache.replacements 0 # number of replacements
471system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use
472system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
473system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
474system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks.
475system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
476system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
514system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
522system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
523system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
527system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency
530system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency
532system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency
534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
540system.cpu.l2cache.fast_writes 0 # number of fast writes performed
541system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 16 unchanged lines hidden (view full) ---
558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles
559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles
560system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles
561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles
562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles
563system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles
564system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses
565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
566system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
567system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses
568system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
569system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses
570system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency
572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency
573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency
574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency
575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency
576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency
577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency
578system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
579
580---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000011 # Number of seconds simulated
4sim_ticks 11243500 # Number of ticks simulated
5final_tick 11243500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 73653 # Simulator instruction rate (inst/s)
8host_op_rate 73641 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 142731766 # Simulator tick rate (ticks/s)
10host_mem_usage 211540 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host
12sim_insts 5800 # Number of instructions simulated
13sim_ops 5800 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28736 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 22400 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 449 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 2555787789 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 1992262196 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 2555787789 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.read_hits 0 # DTB read hits
24system.cpu.dtb.read_misses 0 # DTB read misses
25system.cpu.dtb.read_accesses 0 # DTB read accesses
26system.cpu.dtb.write_hits 0 # DTB write hits
27system.cpu.dtb.write_misses 0 # DTB write misses
28system.cpu.dtb.write_accesses 0 # DTB write accesses
29system.cpu.dtb.hits 0 # DTB hits
30system.cpu.dtb.misses 0 # DTB misses
--- 303 unchanged lines hidden (view full) ---
334system.cpu.icache.overall_miss_latency::total 15734000 # number of overall miss cycles
335system.cpu.icache.ReadReq_accesses::cpu.inst 1899 # number of ReadReq accesses(hits+misses)
336system.cpu.icache.ReadReq_accesses::total 1899 # number of ReadReq accesses(hits+misses)
337system.cpu.icache.demand_accesses::cpu.inst 1899 # number of demand (read+write) accesses
338system.cpu.icache.demand_accesses::total 1899 # number of demand (read+write) accesses
339system.cpu.icache.overall_accesses::cpu.inst 1899 # number of overall (read+write) accesses
340system.cpu.icache.overall_accesses::total 1899 # number of overall (read+write) accesses
341system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.230121 # miss rate for ReadReq accesses
342system.cpu.icache.demand_miss_rate::cpu.inst 0.230121 # miss rate for demand accesses
343system.cpu.icache.overall_miss_rate::cpu.inst 0.230121 # miss rate for overall accesses
344system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36004.576659 # average ReadReq miss latency
345system.cpu.icache.demand_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency
346system.cpu.icache.overall_avg_miss_latency::cpu.inst 36004.576659 # average overall miss latency
347system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
348system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
349system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
350system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
351system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
352system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
353system.cpu.icache.fast_writes 0 # number of fast writes performed
354system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 11 unchanged lines hidden (view full) ---
366system.cpu.icache.overall_mshr_misses::total 355 # number of overall MSHR misses
367system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12417500 # number of ReadReq MSHR miss cycles
368system.cpu.icache.ReadReq_mshr_miss_latency::total 12417500 # number of ReadReq MSHR miss cycles
369system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12417500 # number of demand (read+write) MSHR miss cycles
370system.cpu.icache.demand_mshr_miss_latency::total 12417500 # number of demand (read+write) MSHR miss cycles
371system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12417500 # number of overall MSHR miss cycles
372system.cpu.icache.overall_mshr_miss_latency::total 12417500 # number of overall MSHR miss cycles
373system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for ReadReq accesses
374system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for demand accesses
375system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.186940 # mshr miss rate for overall accesses
376system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 34978.873239 # average ReadReq mshr miss latency
377system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency
378system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 34978.873239 # average overall mshr miss latency
379system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
380system.cpu.dcache.replacements 0 # number of replacements
381system.cpu.dcache.tagsinuse 62.512522 # Cycle average of tags in use
382system.cpu.dcache.total_refs 2216 # Total number of references to valid blocks.
383system.cpu.dcache.sampled_refs 99 # Sample count of references to valid blocks.
384system.cpu.dcache.avg_refs 22.383838 # Average number of references to valid blocks.
385system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
386system.cpu.dcache.occ_blocks::cpu.data 62.512522 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
414system.cpu.dcache.ReadReq_accesses::total 1569 # number of ReadReq accesses(hits+misses)
415system.cpu.dcache.WriteReq_accesses::cpu.data 1046 # number of WriteReq accesses(hits+misses)
416system.cpu.dcache.WriteReq_accesses::total 1046 # number of WriteReq accesses(hits+misses)
417system.cpu.dcache.demand_accesses::cpu.data 2615 # number of demand (read+write) accesses
418system.cpu.dcache.demand_accesses::total 2615 # number of demand (read+write) accesses
419system.cpu.dcache.overall_accesses::cpu.data 2615 # number of overall (read+write) accesses
420system.cpu.dcache.overall_accesses::total 2615 # number of overall (read+write) accesses
421system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.052900 # miss rate for ReadReq accesses
422system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.302103 # miss rate for WriteReq accesses
423system.cpu.dcache.demand_miss_rate::cpu.data 0.152581 # miss rate for demand accesses
424system.cpu.dcache.overall_miss_rate::cpu.data 0.152581 # miss rate for overall accesses
425system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36060.240964 # average ReadReq miss latency
426system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33504.746835 # average WriteReq miss latency
427system.cpu.dcache.demand_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency
428system.cpu.dcache.overall_avg_miss_latency::cpu.data 34036.340852 # average overall miss latency
429system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
430system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
431system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
432system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
433system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
434system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
435system.cpu.dcache.fast_writes 0 # number of fast writes performed
436system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 17 unchanged lines hidden (view full) ---
454system.cpu.dcache.ReadReq_mshr_miss_latency::total 1819500 # number of ReadReq MSHR miss cycles
455system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1750500 # number of WriteReq MSHR miss cycles
456system.cpu.dcache.WriteReq_mshr_miss_latency::total 1750500 # number of WriteReq MSHR miss cycles
457system.cpu.dcache.demand_mshr_miss_latency::cpu.data 3570000 # number of demand (read+write) MSHR miss cycles
458system.cpu.dcache.demand_mshr_miss_latency::total 3570000 # number of demand (read+write) MSHR miss cycles
459system.cpu.dcache.overall_mshr_miss_latency::cpu.data 3570000 # number of overall MSHR miss cycles
460system.cpu.dcache.overall_mshr_miss_latency::total 3570000 # number of overall MSHR miss cycles
461system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.032505 # mshr miss rate for ReadReq accesses
462system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.045889 # mshr miss rate for WriteReq accesses
463system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for demand accesses
464system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.037859 # mshr miss rate for overall accesses
465system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35676.470588 # average ReadReq mshr miss latency
466system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36468.750000 # average WriteReq mshr miss latency
467system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency
468system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36060.606061 # average overall mshr miss latency
469system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
470system.cpu.l2cache.replacements 0 # number of replacements
471system.cpu.l2cache.tagsinuse 201.766772 # Cycle average of tags in use
472system.cpu.l2cache.total_refs 5 # Total number of references to valid blocks.
473system.cpu.l2cache.sampled_refs 401 # Sample count of references to valid blocks.
474system.cpu.l2cache.avg_refs 0.012469 # Average number of references to valid blocks.
475system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
476system.cpu.l2cache.occ_blocks::cpu.inst 171.497459 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
514system.cpu.l2cache.demand_accesses::cpu.inst 355 # number of demand (read+write) accesses
515system.cpu.l2cache.demand_accesses::cpu.data 99 # number of demand (read+write) accesses
516system.cpu.l2cache.demand_accesses::total 454 # number of demand (read+write) accesses
517system.cpu.l2cache.overall_accesses::cpu.inst 355 # number of overall (read+write) accesses
518system.cpu.l2cache.overall_accesses::cpu.data 99 # number of overall (read+write) accesses
519system.cpu.l2cache.overall_accesses::total 454 # number of overall (read+write) accesses
520system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.985915 # miss rate for ReadReq accesses
521system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
522system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
523system.cpu.l2cache.demand_miss_rate::cpu.inst 0.985915 # miss rate for demand accesses
524system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
525system.cpu.l2cache.overall_miss_rate::cpu.inst 0.985915 # miss rate for overall accesses
526system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
527system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34372.857143 # average ReadReq miss latency
528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34529.411765 # average ReadReq miss latency
529system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34895.833333 # average ReadExReq miss latency
530system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency
531system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency
532system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34372.857143 # average overall miss latency
533system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34707.070707 # average overall miss latency
534system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
535system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
536system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
537system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
538system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
539system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
540system.cpu.l2cache.fast_writes 0 # number of fast writes performed
541system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 16 unchanged lines hidden (view full) ---
558system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10905000 # number of demand (read+write) MSHR miss cycles
559system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 3121500 # number of demand (read+write) MSHR miss cycles
560system.cpu.l2cache.demand_mshr_miss_latency::total 14026500 # number of demand (read+write) MSHR miss cycles
561system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10905000 # number of overall MSHR miss cycles
562system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 3121500 # number of overall MSHR miss cycles
563system.cpu.l2cache.overall_mshr_miss_latency::total 14026500 # number of overall MSHR miss cycles
564system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for ReadReq accesses
565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
566system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
567system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for demand accesses
568system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
569system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.985915 # mshr miss rate for overall accesses
570system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
571system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31157.142857 # average ReadReq mshr miss latency
572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31382.352941 # average ReadReq mshr miss latency
573system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31687.500000 # average ReadExReq mshr miss latency
574system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency
575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency
576system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31157.142857 # average overall mshr miss latency
577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31530.303030 # average overall mshr miss latency
578system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
579
580---------- End Simulation Statistics ----------