| stats.txt (9055:38f1926fb599) | stats.txt (9096:8971a998190a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 32088000 # Number of ticks simulated 5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000033 # Number of seconds simulated 4sim_ticks 33413000 # Number of ticks simulated 5final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 540307 # Simulator instruction rate (inst/s) 8host_op_rate 539410 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2965678153 # Simulator tick rate (ticks/s) 10host_mem_usage 215020 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host | 7host_inst_rate 168189 # Simulator instruction rate (inst/s) 8host_op_rate 168105 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 963489284 # Simulator tick rate (ticks/s) 10host_mem_usage 219036 # Number of bytes of host memory used 11host_seconds 0.03 # Real time elapsed on the host |
| 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28096 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 439 # Number of read requests responded to by this memory | 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 16system.physmem.bytes_read::total 28096 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 439 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s) |
| 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses 38system.cpu.dtb.accesses 0 # DTB accesses 39system.cpu.itb.read_hits 0 # DTB read hits 40system.cpu.itb.read_misses 0 # DTB read misses 41system.cpu.itb.read_accesses 0 # DTB read accesses 42system.cpu.itb.write_hits 0 # DTB write hits 43system.cpu.itb.write_misses 0 # DTB write misses 44system.cpu.itb.write_accesses 0 # DTB write accesses 45system.cpu.itb.hits 0 # DTB hits 46system.cpu.itb.misses 0 # DTB misses 47system.cpu.itb.accesses 0 # DTB accesses 48system.cpu.workload.num_syscalls 8 # Number of system calls | 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses 38system.cpu.dtb.accesses 0 # DTB accesses 39system.cpu.itb.read_hits 0 # DTB read hits 40system.cpu.itb.read_misses 0 # DTB read misses 41system.cpu.itb.read_accesses 0 # DTB read accesses 42system.cpu.itb.write_hits 0 # DTB write hits 43system.cpu.itb.write_misses 0 # DTB write misses 44system.cpu.itb.write_accesses 0 # DTB write accesses 45system.cpu.itb.hits 0 # DTB hits 46system.cpu.itb.misses 0 # DTB misses 47system.cpu.itb.accesses 0 # DTB accesses 48system.cpu.workload.num_syscalls 8 # Number of system calls |
| 49system.cpu.numCycles 64176 # number of cpu cycles simulated | 49system.cpu.numCycles 66826 # number of cpu cycles simulated |
| 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 5827 # Number of instructions committed 53system.cpu.committedOps 5827 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 56system.cpu.num_func_calls 194 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 58system.cpu.num_int_insts 5126 # number of integer instructions 59system.cpu.num_fp_insts 2 # number of float instructions 60system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 61system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 64system.cpu.num_mem_refs 2090 # number of memory refs 65system.cpu.num_load_insts 1164 # Number of load instructions 66system.cpu.num_store_insts 926 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles | 50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 52system.cpu.committedInsts 5827 # Number of instructions committed 53system.cpu.committedOps 5827 # Number of ops (including micro ops) committed 54system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses 55system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 56system.cpu.num_func_calls 194 # number of times a function call or return occured 57system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls 58system.cpu.num_int_insts 5126 # number of integer instructions 59system.cpu.num_fp_insts 2 # number of float instructions 60system.cpu.num_int_register_reads 7300 # number of times the integer registers were read 61system.cpu.num_int_register_writes 3409 # number of times the integer registers were written 62system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 63system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 64system.cpu.num_mem_refs 2090 # number of memory refs 65system.cpu.num_load_insts 1164 # Number of load instructions 66system.cpu.num_store_insts 926 # Number of store instructions 67system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 68system.cpu.num_busy_cycles 64176 # Number of busy cycles | 68system.cpu.num_busy_cycles 66826 # Number of busy cycles |
| 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.icache.replacements 13 # number of replacements | 69system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 70system.cpu.idle_fraction 0 # Percentage of idle cycles 71system.cpu.icache.replacements 13 # number of replacements |
| 72system.cpu.icache.tagsinuse 132.493866 # Cycle average of tags in use | 72system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use |
| 73system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 74system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 75system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 76system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 73system.cpu.icache.total_refs 5526 # Total number of references to valid blocks. 74system.cpu.icache.sampled_refs 303 # Sample count of references to valid blocks. 75system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks. 76system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 77system.cpu.icache.occ_blocks::cpu.inst 132.493866 # Average occupied blocks per requestor 78system.cpu.icache.occ_percent::cpu.inst 0.064694 # Average percentage of cache occupancy 79system.cpu.icache.occ_percent::total 0.064694 # Average percentage of cache occupancy | 77system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor 78system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy 79system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy |
| 80system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits 81system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits 82system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits 83system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits 84system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits 85system.cpu.icache.overall_hits::total 5526 # number of overall hits 86system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 87system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 142system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 143system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 144system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 145system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 146system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 147system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 148system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 149system.cpu.dcache.replacements 0 # number of replacements | 80system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits 81system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits 82system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits 83system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits 84system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits 85system.cpu.icache.overall_hits::total 5526 # number of overall hits 86system.cpu.icache.ReadReq_misses::cpu.inst 303 # number of ReadReq misses 87system.cpu.icache.ReadReq_misses::total 303 # number of ReadReq misses --- 54 unchanged lines hidden (view full) --- 142system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency 143system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency 144system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 145system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 146system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency 147system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency 148system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 149system.cpu.dcache.replacements 0 # number of replacements |
| 150system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use | 150system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use |
| 151system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 152system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 153system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 154system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 151system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks. 152system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks. 153system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks. 154system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 155system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor 156system.cpu.dcache.occ_percent::cpu.data 0.021352 # Average percentage of cache occupancy 157system.cpu.dcache.occ_percent::total 0.021352 # Average percentage of cache occupancy | 155system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor 156system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy 157system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy |
| 158system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits 159system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits 160system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 161system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 162system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits 163system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits 164system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits 165system.cpu.dcache.overall_hits::total 1951 # number of overall hits --- 74 unchanged lines hidden (view full) --- 240system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 241system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 242system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 243system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 245system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 246system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 247system.cpu.l2cache.replacements 0 # number of replacements | 158system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits 159system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits 160system.cpu.dcache.WriteReq_hits::cpu.data 874 # number of WriteReq hits 161system.cpu.dcache.WriteReq_hits::total 874 # number of WriteReq hits 162system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits 163system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits 164system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits 165system.cpu.dcache.overall_hits::total 1951 # number of overall hits --- 74 unchanged lines hidden (view full) --- 240system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 241system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 242system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 243system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 244system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 245system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 246system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 247system.cpu.l2cache.replacements 0 # number of replacements |
| 248system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use | 248system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use |
| 249system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 250system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 251system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 252system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 249system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks. 250system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks. 251system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks. 252system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 253system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor 254system.cpu.l2cache.occ_blocks::cpu.data 54.207742 # Average occupied blocks per requestor 255system.cpu.l2cache.occ_percent::cpu.inst 0.004084 # Average percentage of cache occupancy 256system.cpu.l2cache.occ_percent::cpu.data 0.001654 # Average percentage of cache occupancy 257system.cpu.l2cache.occ_percent::total 0.005739 # Average percentage of cache occupancy | 253system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor 254system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor 255system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy 256system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy 257system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy |
| 258system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 259system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 260system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 261system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 262system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 263system.cpu.l2cache.overall_hits::total 2 # number of overall hits 264system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 265system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses --- 108 unchanged lines hidden --- | 258system.cpu.l2cache.ReadReq_hits::cpu.inst 2 # number of ReadReq hits 259system.cpu.l2cache.ReadReq_hits::total 2 # number of ReadReq hits 260system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 261system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 262system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 263system.cpu.l2cache.overall_hits::total 2 # number of overall hits 264system.cpu.l2cache.ReadReq_misses::cpu.inst 301 # number of ReadReq misses 265system.cpu.l2cache.ReadReq_misses::cpu.data 87 # number of ReadReq misses --- 108 unchanged lines hidden --- |