| stats.txt (8835:7c68f84d7c4e) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 32088000 # Number of ticks simulated 5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 32088000 # Number of ticks simulated 5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 603210 # Simulator instruction rate (inst/s) 8host_op_rate 602100 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 3309896144 # Simulator tick rate (ticks/s) 10host_mem_usage 209992 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host | 7host_inst_rate 273601 # Simulator instruction rate (inst/s) 8host_op_rate 273420 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1504754975 # Simulator tick rate (ticks/s) 10host_mem_usage 214572 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 439 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 79 unchanged lines hidden (view full) --- 99system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses 100system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 102system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 103system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 5827 # Number of instructions simulated 13sim_ops 5827 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 28096 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 439 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 79 unchanged lines hidden (view full) --- 99system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses 100system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency 101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 102system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency 103system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 104system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 107system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 108system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 107system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 108system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 109system.cpu.icache.fast_writes 0 # number of fast writes performed 110system.cpu.icache.cache_copies 0 # number of cache copies performed 111system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 112system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 113system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 114system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 115system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 116system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 177system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 109system.cpu.icache.fast_writes 0 # number of fast writes performed 110system.cpu.icache.cache_copies 0 # number of cache copies performed 111system.cpu.icache.ReadReq_mshr_misses::cpu.inst 303 # number of ReadReq MSHR misses 112system.cpu.icache.ReadReq_mshr_misses::total 303 # number of ReadReq MSHR misses 113system.cpu.icache.demand_mshr_misses::cpu.inst 303 # number of demand (read+write) MSHR misses 114system.cpu.icache.demand_mshr_misses::total 303 # number of demand (read+write) MSHR misses 115system.cpu.icache.overall_mshr_misses::cpu.inst 303 # number of overall MSHR misses 116system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses --- 58 unchanged lines hidden (view full) --- 175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency 176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency 177system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency 178system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency 179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 183system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 183system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 184system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 185system.cpu.dcache.fast_writes 0 # number of fast writes performed 186system.cpu.dcache.cache_copies 0 # number of cache copies performed 187system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 188system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 276system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 185system.cpu.dcache.fast_writes 0 # number of fast writes performed 186system.cpu.dcache.cache_copies 0 # number of cache copies performed 187system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 188system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 189system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 190system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 191system.cpu.dcache.demand_mshr_misses::cpu.data 138 # number of demand (read+write) MSHR misses 192system.cpu.dcache.demand_mshr_misses::total 138 # number of demand (read+write) MSHR misses --- 79 unchanged lines hidden (view full) --- 272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 276system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 277system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 278system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 279system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 280system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 281system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 280system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 281system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 282system.cpu.l2cache.fast_writes 0 # number of fast writes performed 283system.cpu.l2cache.cache_copies 0 # number of cache copies performed 284system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 285system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 286system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 287system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 288system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 289system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 282system.cpu.l2cache.fast_writes 0 # number of fast writes performed 283system.cpu.l2cache.cache_copies 0 # number of cache copies performed 284system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 301 # number of ReadReq MSHR misses 285system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 286system.cpu.l2cache.ReadReq_mshr_misses::total 388 # number of ReadReq MSHR misses 287system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 288system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 289system.cpu.l2cache.demand_mshr_misses::cpu.inst 301 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |