| stats.txt (11570:4aac82f10951) | stats.txt (11606:6b749761c398) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000034 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000034 # Number of seconds simulated |
| 4sim_ticks 33932500 # Number of ticks simulated 5final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 34362500 # Number of ticks simulated 5final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 18620 # Simulator instruction rate (inst/s) 8host_op_rate 18619 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 111991731 # Simulator tick rate (ticks/s) 10host_mem_usage 246380 # Number of bytes of host memory used 11host_seconds 0.30 # Real time elapsed on the host | 7host_inst_rate 251821 # Simulator instruction rate (inst/s) 8host_op_rate 251667 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1532173253 # Simulator tick rate (ticks/s) 10host_mem_usage 250252 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host |
| 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 430 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 430 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 25system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s) 33system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.read_hits 0 # DTB read hits 36system.cpu.dtb.read_misses 0 # DTB read misses 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_hits 0 # DTB write hits 39system.cpu.dtb.write_misses 0 # DTB write misses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_accesses 0 # DTB write accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 7 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.read_hits 0 # DTB read hits 36system.cpu.dtb.read_misses 0 # DTB read misses 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_hits 0 # DTB write hits 39system.cpu.dtb.write_misses 0 # DTB write misses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_accesses 0 # DTB write accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 7 # Number of system calls |
| 54system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states 55system.cpu.numCycles 67865 # number of cpu cycles simulated | 54system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states 55system.cpu.numCycles 68725 # number of cpu cycles simulated |
| 56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58system.cpu.committedInsts 5641 # Number of instructions committed 59system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 60system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 61system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 62system.cpu.num_func_calls 191 # number of times a function call or return occured 63system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 64system.cpu.num_int_insts 4957 # number of integer instructions 65system.cpu.num_fp_insts 2 # number of float instructions 66system.cpu.num_int_register_reads 7072 # number of times the integer registers were read 67system.cpu.num_int_register_writes 3291 # number of times the integer registers were written 68system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 69system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 70system.cpu.num_mem_refs 2037 # number of memory refs 71system.cpu.num_load_insts 1135 # Number of load instructions 72system.cpu.num_store_insts 902 # Number of store instructions 73system.cpu.num_idle_cycles 0 # Number of idle cycles | 56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58system.cpu.committedInsts 5641 # Number of instructions committed 59system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 60system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 61system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 62system.cpu.num_func_calls 191 # number of times a function call or return occured 63system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 64system.cpu.num_int_insts 4957 # number of integer instructions 65system.cpu.num_fp_insts 2 # number of float instructions 66system.cpu.num_int_register_reads 7072 # number of times the integer registers were read 67system.cpu.num_int_register_writes 3291 # number of times the integer registers were written 68system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 69system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 70system.cpu.num_mem_refs 2037 # number of memory refs 71system.cpu.num_load_insts 1135 # Number of load instructions 72system.cpu.num_store_insts 902 # Number of store instructions 73system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 74system.cpu.num_busy_cycles 67865 # Number of busy cycles | 74system.cpu.num_busy_cycles 68725 # Number of busy cycles |
| 75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 76system.cpu.idle_fraction 0 # Percentage of idle cycles 77system.cpu.Branches 886 # Number of branches fetched 78system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 79system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 80system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 81system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 82system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 105system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 106system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 107system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 108system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 109system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 110system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 112system.cpu.op_class::total 5642 # Class of executed instruction | 75system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 76system.cpu.idle_fraction 0 # Percentage of idle cycles 77system.cpu.Branches 886 # Number of branches fetched 78system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 79system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 80system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 81system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 82system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 105system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 106system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 107system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 108system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 109system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 110system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 112system.cpu.op_class::total 5642 # Class of executed instruction |
| 113system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 113system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 114system.cpu.dcache.tags.replacements 0 # number of replacements | 114system.cpu.dcache.tags.replacements 0 # number of replacements |
| 115system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use | 115system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use |
| 116system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 117system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 118system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 119system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 116system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 117system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 118system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 119system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 120system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor 121system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy | 120system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor 121system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy |
| 123system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 126system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 127system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 128system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses | 123system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 126system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 127system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 128system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses |
| 129system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 129system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 130system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 131system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 132system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 133system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 134system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 135system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 136system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 137system.cpu.dcache.overall_hits::total 1899 # number of overall hits 138system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 139system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 140system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 141system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 142system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 143system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 144system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 145system.cpu.dcache.overall_misses::total 137 # number of overall misses | 130system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 131system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 132system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 133system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 134system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 135system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 136system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 137system.cpu.dcache.overall_hits::total 1899 # number of overall hits 138system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 139system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 140system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 141system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 142system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 143system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 144system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 145system.cpu.dcache.overall_misses::total 137 # number of overall misses |
| 146system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles 147system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles 148system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles 149system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles 150system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles 151system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles 152system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles 153system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles | 146system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles 147system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles 148system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles 149system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles 150system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles 151system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles 152system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles 153system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles |
| 154system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) 155system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) 156system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 157system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 158system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses 159system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses 160system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses 161system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses 162system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses 163system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses 164system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 165system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 166system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses 167system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses 168system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses | 154system.cpu.dcache.ReadReq_accesses::cpu.data 1135 # number of ReadReq accesses(hits+misses) 155system.cpu.dcache.ReadReq_accesses::total 1135 # number of ReadReq accesses(hits+misses) 156system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 157system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 158system.cpu.dcache.demand_accesses::cpu.data 2036 # number of demand (read+write) accesses 159system.cpu.dcache.demand_accesses::total 2036 # number of demand (read+write) accesses 160system.cpu.dcache.overall_accesses::cpu.data 2036 # number of overall (read+write) accesses 161system.cpu.dcache.overall_accesses::total 2036 # number of overall (read+write) accesses 162system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076652 # miss rate for ReadReq accesses 163system.cpu.dcache.ReadReq_miss_rate::total 0.076652 # miss rate for ReadReq accesses 164system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 165system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 166system.cpu.dcache.demand_miss_rate::cpu.data 0.067289 # miss rate for demand accesses 167system.cpu.dcache.demand_miss_rate::total 0.067289 # miss rate for demand accesses 168system.cpu.dcache.overall_miss_rate::cpu.data 0.067289 # miss rate for overall accesses 169system.cpu.dcache.overall_miss_rate::total 0.067289 # miss rate for overall accesses |
| 170system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency 171system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency 172system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency 173system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency 174system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency 175system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency 176system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency 177system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency | 170system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency 171system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency 172system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency 173system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency 174system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency 175system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency 176system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency 177system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency |
| 178system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 184system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 185system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 188system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 189system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 190system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 191system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses | 178system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 179system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 180system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 181system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 182system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 183system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 184system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 185system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 186system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 187system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 188system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 189system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 190system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 191system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses |
| 192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles 199system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles | 192system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles 193system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles 194system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles 195system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles 196system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles 197system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles 198system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles 199system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles |
| 200system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 204system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses 205system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses 206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses 207system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses | 200system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076652 # mshr miss rate for ReadReq accesses 201system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076652 # mshr miss rate for ReadReq accesses 202system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 203system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 204system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for demand accesses 205system.cpu.dcache.demand_mshr_miss_rate::total 0.067289 # mshr miss rate for demand accesses 206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067289 # mshr miss rate for overall accesses 207system.cpu.dcache.overall_mshr_miss_rate::total 0.067289 # mshr miss rate for overall accesses |
| 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency 212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency 216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 217system.cpu.icache.tags.replacements 13 # number of replacements | 217system.cpu.icache.tags.replacements 13 # number of replacements |
| 218system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use | 218system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use |
| 219system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 219system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 223system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy | 223system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy |
| 226system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 229system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 230system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 231system.cpu.icache.tags.data_accesses 11581 # Number of data accesses | 226system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 229system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 230system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 231system.cpu.icache.tags.data_accesses 11581 # Number of data accesses |
| 232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 233system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 234system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 235system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 236system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 237system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 238system.cpu.icache.overall_hits::total 5348 # number of overall hits 239system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 240system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 241system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 242system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 243system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 244system.cpu.icache.overall_misses::total 295 # number of overall misses | 233system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 234system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 235system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 236system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 237system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 238system.cpu.icache.overall_hits::total 5348 # number of overall hits 239system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 240system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 241system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 242system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 243system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 244system.cpu.icache.overall_misses::total 295 # number of overall misses |
| 245system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles 246system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles 247system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles 248system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles 249system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles 250system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles | 245system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles 246system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles 247system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles 248system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles 249system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles 250system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles |
| 251system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) 252system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) 253system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses 254system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses 255system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses 256system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses 257system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses 258system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses 259system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses 260system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses 261system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses 262system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses | 251system.cpu.icache.ReadReq_accesses::cpu.inst 5643 # number of ReadReq accesses(hits+misses) 252system.cpu.icache.ReadReq_accesses::total 5643 # number of ReadReq accesses(hits+misses) 253system.cpu.icache.demand_accesses::cpu.inst 5643 # number of demand (read+write) accesses 254system.cpu.icache.demand_accesses::total 5643 # number of demand (read+write) accesses 255system.cpu.icache.overall_accesses::cpu.inst 5643 # number of overall (read+write) accesses 256system.cpu.icache.overall_accesses::total 5643 # number of overall (read+write) accesses 257system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052277 # miss rate for ReadReq accesses 258system.cpu.icache.ReadReq_miss_rate::total 0.052277 # miss rate for ReadReq accesses 259system.cpu.icache.demand_miss_rate::cpu.inst 0.052277 # miss rate for demand accesses 260system.cpu.icache.demand_miss_rate::total 0.052277 # miss rate for demand accesses 261system.cpu.icache.overall_miss_rate::cpu.inst 0.052277 # miss rate for overall accesses 262system.cpu.icache.overall_miss_rate::total 0.052277 # miss rate for overall accesses |
| 263system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency 264system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency 265system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency 266system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency 267system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency 268system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency | 263system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency 264system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency 265system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency 266system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency 267system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency 268system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency |
| 269system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 273system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 274system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 275system.cpu.icache.writebacks::writebacks 13 # number of writebacks 276system.cpu.icache.writebacks::total 13 # number of writebacks 277system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 278system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 279system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 280system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 281system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 282system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses | 269system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 270system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 271system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 272system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 273system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 274system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 275system.cpu.icache.writebacks::writebacks 13 # number of writebacks 276system.cpu.icache.writebacks::total 13 # number of writebacks 277system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 278system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 279system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 280system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 281system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 282system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses |
| 283system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles 284system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles 285system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles 286system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles 287system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles 288system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles | 283system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles 284system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles 285system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles 286system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles 287system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles 288system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles |
| 289system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses 290system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses 291system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses 292system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses 293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 294system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses | 289system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for ReadReq accesses 290system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052277 # mshr miss rate for ReadReq accesses 291system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for demand accesses 292system.cpu.icache.demand_mshr_miss_rate::total 0.052277 # mshr miss rate for demand accesses 293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 294system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses |
| 295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency 297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency 297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency 299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency 301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 302system.cpu.l2cache.tags.replacements 0 # number of replacements | 302system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 303system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use | 303system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use |
| 304system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. | 304system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. |
| 305system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. | 305system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks. |
| 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 308system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor | 308system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor |
| 310system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy | 310system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy |
| 311system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy 312system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 316system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id | 311system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy 312system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id 316system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id |
| 317system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 318system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses | 317system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 318system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses |
| 319system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 319system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 320system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 321system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 322system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 323system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 326system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 327system.cpu.l2cache.overall_hits::total 2 # number of overall hits --- 4 unchanged lines hidden (view full) --- 332system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 333system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses 334system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 337system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 338system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 339system.cpu.l2cache.overall_misses::total 430 # number of overall misses | 320system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 321system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 322system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 323system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 326system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 327system.cpu.l2cache.overall_hits::total 2 # number of overall hits --- 4 unchanged lines hidden (view full) --- 332system.cpu.l2cache.ReadSharedReq_misses::cpu.data 87 # number of ReadSharedReq misses 333system.cpu.l2cache.ReadSharedReq_misses::total 87 # number of ReadSharedReq misses 334system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 335system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 336system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 337system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 338system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 339system.cpu.l2cache.overall_misses::total 430 # number of overall misses |
| 340system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles 342system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles 343system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles 344system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles 345system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles | 340system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles 341system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles 342system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles 343system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles 344system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles 345system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles 346system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles 347system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles 348system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles 349system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles 350system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles 351system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles |
| 352system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) 353system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 356system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) 357system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) 358system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 359system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 370system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 371system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 372system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 374system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 375system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 377system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses | 352system.cpu.l2cache.WritebackClean_accesses::writebacks 13 # number of WritebackClean accesses(hits+misses) 353system.cpu.l2cache.WritebackClean_accesses::total 13 # number of WritebackClean accesses(hits+misses) 354system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 355system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 356system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 295 # number of ReadCleanReq accesses(hits+misses) 357system.cpu.l2cache.ReadCleanReq_accesses::total 295 # number of ReadCleanReq accesses(hits+misses) 358system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 87 # number of ReadSharedReq accesses(hits+misses) 359system.cpu.l2cache.ReadSharedReq_accesses::total 87 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 370system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 371system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 372system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 373system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 374system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 375system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 376system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 377system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses |
| 378system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency 380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency 381system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency 382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency 383system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency 386system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency 389system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency | 378system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency 379system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency 380system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency 381system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency 382system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency 383system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency 384system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency 385system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency 386system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency 387system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency 388system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency 389system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency |
| 390system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 393system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 395system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 396system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 397system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 398system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses 399system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses 400system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 401system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses | 390system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 391system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 392system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 393system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 394system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 395system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 396system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 397system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 398system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses 399system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses 400system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses 401system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses 402system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 403system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 404system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 405system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 406system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 407system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses |
| 408system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles 409system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles 410system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles 411system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles 412system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles 413system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles 419system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles | 408system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles 409system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles 410system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles 411system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles 412system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles 413system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles 414system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles 415system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles 416system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles 417system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles 418system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles 419system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles |
| 420system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 421system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 422system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses 423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses 424system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 426system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 427system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 428system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 429system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 430system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 431system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses | 420system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 421system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 422system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadCleanReq accesses 423system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.993220 # mshr miss rate for ReadCleanReq accesses 424system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 425system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 426system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 427system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 428system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 429system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 430system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 431system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses |
| 432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency 435system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency 436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency 437system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 440system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 443system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency | 432system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency 433system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency 434system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency 435system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency 436system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency 437system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency 438system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency 439system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 440system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency 441system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency 442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency 443system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency |
| 444system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 445system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 446system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 447system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 448system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 449system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 444system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 445system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 446system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 447system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 448system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 449system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 450system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 450system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 451system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 474system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 476system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 477system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 480system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 481system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) | 451system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) --- 15 unchanged lines hidden (view full) --- 474system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 475system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 476system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 477system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 480system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 481system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) |
| 482system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states | 482system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter. 483system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 484system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 485system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 486system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 487system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 488system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states |
| 483system.membus.trans_dist::ReadResp 380 # Transaction distribution 484system.membus.trans_dist::ReadExReq 50 # Transaction distribution 485system.membus.trans_dist::ReadExResp 50 # Transaction distribution 486system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 487system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 488system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 489system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 490system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- | 489system.membus.trans_dist::ReadResp 380 # Transaction distribution 490system.membus.trans_dist::ReadExReq 50 # Transaction distribution 491system.membus.trans_dist::ReadExResp 50 # Transaction distribution 492system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 493system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 494system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 495system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 496system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 18 unchanged lines hidden --- |