| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000034 # Number of seconds simulated 4sim_ticks 33932500 # Number of ticks simulated 5final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000034 # Number of seconds simulated 4sim_ticks 33932500 # Number of ticks simulated 5final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 431758 # Simulator instruction rate (inst/s) 8host_op_rate 430982 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2588300068 # Simulator tick rate (ticks/s) 10host_mem_usage 244424 # Number of bytes of host memory used | 7host_inst_rate 497160 # Simulator instruction rate (inst/s) 8host_op_rate 496749 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2985875640 # Simulator tick rate (ticks/s) 10host_mem_usage 289632 # Number of bytes of host memory used |
| 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 430 # Number of read requests responded to by this memory 24system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) | 17system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 19system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 430 # Number of read requests responded to by this memory 25system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s) |
| 33system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.read_hits 0 # DTB read hits 34system.cpu.dtb.read_misses 0 # DTB read misses 35system.cpu.dtb.read_accesses 0 # DTB read accesses 36system.cpu.dtb.write_hits 0 # DTB write hits 37system.cpu.dtb.write_misses 0 # DTB write misses 38system.cpu.dtb.write_accesses 0 # DTB write accesses 39system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 44system.cpu.itb.read_accesses 0 # DTB read accesses 45system.cpu.itb.write_hits 0 # DTB write hits 46system.cpu.itb.write_misses 0 # DTB write misses 47system.cpu.itb.write_accesses 0 # DTB write accesses 48system.cpu.itb.hits 0 # DTB hits 49system.cpu.itb.misses 0 # DTB misses 50system.cpu.itb.accesses 0 # DTB accesses 51system.cpu.workload.num_syscalls 7 # Number of system calls | 34system.cpu_clk_domain.clock 500 # Clock period in ticks 35system.cpu.dtb.read_hits 0 # DTB read hits 36system.cpu.dtb.read_misses 0 # DTB read misses 37system.cpu.dtb.read_accesses 0 # DTB read accesses 38system.cpu.dtb.write_hits 0 # DTB write hits 39system.cpu.dtb.write_misses 0 # DTB write misses 40system.cpu.dtb.write_accesses 0 # DTB write accesses 41system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 46system.cpu.itb.read_accesses 0 # DTB read accesses 47system.cpu.itb.write_hits 0 # DTB write hits 48system.cpu.itb.write_misses 0 # DTB write misses 49system.cpu.itb.write_accesses 0 # DTB write accesses 50system.cpu.itb.hits 0 # DTB hits 51system.cpu.itb.misses 0 # DTB misses 52system.cpu.itb.accesses 0 # DTB accesses 53system.cpu.workload.num_syscalls 7 # Number of system calls |
| 54system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states |
|
| 52system.cpu.numCycles 67865 # number of cpu cycles simulated 53system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 54system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 55system.cpu.committedInsts 5641 # Number of instructions committed 56system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 57system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 58system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 59system.cpu.num_func_calls 191 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 102system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 105system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 106system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 107system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::total 5642 # Class of executed instruction | 55system.cpu.numCycles 67865 # number of cpu cycles simulated 56system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 57system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 58system.cpu.committedInsts 5641 # Number of instructions committed 59system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 60system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 61system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 62system.cpu.num_func_calls 191 # number of times a function call or return occured --- 42 unchanged lines hidden (view full) --- 105system.cpu.op_class::SimdFloatMult 0 0.00% 63.90% # Class of executed instruction 106system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 107system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 108system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 109system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 110system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 111system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 112system.cpu.op_class::total 5642 # Class of executed instruction |
| 113system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 110system.cpu.dcache.tags.replacements 0 # number of replacements 111system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use 112system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 113system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 114system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 115system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor 117system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy 118system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy 119system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 120system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 121system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 122system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 123system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 124system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses | 114system.cpu.dcache.tags.replacements 0 # number of replacements 115system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use 116system.cpu.dcache.tags.total_refs 1899 # Total number of references to valid blocks. 117system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 118system.cpu.dcache.tags.avg_refs 13.861314 # Average number of references to valid blocks. 119system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 120system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor 121system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy 122system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy 123system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 124system.cpu.dcache.tags.age_task_id_blocks_1024::0 22 # Occupied blocks per task id 125system.cpu.dcache.tags.age_task_id_blocks_1024::1 115 # Occupied blocks per task id 126system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 127system.cpu.dcache.tags.tag_accesses 4209 # Number of tag accesses 128system.cpu.dcache.tags.data_accesses 4209 # Number of data accesses |
| 129system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 125system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 126system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 127system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 128system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 129system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 130system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 131system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 132system.cpu.dcache.overall_hits::total 1899 # number of overall hits --- 70 unchanged lines hidden (view full) --- 203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 204system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 206system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 207system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 208system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 209system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 210system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency | 130system.cpu.dcache.ReadReq_hits::cpu.data 1048 # number of ReadReq hits 131system.cpu.dcache.ReadReq_hits::total 1048 # number of ReadReq hits 132system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 133system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 134system.cpu.dcache.demand_hits::cpu.data 1899 # number of demand (read+write) hits 135system.cpu.dcache.demand_hits::total 1899 # number of demand (read+write) hits 136system.cpu.dcache.overall_hits::cpu.data 1899 # number of overall hits 137system.cpu.dcache.overall_hits::total 1899 # number of overall hits --- 70 unchanged lines hidden (view full) --- 208system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency 209system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency 210system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency 211system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency 212system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 213system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency 214system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency 215system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency |
| 216system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 211system.cpu.icache.tags.replacements 13 # number of replacements 212system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use 213system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 214system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 215system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 217system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor 218system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy 219system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy 220system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 221system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 222system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 223system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 224system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 225system.cpu.icache.tags.data_accesses 11581 # Number of data accesses | 217system.cpu.icache.tags.replacements 13 # number of replacements 218system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use 219system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks. 220system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 221system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks. 222system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 223system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor 224system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy 225system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy 226system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 227system.cpu.icache.tags.age_task_id_blocks_1024::0 105 # Occupied blocks per task id 228system.cpu.icache.tags.age_task_id_blocks_1024::1 177 # Occupied blocks per task id 229system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 230system.cpu.icache.tags.tag_accesses 11581 # Number of tag accesses 231system.cpu.icache.tags.data_accesses 11581 # Number of data accesses |
| 232system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 226system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 227system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 228system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 229system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 230system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 231system.cpu.icache.overall_hits::total 5348 # number of overall hits 232system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 233system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 287system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses 288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency 289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency 290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 291system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 293system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency | 233system.cpu.icache.ReadReq_hits::cpu.inst 5348 # number of ReadReq hits 234system.cpu.icache.ReadReq_hits::total 5348 # number of ReadReq hits 235system.cpu.icache.demand_hits::cpu.inst 5348 # number of demand (read+write) hits 236system.cpu.icache.demand_hits::total 5348 # number of demand (read+write) hits 237system.cpu.icache.overall_hits::cpu.inst 5348 # number of overall hits 238system.cpu.icache.overall_hits::total 5348 # number of overall hits 239system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 240system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses --- 52 unchanged lines hidden (view full) --- 293system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses 294system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses 295system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency 296system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency 297system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 298system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency 299system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency 300system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency |
| 301system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 294system.cpu.l2cache.tags.replacements 0 # number of replacements 295system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use 296system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 297system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 298system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. 299system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 300system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor 301system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor 302system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy 303system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy 304system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy 305system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 306system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 307system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 308system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 309system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 310system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses | 302system.cpu.l2cache.tags.replacements 0 # number of replacements 303system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use 304system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks. 305system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 306system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks. 307system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 308system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor 309system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor 310system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003970 # Average percentage of cache occupancy 311system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy 312system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy 313system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 314system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id 315system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id 316system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 317system.cpu.l2cache.tags.tag_accesses 3990 # Number of tag accesses 318system.cpu.l2cache.tags.data_accesses 3990 # Number of data accesses |
| 319system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
|
| 311system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 312system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 313system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 314system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 315system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 316system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 317system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 318system.cpu.l2cache.overall_hits::total 2 # number of overall hits --- 114 unchanged lines hidden (view full) --- 433system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 434system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency 435system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 436system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 437system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 438system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 439system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 440system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 320system.cpu.l2cache.WritebackClean_hits::writebacks 13 # number of WritebackClean hits 321system.cpu.l2cache.WritebackClean_hits::total 13 # number of WritebackClean hits 322system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 2 # number of ReadCleanReq hits 323system.cpu.l2cache.ReadCleanReq_hits::total 2 # number of ReadCleanReq hits 324system.cpu.l2cache.demand_hits::cpu.inst 2 # number of demand (read+write) hits 325system.cpu.l2cache.demand_hits::total 2 # number of demand (read+write) hits 326system.cpu.l2cache.overall_hits::cpu.inst 2 # number of overall hits 327system.cpu.l2cache.overall_hits::total 2 # number of overall hits --- 114 unchanged lines hidden (view full) --- 442system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency 443system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency 444system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 445system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 446system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 447system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 448system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 449system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 450system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
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| 441system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 444system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 447system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 463system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 465system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 466system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 467system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 468system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 469system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 470system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) | 451system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 452system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 456system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 457system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 473system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 474system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 475system.cpu.toL2Bus.reqLayer0.occupancy 235500 # Layer occupancy (ticks) 476system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 477system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 478system.cpu.toL2Bus.respLayer0.utilization 1.3 # Layer utilization (%) 479system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 480system.cpu.toL2Bus.respLayer1.utilization 0.6 # Layer utilization (%) |
| 481system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states |
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| 471system.membus.trans_dist::ReadResp 380 # Transaction distribution 472system.membus.trans_dist::ReadExReq 50 # Transaction distribution 473system.membus.trans_dist::ReadExResp 50 # Transaction distribution 474system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 475system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 476system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 477system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 478system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 482system.membus.trans_dist::ReadResp 380 # Transaction distribution 483system.membus.trans_dist::ReadExReq 50 # Transaction distribution 484system.membus.trans_dist::ReadExResp 50 # Transaction distribution 485system.membus.trans_dist::ReadSharedReq 380 # Transaction distribution 486system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 487system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 488system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 489system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |