| stats.txt (10892:bd37e25fb3b7) | stats.txt (11138:a611a23c8cc2) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30902500 # Number of ticks simulated 5final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated 4sim_ticks 30902500 # Number of ticks simulated 5final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 339265 # Simulator instruction rate (inst/s) 8host_op_rate 338999 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1861147916 # Simulator tick rate (ticks/s) 10host_mem_usage 289452 # Number of bytes of host memory used 11host_seconds 0.02 # Real time elapsed on the host | 7host_inst_rate 459853 # Simulator instruction rate (inst/s) 8host_op_rate 459290 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2521006690 # Simulator tick rate (ticks/s) 10host_mem_usage 291832 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory --- 410 unchanged lines hidden (view full) --- 430system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 431system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 432system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 433system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 434system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 436system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 437system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory --- 410 unchanged lines hidden (view full) --- 430system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 42500 # average ReadSharedReq mshr miss latency 431system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 432system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 433system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 434system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 42501.706485 # average overall mshr miss latency 435system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 42500 # average overall mshr miss latency 436system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42501.162791 # average overall mshr miss latency 437system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 438system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter. 439system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data. 440system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 441system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 442system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 443system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
|
| 438system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 439system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution 440system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 441system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 442system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 443system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 444system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 445system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 446system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) 447system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) 448system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 449system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) 450system.cpu.toL2Bus.snoops 0 # Total snoops (count) 451system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram | 444system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 445system.cpu.toL2Bus.trans_dist::CleanEvict 13 # Transaction distribution 446system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 447system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 448system.cpu.toL2Bus.trans_dist::ReadCleanReq 295 # Transaction distribution 449system.cpu.toL2Bus.trans_dist::ReadSharedReq 87 # Transaction distribution 450system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 603 # Packet count per connected master and slave (bytes) 451system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 452system.cpu.toL2Bus.pkt_count::total 877 # Packet count per connected master and slave (bytes) 453system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) 454system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8768 # Cumulative packet size per connected master and slave (bytes) 455system.cpu.toL2Bus.pkt_size::total 27648 # Cumulative packet size per connected master and slave (bytes) 456system.cpu.toL2Bus.snoops 0 # Total snoops (count) 457system.cpu.toL2Bus.snoop_fanout::samples 445 # Request fanout histogram |
| 452system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram | 458system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram |
| 453system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 454system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram | 459system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram |
| 455system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 456system.cpu.toL2Bus.snoop_fanout::1 445 100.00% 100.00% # Request fanout histogram | 461system.cpu.toL2Bus.snoop_fanout::0 445 100.00% 100.00% # Request fanout histogram 462system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram |
| 457system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 458system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram | 463system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram |
| 459system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 460system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram | 465system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram |
| 461system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram 462system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) 463system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 464system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 465system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 466system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 467system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 468system.membus.trans_dist::ReadResp 380 # Transaction distribution --- 24 unchanged lines hidden --- | 467system.cpu.toL2Bus.snoop_fanout::total 445 # Request fanout histogram 468system.cpu.toL2Bus.reqLayer0.occupancy 222500 # Layer occupancy (ticks) 469system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 470system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 471system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 472system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 473system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 474system.membus.trans_dist::ReadResp 380 # Transaction distribution --- 24 unchanged lines hidden --- |