| stats.txt (10488:7c27480a5031) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000031 # Number of seconds simulated |
| 4sim_ticks 30902000 # Number of ticks simulated 5final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 30902500 # Number of ticks simulated 5final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 104539 # Simulator instruction rate (inst/s) 8host_op_rate 104503 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 574021463 # Simulator tick rate (ticks/s) 10host_mem_usage 276192 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 544856 # Simulator instruction rate (inst/s) 8host_op_rate 544118 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2985748792 # Simulator tick rate (ticks/s) 10host_mem_usage 288768 # Number of bytes of host memory used 11host_seconds 0.01 # Real time elapsed on the host |
| 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 430 # Number of read requests responded to by this memory | 12sim_insts 5624 # Number of instructions simulated 13sim_ops 5624 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory 18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 18752 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 293 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 137 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 430 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s) 32system.membus.trans_dist::ReadReq 380 # Transaction distribution 33system.membus.trans_dist::ReadResp 380 # Transaction distribution 34system.membus.trans_dist::ReadExReq 50 # Transaction distribution 35system.membus.trans_dist::ReadExResp 50 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 430 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 430 # Request fanout histogram 51system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 53system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 12.5 # Layer utilization (%) | 24system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s) |
| 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dtb.read_hits 0 # DTB read hits 57system.cpu.dtb.read_misses 0 # DTB read misses 58system.cpu.dtb.read_accesses 0 # DTB read accesses 59system.cpu.dtb.write_hits 0 # DTB write hits 60system.cpu.dtb.write_misses 0 # DTB write misses 61system.cpu.dtb.write_accesses 0 # DTB write accesses 62system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 67system.cpu.itb.read_accesses 0 # DTB read accesses 68system.cpu.itb.write_hits 0 # DTB write hits 69system.cpu.itb.write_misses 0 # DTB write misses 70system.cpu.itb.write_accesses 0 # DTB write accesses 71system.cpu.itb.hits 0 # DTB hits 72system.cpu.itb.misses 0 # DTB misses 73system.cpu.itb.accesses 0 # DTB accesses 74system.cpu.workload.num_syscalls 7 # Number of system calls | 32system.cpu_clk_domain.clock 500 # Clock period in ticks 33system.cpu.dtb.read_hits 0 # DTB read hits 34system.cpu.dtb.read_misses 0 # DTB read misses 35system.cpu.dtb.read_accesses 0 # DTB read accesses 36system.cpu.dtb.write_hits 0 # DTB write hits 37system.cpu.dtb.write_misses 0 # DTB write misses 38system.cpu.dtb.write_accesses 0 # DTB write accesses 39system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 44system.cpu.itb.read_accesses 0 # DTB read accesses 45system.cpu.itb.write_hits 0 # DTB write hits 46system.cpu.itb.write_misses 0 # DTB write misses 47system.cpu.itb.write_accesses 0 # DTB write accesses 48system.cpu.itb.hits 0 # DTB hits 49system.cpu.itb.misses 0 # DTB misses 50system.cpu.itb.accesses 0 # DTB accesses 51system.cpu.workload.num_syscalls 7 # Number of system calls |
| 75system.cpu.numCycles 61804 # number of cpu cycles simulated | 52system.cpu.numCycles 61805 # number of cpu cycles simulated |
| 76system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 77system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 78system.cpu.committedInsts 5624 # Number of instructions committed 79system.cpu.committedOps 5624 # Number of ops (including micro ops) committed 80system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses 81system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 82system.cpu.num_func_calls 190 # number of times a function call or return occured 83system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls 84system.cpu.num_int_insts 4944 # number of integer instructions 85system.cpu.num_fp_insts 2 # number of float instructions 86system.cpu.num_int_register_reads 7054 # number of times the integer registers were read 87system.cpu.num_int_register_writes 3281 # number of times the integer registers were written 88system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 89system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 90system.cpu.num_mem_refs 2034 # number of memory refs 91system.cpu.num_load_insts 1132 # Number of load instructions 92system.cpu.num_store_insts 902 # Number of store instructions 93system.cpu.num_idle_cycles 0 # Number of idle cycles | 53system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 54system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 55system.cpu.committedInsts 5624 # Number of instructions committed 56system.cpu.committedOps 5624 # Number of ops (including micro ops) committed 57system.cpu.num_int_alu_accesses 4944 # Number of integer alu accesses 58system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 59system.cpu.num_func_calls 190 # number of times a function call or return occured 60system.cpu.num_conditional_control_insts 649 # number of instructions that are conditional controls 61system.cpu.num_int_insts 4944 # number of integer instructions 62system.cpu.num_fp_insts 2 # number of float instructions 63system.cpu.num_int_register_reads 7054 # number of times the integer registers were read 64system.cpu.num_int_register_writes 3281 # number of times the integer registers were written 65system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 66system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 67system.cpu.num_mem_refs 2034 # number of memory refs 68system.cpu.num_load_insts 1132 # Number of load instructions 69system.cpu.num_store_insts 902 # Number of store instructions 70system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 94system.cpu.num_busy_cycles 61804 # Number of busy cycles | 71system.cpu.num_busy_cycles 61805 # Number of busy cycles |
| 95system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 96system.cpu.idle_fraction 0 # Percentage of idle cycles 97system.cpu.Branches 883 # Number of branches fetched 98system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction 99system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction 100system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction 101system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction 102system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 125system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction 126system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction 127system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction 128system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction 129system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction 130system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 131system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 132system.cpu.op_class::total 5625 # Class of executed instruction | 72system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 73system.cpu.idle_fraction 0 # Percentage of idle cycles 74system.cpu.Branches 883 # Number of branches fetched 75system.cpu.op_class::No_OpClass 637 11.32% 11.32% # Class of executed instruction 76system.cpu.op_class::IntAlu 2950 52.44% 63.77% # Class of executed instruction 77system.cpu.op_class::IntMult 2 0.04% 63.80% # Class of executed instruction 78system.cpu.op_class::IntDiv 0 0.00% 63.80% # Class of executed instruction 79system.cpu.op_class::FloatAdd 2 0.04% 63.84% # Class of executed instruction --- 22 unchanged lines hidden (view full) --- 102system.cpu.op_class::SimdFloatMult 0 0.00% 63.84% # Class of executed instruction 103system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.84% # Class of executed instruction 104system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.84% # Class of executed instruction 105system.cpu.op_class::MemRead 1132 20.12% 83.96% # Class of executed instruction 106system.cpu.op_class::MemWrite 902 16.04% 100.00% # Class of executed instruction 107system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 108system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 109system.cpu.op_class::total 5625 # Class of executed instruction |
| 110system.cpu.dcache.tags.replacements 0 # number of replacements 111system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use 112system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. 113system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 114system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. 115system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 116system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor 117system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy 118system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy 119system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 120system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 121system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id 122system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 123system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses 124system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses 125system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits 126system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits 127system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 128system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 129system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits 130system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits 131system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits 132system.cpu.dcache.overall_hits::total 1896 # number of overall hits 133system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 134system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 135system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 136system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 137system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 138system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 139system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 140system.cpu.dcache.overall_misses::total 137 # number of overall misses 141system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 142system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 143system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles 144system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles 145system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles 146system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles 147system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles 148system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles 149system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) 150system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) 151system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 152system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 153system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses 154system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses 155system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses 156system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses 157system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses 158system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses 159system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 160system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 161system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses 162system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses 163system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses 164system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses 165system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 166system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 167system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 168system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 169system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 170system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 171system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 172system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 173system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 174system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 175system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 176system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 177system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 178system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 179system.cpu.dcache.fast_writes 0 # number of fast writes performed 180system.cpu.dcache.cache_copies 0 # number of cache copies performed 181system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 182system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 183system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 184system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 185system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 186system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 187system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 188system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 189system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles 190system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles 191system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles 192system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles 193system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles 194system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles 195system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles 196system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles 197system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses 198system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses 199system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 200system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 201system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses 202system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses 203system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses 204system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses 205system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency 206system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency 207system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency 208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency 209system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency 210system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency 211system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency 212system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency 213system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
|
| 133system.cpu.icache.tags.replacements 13 # number of replacements | 214system.cpu.icache.tags.replacements 13 # number of replacements |
| 134system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use | 215system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use |
| 135system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. 136system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 137system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. 138system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 216system.cpu.icache.tags.total_refs 5331 # Total number of references to valid blocks. 217system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks. 218system.cpu.icache.tags.avg_refs 18.071186 # Average number of references to valid blocks. 219system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 139system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor 140system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy 141system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy | 220system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor 221system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy 222system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy |
| 142system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 143system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 144system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 145system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 146system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses 147system.cpu.icache.tags.data_accesses 11547 # Number of data accesses 148system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits 149system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits 150system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits 151system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits 152system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits 153system.cpu.icache.overall_hits::total 5331 # number of overall hits 154system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 155system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 156system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 157system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 158system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 159system.cpu.icache.overall_misses::total 295 # number of overall misses | 223system.cpu.icache.tags.occ_task_id_blocks::1024 282 # Occupied blocks per task id 224system.cpu.icache.tags.age_task_id_blocks_1024::0 112 # Occupied blocks per task id 225system.cpu.icache.tags.age_task_id_blocks_1024::1 170 # Occupied blocks per task id 226system.cpu.icache.tags.occ_task_id_percent::1024 0.137695 # Percentage of cache occupancy per task id 227system.cpu.icache.tags.tag_accesses 11547 # Number of tag accesses 228system.cpu.icache.tags.data_accesses 11547 # Number of data accesses 229system.cpu.icache.ReadReq_hits::cpu.inst 5331 # number of ReadReq hits 230system.cpu.icache.ReadReq_hits::total 5331 # number of ReadReq hits 231system.cpu.icache.demand_hits::cpu.inst 5331 # number of demand (read+write) hits 232system.cpu.icache.demand_hits::total 5331 # number of demand (read+write) hits 233system.cpu.icache.overall_hits::cpu.inst 5331 # number of overall hits 234system.cpu.icache.overall_hits::total 5331 # number of overall hits 235system.cpu.icache.ReadReq_misses::cpu.inst 295 # number of ReadReq misses 236system.cpu.icache.ReadReq_misses::total 295 # number of ReadReq misses 237system.cpu.icache.demand_misses::cpu.inst 295 # number of demand (read+write) misses 238system.cpu.icache.demand_misses::total 295 # number of demand (read+write) misses 239system.cpu.icache.overall_misses::cpu.inst 295 # number of overall misses 240system.cpu.icache.overall_misses::total 295 # number of overall misses |
| 160system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles 161system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles 162system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles 163system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles 164system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles 165system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles | 241system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles 242system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles 243system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles 244system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles 245system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles 246system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles |
| 166system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) 167system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) 168system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses 169system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses 170system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses 171system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses 172system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses 173system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses 174system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses 175system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses 176system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses 177system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses | 247system.cpu.icache.ReadReq_accesses::cpu.inst 5626 # number of ReadReq accesses(hits+misses) 248system.cpu.icache.ReadReq_accesses::total 5626 # number of ReadReq accesses(hits+misses) 249system.cpu.icache.demand_accesses::cpu.inst 5626 # number of demand (read+write) accesses 250system.cpu.icache.demand_accesses::total 5626 # number of demand (read+write) accesses 251system.cpu.icache.overall_accesses::cpu.inst 5626 # number of overall (read+write) accesses 252system.cpu.icache.overall_accesses::total 5626 # number of overall (read+write) accesses 253system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052435 # miss rate for ReadReq accesses 254system.cpu.icache.ReadReq_miss_rate::total 0.052435 # miss rate for ReadReq accesses 255system.cpu.icache.demand_miss_rate::cpu.inst 0.052435 # miss rate for demand accesses 256system.cpu.icache.demand_miss_rate::total 0.052435 # miss rate for demand accesses 257system.cpu.icache.overall_miss_rate::cpu.inst 0.052435 # miss rate for overall accesses 258system.cpu.icache.overall_miss_rate::total 0.052435 # miss rate for overall accesses |
| 178system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency 179system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency 180system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency 181system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency 182system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency 183system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency | 259system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency 260system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency 261system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency 262system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency 263system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency 264system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency |
| 184system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 185system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 186system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 187system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 188system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 189system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 190system.cpu.icache.fast_writes 0 # number of fast writes performed 191system.cpu.icache.cache_copies 0 # number of cache copies performed 192system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 193system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 194system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 195system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 196system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 197system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses | 265system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 266system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 267system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 268system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 269system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 270system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 271system.cpu.icache.fast_writes 0 # number of fast writes performed 272system.cpu.icache.cache_copies 0 # number of cache copies performed 273system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses 274system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses 275system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses 276system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses 277system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses 278system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses |
| 198system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles 199system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles 200system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles 201system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles 202system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles 203system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles | 279system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles 280system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles 281system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles 282system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles 283system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles 284system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles |
| 204system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses 205system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses 206system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses 207system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses 208system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses 209system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses | 285system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for ReadReq accesses 286system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052435 # mshr miss rate for ReadReq accesses 287system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for demand accesses 288system.cpu.icache.demand_mshr_miss_rate::total 0.052435 # mshr miss rate for demand accesses 289system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052435 # mshr miss rate for overall accesses 290system.cpu.icache.overall_mshr_miss_rate::total 0.052435 # mshr miss rate for overall accesses |
| 210system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency 211system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency 212system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency 213system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency 214system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency 215system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency | 291system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency 292system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency 293system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency 294system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency 295system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency 296system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency |
| 216system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 217system.cpu.l2cache.tags.replacements 0 # number of replacements | 297system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 298system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 218system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use | 299system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use |
| 219system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 220system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 221system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. 222system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 300system.cpu.l2cache.tags.total_refs 2 # Total number of references to valid blocks. 301system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks. 302system.cpu.l2cache.tags.avg_refs 0.005263 # Average number of references to valid blocks. 303system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 223system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor 224system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor | 304system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor 305system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor |
| 225system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy 226system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy 227system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy 228system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 229system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 230system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 231system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 232system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 243system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 244system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 245system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 246system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 247system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 248system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 249system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 250system.cpu.l2cache.overall_misses::total 430 # number of overall misses | 306system.cpu.l2cache.tags.occ_percent::cpu.inst 0.003975 # Average percentage of cache occupancy 307system.cpu.l2cache.tags.occ_percent::cpu.data 0.001631 # Average percentage of cache occupancy 308system.cpu.l2cache.tags.occ_percent::total 0.005607 # Average percentage of cache occupancy 309system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id 310system.cpu.l2cache.tags.age_task_id_blocks_1024::0 138 # Occupied blocks per task id 311system.cpu.l2cache.tags.age_task_id_blocks_1024::1 242 # Occupied blocks per task id 312system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id 313system.cpu.l2cache.tags.tag_accesses 3886 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 324system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 325system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 326system.cpu.l2cache.demand_misses::cpu.inst 293 # number of demand (read+write) misses 327system.cpu.l2cache.demand_misses::cpu.data 137 # number of demand (read+write) misses 328system.cpu.l2cache.demand_misses::total 430 # number of demand (read+write) misses 329system.cpu.l2cache.overall_misses::cpu.inst 293 # number of overall misses 330system.cpu.l2cache.overall_misses::cpu.data 137 # number of overall misses 331system.cpu.l2cache.overall_misses::total 430 # number of overall misses |
| 251system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles 252system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles 253system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles 254system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles 255system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles 256system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles 257system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles 258system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles 259system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles 260system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles 261system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles | 332system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles 333system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles 334system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles 335system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles 336system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles 337system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles 338system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles 339system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles 340system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles 341system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles 342system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles |
| 262system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) 263system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 264system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) 265system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 266system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 267system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses 268system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 269system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 276system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 277system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 278system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 279system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 280system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 281system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 282system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 283system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses | 343system.cpu.l2cache.ReadReq_accesses::cpu.inst 295 # number of ReadReq accesses(hits+misses) 344system.cpu.l2cache.ReadReq_accesses::cpu.data 87 # number of ReadReq accesses(hits+misses) 345system.cpu.l2cache.ReadReq_accesses::total 382 # number of ReadReq accesses(hits+misses) 346system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 347system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 348system.cpu.l2cache.demand_accesses::cpu.inst 295 # number of demand (read+write) accesses 349system.cpu.l2cache.demand_accesses::cpu.data 137 # number of demand (read+write) accesses 350system.cpu.l2cache.demand_accesses::total 432 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 357system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 358system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 359system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993220 # miss rate for demand accesses 360system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 361system.cpu.l2cache.demand_miss_rate::total 0.995370 # miss rate for demand accesses 362system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993220 # miss rate for overall accesses 363system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 364system.cpu.l2cache.overall_miss_rate::total 0.995370 # miss rate for overall accesses |
| 284system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency 285system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency 286system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency 287system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency 288system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency 289system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency 290system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency 291system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency 292system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency 293system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency 294system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency | 365system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency 366system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency 367system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency 368system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency 369system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency 370system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency 371system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency 372system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency 373system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency 374system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency 375system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency |
| 295system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 296system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 297system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 298system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 299system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 300system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 301system.cpu.l2cache.fast_writes 0 # number of fast writes performed 302system.cpu.l2cache.cache_copies 0 # number of cache copies performed 303system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 304system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 305system.cpu.l2cache.ReadReq_mshr_misses::total 380 # number of ReadReq MSHR misses 306system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 307system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 308system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 309system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 310system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 311system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 312system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 313system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses | 376system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 377system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 378system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 379system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 380system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 381system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 382system.cpu.l2cache.fast_writes 0 # number of fast writes performed 383system.cpu.l2cache.cache_copies 0 # number of cache copies performed 384system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 293 # number of ReadReq MSHR misses 385system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 386system.cpu.l2cache.ReadReq_mshr_misses::total 380 # number of ReadReq MSHR misses 387system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 388system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 389system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses 390system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 391system.cpu.l2cache.demand_mshr_misses::total 430 # number of demand (read+write) MSHR misses 392system.cpu.l2cache.overall_mshr_misses::cpu.inst 293 # number of overall MSHR misses 393system.cpu.l2cache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 394system.cpu.l2cache.overall_mshr_misses::total 430 # number of overall MSHR misses |
| 314system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles 315system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles 316system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles 317system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles 318system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles 319system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles 320system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles 321system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles 322system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles 323system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles 324system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles | 395system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles 396system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles 397system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles 398system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles 399system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles 400system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles 401system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles 402system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles 403system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles 404system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles 405system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles |
| 325system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses 326system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 327system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses 328system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 329system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 330system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 331system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 332system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 333system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 334system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 335system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses | 406system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for ReadReq accesses 407system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 408system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994764 # mshr miss rate for ReadReq accesses 409system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 410system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 411system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for demand accesses 412system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 413system.cpu.l2cache.demand_mshr_miss_rate::total 0.995370 # mshr miss rate for demand accesses 414system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993220 # mshr miss rate for overall accesses 415system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 416system.cpu.l2cache.overall_mshr_miss_rate::total 0.995370 # mshr miss rate for overall accesses |
| 336system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency 337system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency 338system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency 339system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency 340system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency 341system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 342system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 343system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency 344system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency 345system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency 346system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency | 417system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency 418system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency 419system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency 420system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency 421system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency 422system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 423system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 424system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency 425system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency 426system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency 427system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency |
| 347system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 428system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 348system.cpu.dcache.tags.replacements 0 # number of replacements 349system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use 350system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks. 351system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks. 352system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks. 353system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 354system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor 355system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy 356system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy 357system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id 358system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id 359system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id 360system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id 361system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses 362system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses 363system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits 364system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits 365system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits 366system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits 367system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits 368system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits 369system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits 370system.cpu.dcache.overall_hits::total 1896 # number of overall hits 371system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses 372system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses 373system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses 374system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses 375system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses 376system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses 377system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses 378system.cpu.dcache.overall_misses::total 137 # number of overall misses 379system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles 380system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles 381system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles 382system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles 383system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles 384system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles 385system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles 386system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles 387system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses) 388system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses) 389system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 390system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 391system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses 392system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses 393system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses 394system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses 395system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses 396system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses 397system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses 398system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses 399system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses 400system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses 401system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses 402system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses 403system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency 404system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency 405system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency 406system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency 407system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency 408system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency 409system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency 410system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency 411system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 412system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 413system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 414system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 415system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 416system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 417system.cpu.dcache.fast_writes 0 # number of fast writes performed 418system.cpu.dcache.cache_copies 0 # number of cache copies performed 419system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses 420system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses 421system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 422system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 423system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses 424system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses 425system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses 426system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses 427system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles 428system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles 429system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles 430system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles 431system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles 432system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles 433system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles 434system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles 435system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses 436system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses 437system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 438system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 439system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses 440system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses 441system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses 442system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses 443system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency 444system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 445system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 446system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 447system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 448system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 449system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 450system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 451system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 452system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 456system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 457system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) 459system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) --- 12 unchanged lines hidden (view full) --- 472system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 474system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks) 475system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) | 429system.cpu.toL2Bus.trans_dist::ReadReq 382 # Transaction distribution 430system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution 431system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 432system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 433system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 590 # Packet count per connected master and slave (bytes) 434system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 274 # Packet count per connected master and slave (bytes) 435system.cpu.toL2Bus.pkt_count::total 864 # Packet count per connected master and slave (bytes) 436system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 18880 # Cumulative packet size per connected master and slave (bytes) --- 12 unchanged lines hidden (view full) --- 449system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 450system.cpu.toL2Bus.snoop_fanout::total 432 # Request fanout histogram 451system.cpu.toL2Bus.reqLayer0.occupancy 216000 # Layer occupancy (ticks) 452system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 453system.cpu.toL2Bus.respLayer0.occupancy 442500 # Layer occupancy (ticks) 454system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 455system.cpu.toL2Bus.respLayer1.occupancy 205500 # Layer occupancy (ticks) 456system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) |
| 457system.membus.trans_dist::ReadReq 380 # Transaction distribution 458system.membus.trans_dist::ReadResp 380 # Transaction distribution 459system.membus.trans_dist::ReadExReq 50 # Transaction distribution 460system.membus.trans_dist::ReadExResp 50 # Transaction distribution 461system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes) 462system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes) 463system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes) 464system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes) 465system.membus.snoops 0 # Total snoops (count) 466system.membus.snoop_fanout::samples 430 # Request fanout histogram 467system.membus.snoop_fanout::mean 0 # Request fanout histogram 468system.membus.snoop_fanout::stdev 0 # Request fanout histogram 469system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 470system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram 471system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 472system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 473system.membus.snoop_fanout::min_value 0 # Request fanout histogram 474system.membus.snoop_fanout::max_value 0 # Request fanout histogram 475system.membus.snoop_fanout::total 430 # Request fanout histogram 476system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks) 477system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 478system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks) 479system.membus.respLayer1.utilization 7.0 # Layer utilization (%) |
|
| 480 481---------- End Simulation Statistics ---------- | 480 481---------- End Simulation Statistics ---------- |