1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000032 # Number of seconds simulated 4sim_ticks 31633000 # Number of ticks simulated 5final_tick 31633000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 442331 # Simulator instruction rate (inst/s) 8host_op_rate 441894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 2401898254 # Simulator tick rate (ticks/s) 10host_mem_usage 285092 # Number of bytes of host memory used |
11host_seconds 0.01 # Real time elapsed on the host 12sim_insts 5814 # Number of instructions simulated 13sim_ops 5814 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory 18system.physmem.bytes_read::total 28096 # Number of bytes read from this memory --- 5 unchanged lines hidden (view full) --- 24system.physmem.bw_read::cpu.inst 608984289 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 279202099 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 888186388 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 608984289 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 608984289 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 608984289 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 279202099 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 888186388 # Total bandwidth to/from this memory (bytes/s) |
32system.membus.trans_dist::ReadReq 388 # Transaction distribution 33system.membus.trans_dist::ReadResp 388 # Transaction distribution 34system.membus.trans_dist::ReadExReq 51 # Transaction distribution 35system.membus.trans_dist::ReadExResp 51 # Transaction distribution 36system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 878 # Packet count per connected master and slave (bytes) 37system.membus.pkt_count::total 878 # Packet count per connected master and slave (bytes) |
38system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 28096 # Cumulative packet size per connected master and slave (bytes) 39system.membus.pkt_size::total 28096 # Cumulative packet size per connected master and slave (bytes) 40system.membus.snoops 0 # Total snoops (count) 41system.membus.snoop_fanout::samples 439 # Request fanout histogram 42system.membus.snoop_fanout::mean 0 # Request fanout histogram 43system.membus.snoop_fanout::stdev 0 # Request fanout histogram 44system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 45system.membus.snoop_fanout::0 439 100.00% 100.00% # Request fanout histogram 46system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 47system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 48system.membus.snoop_fanout::min_value 0 # Request fanout histogram 49system.membus.snoop_fanout::max_value 0 # Request fanout histogram 50system.membus.snoop_fanout::total 439 # Request fanout histogram |
51system.membus.reqLayer0.occupancy 439000 # Layer occupancy (ticks) 52system.membus.reqLayer0.utilization 1.4 # Layer utilization (%) 53system.membus.respLayer1.occupancy 3951000 # Layer occupancy (ticks) 54system.membus.respLayer1.utilization 12.5 # Layer utilization (%) 55system.cpu_clk_domain.clock 500 # Clock period in ticks 56system.cpu.dtb.read_hits 0 # DTB read hits 57system.cpu.dtb.read_misses 0 # DTB read misses 58system.cpu.dtb.read_accesses 0 # DTB read accesses --- 385 unchanged lines hidden (view full) --- 444system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency 445system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency 446system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency 447system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 448system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 449system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency 450system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency 451system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate |
452system.cpu.toL2Bus.trans_dist::ReadReq 390 # Transaction distribution 453system.cpu.toL2Bus.trans_dist::ReadResp 390 # Transaction distribution 454system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 455system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 456system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 606 # Packet count per connected master and slave (bytes) 457system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 276 # Packet count per connected master and slave (bytes) 458system.cpu.toL2Bus.pkt_count::total 882 # Packet count per connected master and slave (bytes) |
459system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 19392 # Cumulative packet size per connected master and slave (bytes) 460system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 8832 # Cumulative packet size per connected master and slave (bytes) 461system.cpu.toL2Bus.pkt_size::total 28224 # Cumulative packet size per connected master and slave (bytes) 462system.cpu.toL2Bus.snoops 0 # Total snoops (count) 463system.cpu.toL2Bus.snoop_fanout::samples 441 # Request fanout histogram 464system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 465system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 466system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 467system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 468system.cpu.toL2Bus.snoop_fanout::1 441 100.00% 100.00% # Request fanout histogram 469system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 470system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 471system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 472system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 473system.cpu.toL2Bus.snoop_fanout::total 441 # Request fanout histogram |
474system.cpu.toL2Bus.reqLayer0.occupancy 220500 # Layer occupancy (ticks) 475system.cpu.toL2Bus.reqLayer0.utilization 0.7 # Layer utilization (%) 476system.cpu.toL2Bus.respLayer0.occupancy 454500 # Layer occupancy (ticks) 477system.cpu.toL2Bus.respLayer0.utilization 1.4 # Layer utilization (%) 478system.cpu.toL2Bus.respLayer1.occupancy 207000 # Layer occupancy (ticks) 479system.cpu.toL2Bus.respLayer1.utilization 0.7 # Layer utilization (%) 480 481---------- End Simulation Statistics ---------- |