4,5c4,5
< sim_ticks 33413000 # Number of ticks simulated
< final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 33399000 # Number of ticks simulated
> final_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 168189 # Simulator instruction rate (inst/s)
< host_op_rate 168105 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 963489284 # Simulator tick rate (ticks/s)
< host_mem_usage 219036 # Number of bytes of host memory used
---
> host_inst_rate 212162 # Simulator instruction rate (inst/s)
> host_op_rate 212025 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1217250605 # Simulator tick rate (ticks/s)
> host_mem_usage 223376 # Number of bytes of host memory used
12,13c12,13
< sim_insts 5827 # Number of instructions simulated
< sim_ops 5827 # Number of ops (including micro ops) simulated
---
> sim_insts 5814 # Number of instructions simulated
> sim_ops 5814 # Number of ops (including micro ops) simulated
22,29c22,29
< system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s)
49c49
< system.cpu.numCycles 66826 # number of cpu cycles simulated
---
> system.cpu.numCycles 66798 # number of cpu cycles simulated
52,54c52,54
< system.cpu.committedInsts 5827 # Number of instructions committed
< system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
---
> system.cpu.committedInsts 5814 # Number of instructions committed
> system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
57,58c57,58
< system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
< system.cpu.num_int_insts 5126 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
> system.cpu.num_int_insts 5113 # number of integer instructions
60,61c60,61
< system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
< system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
> system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
64,65c64,65
< system.cpu.num_mem_refs 2090 # number of memory refs
< system.cpu.num_load_insts 1164 # Number of load instructions
---
> system.cpu.num_mem_refs 2089 # number of memory refs
> system.cpu.num_load_insts 1163 # Number of load instructions
68c68
< system.cpu.num_busy_cycles 66826 # Number of busy cycles
---
> system.cpu.num_busy_cycles 66798 # Number of busy cycles
72,73c72,73
< system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use
< system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use
> system.cpu.icache.total_refs 5513 # Total number of references to valid blocks.
75c75
< system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks.
77,85c77,85
< system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits
< system.cpu.icache.overall_hits::total 5526 # number of overall hits
---
> system.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits
> system.cpu.icache.overall_hits::total 5513 # number of overall hits
98,109c98,109
< system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses
136,141c136,141
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses
150,151c150,151
< system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use
< system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use
> system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
153c153
< system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
155,159c155,159
< system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits
---
> system.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
162,165c162,165
< system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits
< system.cpu.dcache.overall_hits::total 1951 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
> system.cpu.dcache.overall_hits::total 1950 # number of overall hits
182,183c182,183
< system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
186,191c186,191
< system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
194,197c194,197
< system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
230,231c230,231
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
234,237c234,237
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
248c248
< system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use
253,257c253,257
< system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy
< sim_ticks 33413000 # Number of ticks simulated
< final_tick 33413000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 33399000 # Number of ticks simulated
> final_tick 33399000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,10c7,10
< host_inst_rate 168189 # Simulator instruction rate (inst/s)
< host_op_rate 168105 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 963489284 # Simulator tick rate (ticks/s)
< host_mem_usage 219036 # Number of bytes of host memory used
---
> host_inst_rate 212162 # Simulator instruction rate (inst/s)
> host_op_rate 212025 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1217250605 # Simulator tick rate (ticks/s)
> host_mem_usage 223376 # Number of bytes of host memory used
12,13c12,13
< sim_insts 5827 # Number of instructions simulated
< sim_ops 5827 # Number of ops (including micro ops) simulated
---
> sim_insts 5814 # Number of instructions simulated
> sim_ops 5814 # Number of ops (including micro ops) simulated
22,29c22,29
< system.physmem.bw_read::cpu.inst 576542064 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 264328255 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 840870320 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 576542064 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 576542064 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 576542064 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 264328255 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 840870320 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 576783736 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 264439055 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 841222791 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 576783736 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 576783736 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 576783736 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 264439055 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 841222791 # Total bandwidth to/from this memory (bytes/s)
49c49
< system.cpu.numCycles 66826 # number of cpu cycles simulated
---
> system.cpu.numCycles 66798 # number of cpu cycles simulated
52,54c52,54
< system.cpu.committedInsts 5827 # Number of instructions committed
< system.cpu.committedOps 5827 # Number of ops (including micro ops) committed
< system.cpu.num_int_alu_accesses 5126 # Number of integer alu accesses
---
> system.cpu.committedInsts 5814 # Number of instructions committed
> system.cpu.committedOps 5814 # Number of ops (including micro ops) committed
> system.cpu.num_int_alu_accesses 5113 # Number of integer alu accesses
57,58c57,58
< system.cpu.num_conditional_control_insts 677 # number of instructions that are conditional controls
< system.cpu.num_int_insts 5126 # number of integer instructions
---
> system.cpu.num_conditional_control_insts 676 # number of instructions that are conditional controls
> system.cpu.num_int_insts 5113 # number of integer instructions
60,61c60,61
< system.cpu.num_int_register_reads 7300 # number of times the integer registers were read
< system.cpu.num_int_register_writes 3409 # number of times the integer registers were written
---
> system.cpu.num_int_register_reads 7284 # number of times the integer registers were read
> system.cpu.num_int_register_writes 3397 # number of times the integer registers were written
64,65c64,65
< system.cpu.num_mem_refs 2090 # number of memory refs
< system.cpu.num_load_insts 1164 # Number of load instructions
---
> system.cpu.num_mem_refs 2089 # number of memory refs
> system.cpu.num_load_insts 1163 # Number of load instructions
68c68
< system.cpu.num_busy_cycles 66826 # Number of busy cycles
---
> system.cpu.num_busy_cycles 66798 # Number of busy cycles
72,73c72,73
< system.cpu.icache.tagsinuse 133.092783 # Cycle average of tags in use
< system.cpu.icache.total_refs 5526 # Total number of references to valid blocks.
---
> system.cpu.icache.tagsinuse 133.141027 # Cycle average of tags in use
> system.cpu.icache.total_refs 5513 # Total number of references to valid blocks.
75c75
< system.cpu.icache.avg_refs 18.237624 # Average number of references to valid blocks.
---
> system.cpu.icache.avg_refs 18.194719 # Average number of references to valid blocks.
77,85c77,85
< system.cpu.icache.occ_blocks::cpu.inst 133.092783 # Average occupied blocks per requestor
< system.cpu.icache.occ_percent::cpu.inst 0.064987 # Average percentage of cache occupancy
< system.cpu.icache.occ_percent::total 0.064987 # Average percentage of cache occupancy
< system.cpu.icache.ReadReq_hits::cpu.inst 5526 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 5526 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 5526 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 5526 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 5526 # number of overall hits
< system.cpu.icache.overall_hits::total 5526 # number of overall hits
---
> system.cpu.icache.occ_blocks::cpu.inst 133.141027 # Average occupied blocks per requestor
> system.cpu.icache.occ_percent::cpu.inst 0.065010 # Average percentage of cache occupancy
> system.cpu.icache.occ_percent::total 0.065010 # Average percentage of cache occupancy
> system.cpu.icache.ReadReq_hits::cpu.inst 5513 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 5513 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 5513 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 5513 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 5513 # number of overall hits
> system.cpu.icache.overall_hits::total 5513 # number of overall hits
98,109c98,109
< system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses
---
> system.cpu.icache.ReadReq_accesses::cpu.inst 5816 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 5816 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 5816 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 5816 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 5816 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 5816 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.052098 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.052098 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.052098 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.052098 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.052098 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.052098 # miss rate for overall accesses
136,141c136,141
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses
---
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.052098 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.052098 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052098 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.052098 # mshr miss rate for overall accesses
150,151c150,151
< system.cpu.dcache.tagsinuse 87.717237 # Cycle average of tags in use
< system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
---
> system.cpu.dcache.tagsinuse 87.742269 # Cycle average of tags in use
> system.cpu.dcache.total_refs 1950 # Total number of references to valid blocks.
153c153
< system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
---
> system.cpu.dcache.avg_refs 14.130435 # Average number of references to valid blocks.
155,159c155,159
< system.cpu.dcache.occ_blocks::cpu.data 87.717237 # Average occupied blocks per requestor
< system.cpu.dcache.occ_percent::cpu.data 0.021415 # Average percentage of cache occupancy
< system.cpu.dcache.occ_percent::total 0.021415 # Average percentage of cache occupancy
< system.cpu.dcache.ReadReq_hits::cpu.data 1077 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1077 # number of ReadReq hits
---
> system.cpu.dcache.occ_blocks::cpu.data 87.742269 # Average occupied blocks per requestor
> system.cpu.dcache.occ_percent::cpu.data 0.021421 # Average percentage of cache occupancy
> system.cpu.dcache.occ_percent::total 0.021421 # Average percentage of cache occupancy
> system.cpu.dcache.ReadReq_hits::cpu.data 1076 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1076 # number of ReadReq hits
162,165c162,165
< system.cpu.dcache.demand_hits::cpu.data 1951 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1951 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1951 # number of overall hits
< system.cpu.dcache.overall_hits::total 1951 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 1950 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1950 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1950 # number of overall hits
> system.cpu.dcache.overall_hits::total 1950 # number of overall hits
182,183c182,183
< system.cpu.dcache.ReadReq_accesses::cpu.data 1164 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_accesses::cpu.data 1163 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1163 # number of ReadReq accesses(hits+misses)
186,191c186,191
< system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2088 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2088 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2088 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2088 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074807 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.074807 # miss rate for ReadReq accesses
194,197c194,197
< system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.066092 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.066092 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.066092 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.066092 # miss rate for overall accesses
230,231c230,231
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074807 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074807 # mshr miss rate for ReadReq accesses
234,237c234,237
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.066092 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066092 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.066092 # mshr miss rate for overall accesses
248c248
< system.cpu.l2cache.tagsinuse 188.818071 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 188.881290 # Cycle average of tags in use
253,257c253,257
< system.cpu.l2cache.occ_blocks::cpu.inst 134.446837 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 54.371234 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_percent::cpu.inst 0.004103 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::cpu.data 0.001659 # Average percentage of cache occupancy
< system.cpu.l2cache.occ_percent::total 0.005762 # Average percentage of cache occupancy
---
> system.cpu.l2cache.occ_blocks::cpu.inst 134.495649 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 54.385641 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_percent::cpu.inst 0.004104 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::cpu.data 0.001660 # Average percentage of cache occupancy
> system.cpu.l2cache.occ_percent::total 0.005764 # Average percentage of cache occupancy