7,11c7,11
< host_inst_rate 273601 # Simulator instruction rate (inst/s)
< host_op_rate 273420 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1504754975 # Simulator tick rate (ticks/s)
< host_mem_usage 214572 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 540307 # Simulator instruction rate (inst/s)
> host_op_rate 539410 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2965678153 # Simulator tick rate (ticks/s)
> host_mem_usage 215020 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28096 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 439 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28096 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 439 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s)
97a105
> system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses
98a107
> system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses
99a109
> system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses
100a111
> system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency
101a113
> system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency
102a115
> system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency
123a137
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses
124a139
> system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses
125a141
> system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses
126a143
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency
127a145
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
128a147
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
171a191
> system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses
172a193
> system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
173a195
> system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses
174a197
> system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses
175a199
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
176a201
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
177a203
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
178a205
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
203a231
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses
204a233
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
205a235
> system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses
206a237
> system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses
207a239
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
208a241
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
209a243
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
210a245
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
263a299
> system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses
264a301
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
266a304
> system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses
268a307
> system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses
270a310
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
271a312
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
273a315
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
275a318
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
307a351
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses
308a353
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
310a356
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses
312a359
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses
314a362
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
315a364
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
317a367
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
319a370
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< host_inst_rate 273601 # Simulator instruction rate (inst/s)
< host_op_rate 273420 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 1504754975 # Simulator tick rate (ticks/s)
< host_mem_usage 214572 # Number of bytes of host memory used
< host_seconds 0.02 # Real time elapsed on the host
---
> host_inst_rate 540307 # Simulator instruction rate (inst/s)
> host_op_rate 539410 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2965678153 # Simulator tick rate (ticks/s)
> host_mem_usage 215020 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 28096 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 439 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 19264 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 8832 # Number of bytes read from this memory
> system.physmem.bytes_read::total 28096 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 19264 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 19264 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 301 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 138 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 439 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 600349040 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 275243082 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 875592122 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 600349040 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 600349040 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 600349040 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 275243082 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 875592122 # Total bandwidth to/from this memory (bytes/s)
97a105
> system.cpu.icache.ReadReq_miss_rate::total 0.051981 # miss rate for ReadReq accesses
98a107
> system.cpu.icache.demand_miss_rate::total 0.051981 # miss rate for demand accesses
99a109
> system.cpu.icache.overall_miss_rate::total 0.051981 # miss rate for overall accesses
100a111
> system.cpu.icache.ReadReq_avg_miss_latency::total 55722.772277 # average ReadReq miss latency
101a113
> system.cpu.icache.demand_avg_miss_latency::total 55722.772277 # average overall miss latency
102a115
> system.cpu.icache.overall_avg_miss_latency::total 55722.772277 # average overall miss latency
123a137
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.051981 # mshr miss rate for ReadReq accesses
124a139
> system.cpu.icache.demand_mshr_miss_rate::total 0.051981 # mshr miss rate for demand accesses
125a141
> system.cpu.icache.overall_mshr_miss_rate::total 0.051981 # mshr miss rate for overall accesses
126a143
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52722.772277 # average ReadReq mshr miss latency
127a145
> system.cpu.icache.demand_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
128a147
> system.cpu.icache.overall_avg_mshr_miss_latency::total 52722.772277 # average overall mshr miss latency
171a191
> system.cpu.dcache.ReadReq_miss_rate::total 0.074742 # miss rate for ReadReq accesses
172a193
> system.cpu.dcache.WriteReq_miss_rate::total 0.055135 # miss rate for WriteReq accesses
173a195
> system.cpu.dcache.demand_miss_rate::total 0.066060 # miss rate for demand accesses
174a197
> system.cpu.dcache.overall_miss_rate::total 0.066060 # miss rate for overall accesses
175a199
> system.cpu.dcache.ReadReq_avg_miss_latency::total 56000 # average ReadReq miss latency
176a201
> system.cpu.dcache.WriteReq_avg_miss_latency::total 56000 # average WriteReq miss latency
177a203
> system.cpu.dcache.demand_avg_miss_latency::total 56000 # average overall miss latency
178a205
> system.cpu.dcache.overall_avg_miss_latency::total 56000 # average overall miss latency
203a231
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.074742 # mshr miss rate for ReadReq accesses
204a233
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
205a235
> system.cpu.dcache.demand_mshr_miss_rate::total 0.066060 # mshr miss rate for demand accesses
206a237
> system.cpu.dcache.overall_mshr_miss_rate::total 0.066060 # mshr miss rate for overall accesses
207a239
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
208a241
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
209a243
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
210a245
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
263a299
> system.cpu.l2cache.ReadReq_miss_rate::total 0.994872 # miss rate for ReadReq accesses
264a301
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
266a304
> system.cpu.l2cache.demand_miss_rate::total 0.995465 # miss rate for demand accesses
268a307
> system.cpu.l2cache.overall_miss_rate::total 0.995465 # miss rate for overall accesses
270a310
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
271a312
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
273a315
> system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
275a318
> system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
307a351
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.994872 # mshr miss rate for ReadReq accesses
308a353
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
310a356
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.995465 # mshr miss rate for demand accesses
312a359
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.995465 # mshr miss rate for overall accesses
314a362
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
315a364
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
317a367
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
319a370
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency