4,5c4,5
< sim_ticks 33932500 # Number of ticks simulated
< final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 34362500 # Number of ticks simulated
> final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 18620 # Simulator instruction rate (inst/s)
< host_op_rate 18619 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 111991731 # Simulator tick rate (ticks/s)
< host_mem_usage 246380 # Number of bytes of host memory used
< host_seconds 0.30 # Real time elapsed on the host
---
> host_inst_rate 251821 # Simulator instruction rate (inst/s)
> host_op_rate 251667 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1532173253 # Simulator tick rate (ticks/s)
> host_mem_usage 250252 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
54,55c54,55
< system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 67865 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 68725 # number of cpu cycles simulated
74c74
< system.cpu.num_busy_cycles 67865 # Number of busy cycles
---
> system.cpu.num_busy_cycles 68725 # Number of busy cycles
113c113
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
115c115
< system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use
120,122c120,122
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy
129c129
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
146,153c146,153
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles
170,177c170,177
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
192,199c192,199
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles
208,216c208,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
218c218
< system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use
223,225c223,225
< system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy
232c232
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
245,250c245,250
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles
263,268c263,268
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency
283,288c283,288
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles
295,301c295,301
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
303c303
< system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use
305,306c305,306
< system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks.
308,309c308,309
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor
311,316c311,316
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id
319c319
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
340,351c340,351
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles
378,389c378,389
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency
408,419c408,419
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles
432,443c432,443
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
450c450
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
482c482,488
< system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
< sim_ticks 33932500 # Number of ticks simulated
< final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 34362500 # Number of ticks simulated
> final_tick 34362500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 18620 # Simulator instruction rate (inst/s)
< host_op_rate 18619 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 111991731 # Simulator tick rate (ticks/s)
< host_mem_usage 246380 # Number of bytes of host memory used
< host_seconds 0.30 # Real time elapsed on the host
---
> host_inst_rate 251821 # Simulator instruction rate (inst/s)
> host_op_rate 251667 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 1532173253 # Simulator tick rate (ticks/s)
> host_mem_usage 250252 # Number of bytes of host memory used
> host_seconds 0.02 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
25,33c25,33
< system.physmem.bw_read::cpu.inst 552626538 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 258395344 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 811021882 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 552626538 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 552626538 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 552626538 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 258395344 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 811021882 # Total bandwidth to/from this memory (bytes/s)
< system.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.physmem.bw_read::cpu.inst 545711168 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 255161877 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 800873045 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 545711168 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 545711168 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 545711168 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 255161877 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 800873045 # Total bandwidth to/from this memory (bytes/s)
> system.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
54,55c54,55
< system.cpu.pwrStateResidencyTicks::ON 33932500 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 67865 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 34362500 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 68725 # number of cpu cycles simulated
74c74
< system.cpu.num_busy_cycles 67865 # Number of busy cycles
---
> system.cpu.num_busy_cycles 68725 # Number of busy cycles
113c113
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
115c115
< system.cpu.dcache.tags.tagsinuse 86.030444 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 86.019878 # Cycle average of tags in use
120,122c120,122
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.030444 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021004 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021004 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.019878 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021001 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021001 # Average percentage of cache occupancy
129c129
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
146,153c146,153
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 5394000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 5394000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 3100000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 3100000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 8494000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 8494000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 8494000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 8494000 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 5481000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 5481000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 3150000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 3150000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 8631000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 8631000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 8631000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 8631000 # number of overall miss cycles
170,177c170,177
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 62000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 62000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 62000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 63000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 63000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 63000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 63000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63000 # average overall miss latency
192,199c192,199
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5307000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 5307000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3050000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3050000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8357000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 8357000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8357000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 8357000 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5394000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 5394000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3100000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3100000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 8494000 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8494000 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 8494000 # number of overall MSHR miss cycles
208,216c208,216
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 62000 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 62000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 62000 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 62000 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
218c218
< system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 128.944610 # Cycle average of tags in use
223,225c223,225
< system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.062965 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 128.944610 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.062961 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.062961 # Average percentage of cache occupancy
232c232
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
245,250c245,250
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 18192500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 18192500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 18192500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 18192500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 18192500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 18192500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 18485500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 18485500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 18485500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 18485500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 18485500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 18485500 # number of overall miss cycles
263,268c263,268
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 61669.491525 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 61669.491525 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 61669.491525 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 62662.711864 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 62662.711864 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 62662.711864 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 62662.711864 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 62662.711864 # average overall miss latency
283,288c283,288
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17897500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 17897500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17897500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 17897500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17897500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 17897500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 18190500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 18190500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 18190500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 18190500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 18190500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 18190500 # number of overall MSHR miss cycles
295,301c295,301
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 61662.711864 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 61662.711864 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 61662.711864 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 61662.711864 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
303c303
< system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 216.139082 # Cycle average of tags in use
305,306c305,306
< system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 430 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.034884 # Average number of references to valid blocks.
308,309c308,309
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.077342 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 86.061740 # Average occupied blocks per requestor
311,316c311,316
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001630 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.005600 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 380 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 125 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 255 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.011597 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002626 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.006596 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 430 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 130 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 300 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013123 # Percentage of cache occupancy per task id
319c319
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
340,351c340,351
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2975000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2975000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17434000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 17434000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5176500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 5176500 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 17434000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 25585500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 17434000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 25585500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3025000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3025000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 17727000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 17727000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 5263500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 5263500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 17727000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 8288500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 26015500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 17727000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 8288500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 26015500 # number of overall miss cycles
378,389c378,389
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 59500 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 59501.706485 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 59501.706485 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 59500 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 59501.162791 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 59501.706485 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 60500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 60501.706485 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 60501.706485 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 60500 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 60501.162791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 60501.706485 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 60501.162791 # average overall miss latency
408,419c408,419
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2475000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2475000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14504000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14504000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4306500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4306500 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14504000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6781500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 21285500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14504000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6781500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 21285500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2525000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2525000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 14797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 14797000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 4393500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 4393500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 14797000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6918500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 21715500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 14797000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6918500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 21715500 # number of overall MSHR miss cycles
432,443c432,443
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 49500 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 49501.706485 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 49501.706485 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 50500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 50501.706485 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 50501.706485 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 50500 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 50501.706485 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 50500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 50501.162791 # average overall mshr miss latency
450c450
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states
482c482,488
< system.membus.pwrStateResidencyTicks::UNDEFINED 33932500 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 430 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 34362500 # Cumulative time (in ticks) in various power states