4,5c4,5
< sim_ticks 30902000 # Number of ticks simulated
< final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30902500 # Number of ticks simulated
> final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 104539 # Simulator instruction rate (inst/s)
< host_op_rate 104503 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 574021463 # Simulator tick rate (ticks/s)
< host_mem_usage 276192 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 544856 # Simulator instruction rate (inst/s)
> host_op_rate 544118 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2985748792 # Simulator tick rate (ticks/s)
> host_mem_usage 288768 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
24,54c24,31
< system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 380 # Transaction distribution
< system.membus.trans_dist::ReadResp 380 # Transaction distribution
< system.membus.trans_dist::ReadExReq 50 # Transaction distribution
< system.membus.trans_dist::ReadExResp 50 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 430 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 430 # Request fanout histogram
< system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.5 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s)
75c52
< system.cpu.numCycles 61804 # number of cpu cycles simulated
---
> system.cpu.numCycles 61805 # number of cpu cycles simulated
94c71
< system.cpu.num_busy_cycles 61804 # Number of busy cycles
---
> system.cpu.num_busy_cycles 61805 # Number of busy cycles
132a110,213
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
> system.cpu.dcache.overall_hits::total 1896 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
> system.cpu.dcache.overall_misses::total 137 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
134c215
< system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use
139,141c220,222
< system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy
160,165c241,246
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles
178,183c259,264
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency
198,203c279,284
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles
210,215c291,296
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
218c299
< system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use
223,224c304,305
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor
251,261c332,342
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles
284,294c365,375
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency
314,324c395,405
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles
336,346c417,427
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
348,451d428
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
< system.cpu.dcache.overall_hits::total 1896 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
< system.cpu.dcache.overall_misses::total 137 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
479a457,479
> system.membus.trans_dist::ReadReq 380 # Transaction distribution
> system.membus.trans_dist::ReadResp 380 # Transaction distribution
> system.membus.trans_dist::ReadExReq 50 # Transaction distribution
> system.membus.trans_dist::ReadExResp 50 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 430 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 430 # Request fanout histogram
> system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.0 # Layer utilization (%)
< sim_ticks 30902000 # Number of ticks simulated
< final_tick 30902000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 30902500 # Number of ticks simulated
> final_tick 30902500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 104539 # Simulator instruction rate (inst/s)
< host_op_rate 104503 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 574021463 # Simulator tick rate (ticks/s)
< host_mem_usage 276192 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 544856 # Simulator instruction rate (inst/s)
> host_op_rate 544118 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 2985748792 # Simulator tick rate (ticks/s)
> host_mem_usage 288768 # Number of bytes of host memory used
> host_seconds 0.01 # Real time elapsed on the host
24,54c24,31
< system.physmem.bw_read::cpu.inst 606821565 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 283735681 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 890557245 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 606821565 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 606821565 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 606821565 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 283735681 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 890557245 # Total bandwidth to/from this memory (bytes/s)
< system.membus.trans_dist::ReadReq 380 # Transaction distribution
< system.membus.trans_dist::ReadResp 380 # Transaction distribution
< system.membus.trans_dist::ReadExReq 50 # Transaction distribution
< system.membus.trans_dist::ReadExResp 50 # Transaction distribution
< system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
< system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
< system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
< system.membus.snoops 0 # Total snoops (count)
< system.membus.snoop_fanout::samples 430 # Request fanout histogram
< system.membus.snoop_fanout::mean 0 # Request fanout histogram
< system.membus.snoop_fanout::stdev 0 # Request fanout histogram
< system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
< system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
< system.membus.snoop_fanout::min_value 0 # Request fanout histogram
< system.membus.snoop_fanout::max_value 0 # Request fanout histogram
< system.membus.snoop_fanout::total 430 # Request fanout histogram
< system.membus.reqLayer0.occupancy 430000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
< system.membus.respLayer1.occupancy 3870000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 12.5 # Layer utilization (%)
---
> system.physmem.bw_read::cpu.inst 606811747 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 283731090 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 890542836 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 606811747 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 606811747 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 606811747 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 283731090 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 890542836 # Total bandwidth to/from this memory (bytes/s)
75c52
< system.cpu.numCycles 61804 # number of cpu cycles simulated
---
> system.cpu.numCycles 61805 # number of cpu cycles simulated
94c71
< system.cpu.num_busy_cycles 61804 # Number of busy cycles
---
> system.cpu.num_busy_cycles 61805 # Number of busy cycles
132a110,213
> system.cpu.dcache.tags.replacements 0 # number of replacements
> system.cpu.dcache.tags.tagsinuse 86.155054 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
> system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
> system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
> system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
> system.cpu.dcache.tags.occ_blocks::cpu.data 86.155054 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.021034 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.021034 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
> system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
> system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
> system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
> system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
> system.cpu.dcache.overall_hits::total 1896 # number of overall hits
> system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
> system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
> system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
> system.cpu.dcache.overall_misses::total 137 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
> system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
> system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
> system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
> system.cpu.dcache.fast_writes 0 # number of fast writes performed
> system.cpu.dcache.cache_copies 0 # number of cache copies performed
> system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
> system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
> system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
> system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
> system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
> system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4654500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 4654500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2675000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 2675000 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7329500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 7329500 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7329500 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 7329500 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53500 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53500 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53500 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 53500 # average overall mshr miss latency
> system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
134c215
< system.cpu.icache.tags.tagsinuse 129.108186 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 129.101534 # Cycle average of tags in use
139,141c220,222
< system.cpu.icache.tags.occ_blocks::cpu.inst 129.108186 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.063041 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.063041 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 129.101534 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.063038 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.063038 # Average percentage of cache occupancy
160,165c241,246
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 16141000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 16141000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 16141000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 16141000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 16141000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 16141500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 16141500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 16141500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 16141500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 16141500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 16141500 # number of overall miss cycles
178,183c259,264
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54715.254237 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 54715.254237 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 54715.254237 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 54715.254237 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 54715.254237 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 54716.949153 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 54716.949153 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 54716.949153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 54716.949153 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 54716.949153 # average overall miss latency
198,203c279,284
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15551000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 15551000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 15551000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15551000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 15551000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15699000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 15699000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15699000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 15699000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15699000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 15699000 # number of overall MSHR miss cycles
210,215c291,296
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52715.254237 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52715.254237 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52715.254237 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 52715.254237 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 53216.949153 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 53216.949153 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 53216.949153 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 53216.949153 # average overall mshr miss latency
218c299
< system.cpu.l2cache.tags.tagsinuse 183.724070 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 183.714965 # Cycle average of tags in use
223,224c304,305
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.264551 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 53.459518 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.257719 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 53.457246 # Average occupied blocks per requestor
251,261c332,342
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15236000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4524000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 19760000 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2600000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 2600000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 15236000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 7124000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 22360000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 15236000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 7124000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 22360000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 15383000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 4567500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 19950500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2625000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 2625000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 15383000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 7192500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 22575500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 15383000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 7192500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 22575500 # number of overall miss cycles
284,294c365,375
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 52000 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52000 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 52000 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52501.706485 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52500 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 52501.315789 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52500 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52500 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 52501.162791 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52501.706485 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52500 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 52501.162791 # average overall miss latency
314,324c395,405
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11720000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3480000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15200000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2000000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2000000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11720000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5480000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 17200000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11720000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5480000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 17200000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 11866500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 3523500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 15390000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2025000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2025000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 11866500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5548500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 17415000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 11866500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5548500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 17415000 # number of overall MSHR miss cycles
336,346c417,427
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40000 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40000 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40000 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 40500 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40500 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40500 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 40500 # average overall mshr miss latency
348,451d428
< system.cpu.dcache.tags.replacements 0 # number of replacements
< system.cpu.dcache.tags.tagsinuse 86.158665 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 1896 # Total number of references to valid blocks.
< system.cpu.dcache.tags.sampled_refs 137 # Sample count of references to valid blocks.
< system.cpu.dcache.tags.avg_refs 13.839416 # Average number of references to valid blocks.
< system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
< system.cpu.dcache.tags.occ_blocks::cpu.data 86.158665 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.021035 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.021035 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_task_id_blocks::1024 137 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 26 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 111 # Occupied blocks per task id
< system.cpu.dcache.tags.occ_task_id_percent::1024 0.033447 # Percentage of cache occupancy per task id
< system.cpu.dcache.tags.tag_accesses 4203 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 4203 # Number of data accesses
< system.cpu.dcache.ReadReq_hits::cpu.data 1045 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1045 # number of ReadReq hits
< system.cpu.dcache.WriteReq_hits::cpu.data 851 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 851 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 1896 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 1896 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 1896 # number of overall hits
< system.cpu.dcache.overall_hits::total 1896 # number of overall hits
< system.cpu.dcache.ReadReq_misses::cpu.data 87 # number of ReadReq misses
< system.cpu.dcache.ReadReq_misses::total 87 # number of ReadReq misses
< system.cpu.dcache.WriteReq_misses::cpu.data 50 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 50 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 137 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 137 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 137 # number of overall misses
< system.cpu.dcache.overall_misses::total 137 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 4785000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 4785000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 2750000 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 2750000 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 7535000 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 7535000 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 7535000 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 7535000 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 1132 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 1132 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
< system.cpu.dcache.demand_accesses::cpu.data 2033 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2033 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2033 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2033 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.076855 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.076855 # miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055494 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.055494 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.067388 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.067388 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.067388 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.067388 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55000 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 55000 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 55000 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 55000 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 55000 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 55000 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
< system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
< system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
< system.cpu.dcache.fast_writes 0 # number of fast writes performed
< system.cpu.dcache.cache_copies 0 # number of cache copies performed
< system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
< system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
< system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
< system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
< system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
< system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 4611000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2650000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 2650000 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7261000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 7261000 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7261000 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 7261000 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.076855 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.076855 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.067388 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.067388 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.067388 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 53000 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 53000 # average overall mshr miss latency
< system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
479a457,479
> system.membus.trans_dist::ReadReq 380 # Transaction distribution
> system.membus.trans_dist::ReadResp 380 # Transaction distribution
> system.membus.trans_dist::ReadExReq 50 # Transaction distribution
> system.membus.trans_dist::ReadExResp 50 # Transaction distribution
> system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 860 # Packet count per connected master and slave (bytes)
> system.membus.pkt_count::total 860 # Packet count per connected master and slave (bytes)
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 27520 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 27520 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 430 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 430 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 430 # Request fanout histogram
> system.membus.reqLayer0.occupancy 430500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 1.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2150500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 7.0 # Layer utilization (%)