1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000032 # Number of seconds simulated
4sim_ticks 32088000 # Number of ticks simulated
5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 273601 # Simulator instruction rate (inst/s)
8host_op_rate 273420 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1504754975 # Simulator tick rate (ticks/s)
10host_mem_usage 214572 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 5827 # Number of instructions simulated
13sim_ops 5827 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28096 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 439 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.read_hits 0 # DTB read hits
24system.cpu.dtb.read_misses 0 # DTB read misses
25system.cpu.dtb.read_accesses 0 # DTB read accesses
26system.cpu.dtb.write_hits 0 # DTB write hits
27system.cpu.dtb.write_misses 0 # DTB write misses
28system.cpu.dtb.write_accesses 0 # DTB write accesses
29system.cpu.dtb.hits 0 # DTB hits
30system.cpu.dtb.misses 0 # DTB misses
--- 59 unchanged lines hidden (view full) ---
90system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles
91system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
92system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
93system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
94system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
95system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
96system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
97system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
98system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
99system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
100system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
102system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
103system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
104system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
108system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
109system.cpu.icache.fast_writes 0 # number of fast writes performed
110system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 5 unchanged lines hidden (view full) ---
116system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
117system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
119system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
120system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
121system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
122system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
123system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
124system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
125system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
126system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
127system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
129system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
130system.cpu.dcache.replacements 0 # number of replacements
131system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
132system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
133system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
134system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
135system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
164system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
165system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
166system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
167system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
168system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
169system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
170system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
171system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses
172system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
173system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses
174system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses
175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
177system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
178system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
183system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
184system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
185system.cpu.dcache.fast_writes 0 # number of fast writes performed
186system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 9 unchanged lines hidden (view full) ---
196system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
198system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
199system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
200system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
201system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
202system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
203system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
204system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
209system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
210system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
212system.cpu.l2cache.replacements 0 # number of replacements
213system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
214system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
215system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
216system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
217system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
218system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
256system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses
257system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
258system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
259system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses
260system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
261system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
262system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses
263system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
264system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
265system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses
266system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
267system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses
268system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
270system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
271system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
276system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
277system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
278system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
279system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
280system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
281system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
282system.cpu.l2cache.fast_writes 0 # number of fast writes performed
283system.cpu.l2cache.cache_copies 0 # number of cache copies performed
--- 16 unchanged lines hidden (view full) ---
300system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles
301system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
302system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
303system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
304system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
305system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
306system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
307system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
308system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
309system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
310system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
311system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
312system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
313system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
314system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
316system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
320system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
321
322---------- End Simulation Statistics ----------
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000032 # Number of seconds simulated
4sim_ticks 32088000 # Number of ticks simulated
5final_tick 32088000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 273601 # Simulator instruction rate (inst/s)
8host_op_rate 273420 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 1504754975 # Simulator tick rate (ticks/s)
10host_mem_usage 214572 # Number of bytes of host memory used
11host_seconds 0.02 # Real time elapsed on the host
12sim_insts 5827 # Number of instructions simulated
13sim_ops 5827 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read 28096 # Number of bytes read from this memory
15system.physmem.bytes_inst_read 19264 # Number of instructions bytes read from this memory
16system.physmem.bytes_written 0 # Number of bytes written to this memory
17system.physmem.num_reads 439 # Number of read requests responded to by this memory
18system.physmem.num_writes 0 # Number of write requests responded to by this memory
19system.physmem.num_other 0 # Number of other requests responded to by this memory
20system.physmem.bw_read 875592122 # Total read bandwidth from this memory (bytes/s)
21system.physmem.bw_inst_read 600349040 # Instruction read bandwidth from this memory (bytes/s)
22system.physmem.bw_total 875592122 # Total bandwidth to/from this memory (bytes/s)
23system.cpu.dtb.read_hits 0 # DTB read hits
24system.cpu.dtb.read_misses 0 # DTB read misses
25system.cpu.dtb.read_accesses 0 # DTB read accesses
26system.cpu.dtb.write_hits 0 # DTB write hits
27system.cpu.dtb.write_misses 0 # DTB write misses
28system.cpu.dtb.write_accesses 0 # DTB write accesses
29system.cpu.dtb.hits 0 # DTB hits
30system.cpu.dtb.misses 0 # DTB misses
--- 59 unchanged lines hidden (view full) ---
90system.cpu.icache.overall_miss_latency::total 16884000 # number of overall miss cycles
91system.cpu.icache.ReadReq_accesses::cpu.inst 5829 # number of ReadReq accesses(hits+misses)
92system.cpu.icache.ReadReq_accesses::total 5829 # number of ReadReq accesses(hits+misses)
93system.cpu.icache.demand_accesses::cpu.inst 5829 # number of demand (read+write) accesses
94system.cpu.icache.demand_accesses::total 5829 # number of demand (read+write) accesses
95system.cpu.icache.overall_accesses::cpu.inst 5829 # number of overall (read+write) accesses
96system.cpu.icache.overall_accesses::total 5829 # number of overall (read+write) accesses
97system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.051981 # miss rate for ReadReq accesses
98system.cpu.icache.demand_miss_rate::cpu.inst 0.051981 # miss rate for demand accesses
99system.cpu.icache.overall_miss_rate::cpu.inst 0.051981 # miss rate for overall accesses
100system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 55722.772277 # average ReadReq miss latency
101system.cpu.icache.demand_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
102system.cpu.icache.overall_avg_miss_latency::cpu.inst 55722.772277 # average overall miss latency
103system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
104system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
105system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
106system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
107system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
108system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
109system.cpu.icache.fast_writes 0 # number of fast writes performed
110system.cpu.icache.cache_copies 0 # number of cache copies performed
--- 5 unchanged lines hidden (view full) ---
116system.cpu.icache.overall_mshr_misses::total 303 # number of overall MSHR misses
117system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 15975000 # number of ReadReq MSHR miss cycles
118system.cpu.icache.ReadReq_mshr_miss_latency::total 15975000 # number of ReadReq MSHR miss cycles
119system.cpu.icache.demand_mshr_miss_latency::cpu.inst 15975000 # number of demand (read+write) MSHR miss cycles
120system.cpu.icache.demand_mshr_miss_latency::total 15975000 # number of demand (read+write) MSHR miss cycles
121system.cpu.icache.overall_mshr_miss_latency::cpu.inst 15975000 # number of overall MSHR miss cycles
122system.cpu.icache.overall_mshr_miss_latency::total 15975000 # number of overall MSHR miss cycles
123system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for ReadReq accesses
124system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for demand accesses
125system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.051981 # mshr miss rate for overall accesses
126system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52722.772277 # average ReadReq mshr miss latency
127system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
128system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52722.772277 # average overall mshr miss latency
129system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
130system.cpu.dcache.replacements 0 # number of replacements
131system.cpu.dcache.tagsinuse 87.458397 # Cycle average of tags in use
132system.cpu.dcache.total_refs 1951 # Total number of references to valid blocks.
133system.cpu.dcache.sampled_refs 138 # Sample count of references to valid blocks.
134system.cpu.dcache.avg_refs 14.137681 # Average number of references to valid blocks.
135system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
136system.cpu.dcache.occ_blocks::cpu.data 87.458397 # Average occupied blocks per requestor
--- 27 unchanged lines hidden (view full) ---
164system.cpu.dcache.ReadReq_accesses::total 1164 # number of ReadReq accesses(hits+misses)
165system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
166system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
167system.cpu.dcache.demand_accesses::cpu.data 2089 # number of demand (read+write) accesses
168system.cpu.dcache.demand_accesses::total 2089 # number of demand (read+write) accesses
169system.cpu.dcache.overall_accesses::cpu.data 2089 # number of overall (read+write) accesses
170system.cpu.dcache.overall_accesses::total 2089 # number of overall (read+write) accesses
171system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074742 # miss rate for ReadReq accesses
172system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.055135 # miss rate for WriteReq accesses
173system.cpu.dcache.demand_miss_rate::cpu.data 0.066060 # miss rate for demand accesses
174system.cpu.dcache.overall_miss_rate::cpu.data 0.066060 # miss rate for overall accesses
175system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 56000 # average ReadReq miss latency
176system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 56000 # average WriteReq miss latency
177system.cpu.dcache.demand_avg_miss_latency::cpu.data 56000 # average overall miss latency
178system.cpu.dcache.overall_avg_miss_latency::cpu.data 56000 # average overall miss latency
179system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
180system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
181system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
182system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
183system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
184system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
185system.cpu.dcache.fast_writes 0 # number of fast writes performed
186system.cpu.dcache.cache_copies 0 # number of cache copies performed
--- 9 unchanged lines hidden (view full) ---
196system.cpu.dcache.ReadReq_mshr_miss_latency::total 4611000 # number of ReadReq MSHR miss cycles
197system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2703000 # number of WriteReq MSHR miss cycles
198system.cpu.dcache.WriteReq_mshr_miss_latency::total 2703000 # number of WriteReq MSHR miss cycles
199system.cpu.dcache.demand_mshr_miss_latency::cpu.data 7314000 # number of demand (read+write) MSHR miss cycles
200system.cpu.dcache.demand_mshr_miss_latency::total 7314000 # number of demand (read+write) MSHR miss cycles
201system.cpu.dcache.overall_mshr_miss_latency::cpu.data 7314000 # number of overall MSHR miss cycles
202system.cpu.dcache.overall_mshr_miss_latency::total 7314000 # number of overall MSHR miss cycles
203system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.074742 # mshr miss rate for ReadReq accesses
204system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
205system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for demand accesses
206system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.066060 # mshr miss rate for overall accesses
207system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 53000 # average ReadReq mshr miss latency
208system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53000 # average WriteReq mshr miss latency
209system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
210system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 53000 # average overall mshr miss latency
211system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
212system.cpu.l2cache.replacements 0 # number of replacements
213system.cpu.l2cache.tagsinuse 188.045319 # Cycle average of tags in use
214system.cpu.l2cache.total_refs 2 # Total number of references to valid blocks.
215system.cpu.l2cache.sampled_refs 388 # Sample count of references to valid blocks.
216system.cpu.l2cache.avg_refs 0.005155 # Average number of references to valid blocks.
217system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
218system.cpu.l2cache.occ_blocks::cpu.inst 133.837577 # Average occupied blocks per requestor
--- 37 unchanged lines hidden (view full) ---
256system.cpu.l2cache.demand_accesses::cpu.inst 303 # number of demand (read+write) accesses
257system.cpu.l2cache.demand_accesses::cpu.data 138 # number of demand (read+write) accesses
258system.cpu.l2cache.demand_accesses::total 441 # number of demand (read+write) accesses
259system.cpu.l2cache.overall_accesses::cpu.inst 303 # number of overall (read+write) accesses
260system.cpu.l2cache.overall_accesses::cpu.data 138 # number of overall (read+write) accesses
261system.cpu.l2cache.overall_accesses::total 441 # number of overall (read+write) accesses
262system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.993399 # miss rate for ReadReq accesses
263system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
264system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
265system.cpu.l2cache.demand_miss_rate::cpu.inst 0.993399 # miss rate for demand accesses
266system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
267system.cpu.l2cache.overall_miss_rate::cpu.inst 0.993399 # miss rate for overall accesses
268system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
269system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 52000 # average ReadReq miss latency
270system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 52000 # average ReadReq miss latency
271system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52000 # average ReadExReq miss latency
272system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 52000 # average overall miss latency
273system.cpu.l2cache.demand_avg_miss_latency::cpu.data 52000 # average overall miss latency
274system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 52000 # average overall miss latency
275system.cpu.l2cache.overall_avg_miss_latency::cpu.data 52000 # average overall miss latency
276system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
277system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
278system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
279system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
280system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
281system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
282system.cpu.l2cache.fast_writes 0 # number of fast writes performed
283system.cpu.l2cache.cache_copies 0 # number of cache copies performed
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300system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12040000 # number of demand (read+write) MSHR miss cycles
301system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 5520000 # number of demand (read+write) MSHR miss cycles
302system.cpu.l2cache.demand_mshr_miss_latency::total 17560000 # number of demand (read+write) MSHR miss cycles
303system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12040000 # number of overall MSHR miss cycles
304system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 5520000 # number of overall MSHR miss cycles
305system.cpu.l2cache.overall_mshr_miss_latency::total 17560000 # number of overall MSHR miss cycles
306system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for ReadReq accesses
307system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
308system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
309system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for demand accesses
310system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
311system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.993399 # mshr miss rate for overall accesses
312system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
313system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 40000 # average ReadReq mshr miss latency
314system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadReq mshr miss latency
315system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40000 # average ReadExReq mshr miss latency
316system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
317system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
318system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 40000 # average overall mshr miss latency
319system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 40000 # average overall mshr miss latency
320system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
321
322---------- End Simulation Statistics ----------