1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000034 # Number of seconds simulated
4sim_ticks 33932500 # Number of ticks simulated
5final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 442497 # Simulator instruction rate (inst/s)
8host_op_rate 441783 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2653552582 # Simulator tick rate (ticks/s)
10host_mem_usage 249064 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5641 # Number of instructions simulated
13sim_ops 5641 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
--- 151 unchanged lines hidden (view full) ---
171system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
172system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
173system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
174system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
175system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
176system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
177system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
178system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
180system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
182system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
183system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
184system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
185system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
186system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
204system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
206system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
207system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
208system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
209system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
210system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
211system.cpu.icache.tags.replacements 13 # number of replacements
212system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
213system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
214system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
215system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks.
216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
217system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
218system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
260system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
261system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
268system.cpu.icache.writebacks::writebacks 13 # number of writebacks
269system.cpu.icache.writebacks::total 13 # number of writebacks
270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
271system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
272system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
273system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
274system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
275system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses
287system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses
288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
291system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
293system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
294system.cpu.l2cache.tags.replacements 0 # number of replacements
295system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
296system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
297system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
298system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
299system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
300system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
301system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
--- 77 unchanged lines hidden (view full) ---
379system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
380system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
381system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
382system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
383system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
386system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
387system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
388system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
389system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses
390system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses
391system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
392system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses
393system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
394system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
--- 32 unchanged lines hidden (view full) ---
427system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
428system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
429system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
430system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
431system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
432system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
433system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
434system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
435system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
436system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
437system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
438system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
439system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
440system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
441system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
442system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
--- 53 unchanged lines hidden ---
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000034 # Number of seconds simulated
4sim_ticks 33932500 # Number of ticks simulated
5final_tick 33932500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 442497 # Simulator instruction rate (inst/s)
8host_op_rate 441783 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 2653552582 # Simulator tick rate (ticks/s)
10host_mem_usage 249064 # Number of bytes of host memory used
11host_seconds 0.01 # Real time elapsed on the host
12sim_insts 5641 # Number of instructions simulated
13sim_ops 5641 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 18752 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 8768 # Number of bytes read from this memory
18system.physmem.bytes_read::total 27520 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 18752 # Number of instructions bytes read from this memory
--- 151 unchanged lines hidden (view full) ---
171system.cpu.dcache.overall_avg_miss_latency::cpu.data 62000 # average overall miss latency
172system.cpu.dcache.overall_avg_miss_latency::total 62000 # average overall miss latency
173system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
174system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
175system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
176system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
177system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
178system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
179system.cpu.dcache.ReadReq_mshr_misses::cpu.data 87 # number of ReadReq MSHR misses
180system.cpu.dcache.ReadReq_mshr_misses::total 87 # number of ReadReq MSHR misses
181system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
182system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
183system.cpu.dcache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
184system.cpu.dcache.demand_mshr_misses::total 137 # number of demand (read+write) MSHR misses
185system.cpu.dcache.overall_mshr_misses::cpu.data 137 # number of overall MSHR misses
186system.cpu.dcache.overall_mshr_misses::total 137 # number of overall MSHR misses
--- 16 unchanged lines hidden (view full) ---
203system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61000 # average ReadReq mshr miss latency
204system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61000 # average ReadReq mshr miss latency
205system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 61000 # average WriteReq mshr miss latency
206system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 61000 # average WriteReq mshr miss latency
207system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
208system.cpu.dcache.demand_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
209system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61000 # average overall mshr miss latency
210system.cpu.dcache.overall_avg_mshr_miss_latency::total 61000 # average overall mshr miss latency
211system.cpu.icache.tags.replacements 13 # number of replacements
212system.cpu.icache.tags.tagsinuse 128.953338 # Cycle average of tags in use
213system.cpu.icache.tags.total_refs 5348 # Total number of references to valid blocks.
214system.cpu.icache.tags.sampled_refs 295 # Sample count of references to valid blocks.
215system.cpu.icache.tags.avg_refs 18.128814 # Average number of references to valid blocks.
216system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
217system.cpu.icache.tags.occ_blocks::cpu.inst 128.953338 # Average occupied blocks per requestor
218system.cpu.icache.tags.occ_percent::cpu.inst 0.062965 # Average percentage of cache occupancy
--- 41 unchanged lines hidden (view full) ---
260system.cpu.icache.overall_avg_miss_latency::cpu.inst 61669.491525 # average overall miss latency
261system.cpu.icache.overall_avg_miss_latency::total 61669.491525 # average overall miss latency
262system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
263system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
264system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
265system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
266system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
267system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
268system.cpu.icache.writebacks::writebacks 13 # number of writebacks
269system.cpu.icache.writebacks::total 13 # number of writebacks
270system.cpu.icache.ReadReq_mshr_misses::cpu.inst 295 # number of ReadReq MSHR misses
271system.cpu.icache.ReadReq_mshr_misses::total 295 # number of ReadReq MSHR misses
272system.cpu.icache.demand_mshr_misses::cpu.inst 295 # number of demand (read+write) MSHR misses
273system.cpu.icache.demand_mshr_misses::total 295 # number of demand (read+write) MSHR misses
274system.cpu.icache.overall_mshr_misses::cpu.inst 295 # number of overall MSHR misses
275system.cpu.icache.overall_mshr_misses::total 295 # number of overall MSHR misses
--- 10 unchanged lines hidden (view full) ---
286system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.052277 # mshr miss rate for overall accesses
287system.cpu.icache.overall_mshr_miss_rate::total 0.052277 # mshr miss rate for overall accesses
288system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 60669.491525 # average ReadReq mshr miss latency
289system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 60669.491525 # average ReadReq mshr miss latency
290system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
291system.cpu.icache.demand_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
292system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 60669.491525 # average overall mshr miss latency
293system.cpu.icache.overall_avg_mshr_miss_latency::total 60669.491525 # average overall mshr miss latency
294system.cpu.l2cache.tags.replacements 0 # number of replacements
295system.cpu.l2cache.tags.tagsinuse 183.490494 # Cycle average of tags in use
296system.cpu.l2cache.tags.total_refs 15 # Total number of references to valid blocks.
297system.cpu.l2cache.tags.sampled_refs 380 # Sample count of references to valid blocks.
298system.cpu.l2cache.tags.avg_refs 0.039474 # Average number of references to valid blocks.
299system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
300system.cpu.l2cache.tags.occ_blocks::cpu.inst 130.087016 # Average occupied blocks per requestor
301system.cpu.l2cache.tags.occ_blocks::cpu.data 53.403478 # Average occupied blocks per requestor
--- 77 unchanged lines hidden (view full) ---
379system.cpu.l2cache.overall_avg_miss_latency::cpu.data 59500 # average overall miss latency
380system.cpu.l2cache.overall_avg_miss_latency::total 59501.162791 # average overall miss latency
381system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
382system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
383system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
384system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
385system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
386system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
387system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
388system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
389system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 293 # number of ReadCleanReq MSHR misses
390system.cpu.l2cache.ReadCleanReq_mshr_misses::total 293 # number of ReadCleanReq MSHR misses
391system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 87 # number of ReadSharedReq MSHR misses
392system.cpu.l2cache.ReadSharedReq_mshr_misses::total 87 # number of ReadSharedReq MSHR misses
393system.cpu.l2cache.demand_mshr_misses::cpu.inst 293 # number of demand (read+write) MSHR misses
394system.cpu.l2cache.demand_mshr_misses::cpu.data 137 # number of demand (read+write) MSHR misses
--- 32 unchanged lines hidden (view full) ---
427system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 49500 # average ReadSharedReq mshr miss latency
428system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 49500 # average ReadSharedReq mshr miss latency
429system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
430system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
431system.cpu.l2cache.demand_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
432system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 49501.706485 # average overall mshr miss latency
433system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 49500 # average overall mshr miss latency
434system.cpu.l2cache.overall_avg_mshr_miss_latency::total 49501.162791 # average overall mshr miss latency
435system.cpu.toL2Bus.snoop_filter.tot_requests 445 # Total number of requests made to the snoop filter.
436system.cpu.toL2Bus.snoop_filter.hit_single_requests 13 # Number of requests hitting in the snoop filter with a single holder of the requested data.
437system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
438system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
439system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
440system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
441system.cpu.toL2Bus.trans_dist::ReadResp 382 # Transaction distribution
442system.cpu.toL2Bus.trans_dist::WritebackClean 13 # Transaction distribution
--- 53 unchanged lines hidden ---