| stats.txt (11530:6e143fd2cabf) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000100 # Number of seconds simulated 4sim_ticks 100232 # Number of ticks simulated 5final_tick 100232 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000106 # Number of seconds simulated 4sim_ticks 106125 # Number of ticks simulated 5final_tick 106125 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000 # Frequency of simulated ticks | 6sim_freq 1000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93908 # Simulator instruction rate (inst/s) 8host_op_rate 93894 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1668107 # Simulator tick rate (ticks/s) 10host_mem_usage 455812 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 64036 # Simulator instruction rate (inst/s) 8host_op_rate 64023 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 1204237 # Simulator tick rate (ticks/s) 10host_mem_usage 413260 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks | 12sim_insts 5641 # Number of instructions simulated 13sim_ops 5641 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1 # Clock period in ticks |
| 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 16system.mem_ctrls.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 17system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory 19system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory 20system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory 21system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory 22system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory 23system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory 24system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory | 17system.mem_ctrls.bytes_read::ruby.dir_cntrl0 94208 # Number of bytes read from this memory 18system.mem_ctrls.bytes_read::total 94208 # Number of bytes read from this memory 19system.mem_ctrls.bytes_written::ruby.dir_cntrl0 93952 # Number of bytes written to this memory 20system.mem_ctrls.bytes_written::total 93952 # Number of bytes written to this memory 21system.mem_ctrls.num_reads::ruby.dir_cntrl0 1472 # Number of read requests responded to by this memory 22system.mem_ctrls.num_reads::total 1472 # Number of read requests responded to by this memory 23system.mem_ctrls.num_writes::ruby.dir_cntrl0 1468 # Number of write requests responded to by this memory 24system.mem_ctrls.num_writes::total 1468 # Number of write requests responded to by this memory |
| 25system.mem_ctrls.bw_read::ruby.dir_cntrl0 939899433 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_read::total 939899433 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::ruby.dir_cntrl0 937345359 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_write::total 937345359 # Write bandwidth from this memory (bytes/s) 29system.mem_ctrls.bw_total::ruby.dir_cntrl0 1877244792 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.bw_total::total 1877244792 # Total bandwidth to/from this memory (bytes/s) | 25system.mem_ctrls.bw_read::ruby.dir_cntrl0 887707892 # Total read bandwidth from this memory (bytes/s) 26system.mem_ctrls.bw_read::total 887707892 # Total read bandwidth from this memory (bytes/s) 27system.mem_ctrls.bw_write::ruby.dir_cntrl0 885295642 # Write bandwidth from this memory (bytes/s) 28system.mem_ctrls.bw_write::total 885295642 # Write bandwidth from this memory (bytes/s) 29system.mem_ctrls.bw_total::ruby.dir_cntrl0 1773003534 # Total bandwidth to/from this memory (bytes/s) 30system.mem_ctrls.bw_total::total 1773003534 # Total bandwidth to/from this memory (bytes/s) |
| 31system.mem_ctrls.readReqs 1472 # Number of read requests accepted 32system.mem_ctrls.writeReqs 1468 # Number of write requests accepted 33system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue 34system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue | 31system.mem_ctrls.readReqs 1472 # Number of read requests accepted 32system.mem_ctrls.writeReqs 1468 # Number of write requests accepted 33system.mem_ctrls.readBursts 1472 # Number of DRAM read bursts, including those serviced by the write queue 34system.mem_ctrls.writeBursts 1468 # Number of DRAM write bursts, including those merged in the write queue |
| 35system.mem_ctrls.bytesReadDRAM 58752 # Total number of bytes read from DRAM 36system.mem_ctrls.bytesReadWrQ 35456 # Total number of bytes read from write queue 37system.mem_ctrls.bytesWritten 60352 # Total number of bytes written to DRAM | 35system.mem_ctrls.bytesReadDRAM 58880 # Total number of bytes read from DRAM 36system.mem_ctrls.bytesReadWrQ 35328 # Total number of bytes read from write queue 37system.mem_ctrls.bytesWritten 59776 # Total number of bytes written to DRAM |
| 38system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side 39system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side | 38system.mem_ctrls.bytesReadSys 94208 # Total read bytes from the system interface side 39system.mem_ctrls.bytesWrittenSys 93952 # Total written bytes from the system interface side |
| 40system.mem_ctrls.servicedByWrQ 554 # Number of DRAM read bursts serviced by the write queue 41system.mem_ctrls.mergedWrBursts 502 # Number of DRAM write bursts merged with an existing one | 40system.mem_ctrls.servicedByWrQ 552 # Number of DRAM read bursts serviced by the write queue 41system.mem_ctrls.mergedWrBursts 510 # Number of DRAM write bursts merged with an existing one |
| 42system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write | 42system.mem_ctrls.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write |
| 43system.mem_ctrls.perBankRdBursts::0 33 # Per bank write bursts | 43system.mem_ctrls.perBankRdBursts::0 31 # Per bank write bursts |
| 44system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts | 44system.mem_ctrls.perBankRdBursts::1 0 # Per bank write bursts 45system.mem_ctrls.perBankRdBursts::2 0 # Per bank write bursts 46system.mem_ctrls.perBankRdBursts::3 0 # Per bank write bursts 47system.mem_ctrls.perBankRdBursts::4 7 # Per bank write bursts 48system.mem_ctrls.perBankRdBursts::5 3 # Per bank write bursts 49system.mem_ctrls.perBankRdBursts::6 13 # Per bank write bursts |
| 50system.mem_ctrls.perBankRdBursts::7 81 # Per bank write bursts | 50system.mem_ctrls.perBankRdBursts::7 83 # Per bank write bursts |
| 51system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts | 51system.mem_ctrls.perBankRdBursts::8 66 # Per bank write bursts |
| 52system.mem_ctrls.perBankRdBursts::9 245 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::10 98 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::11 45 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::12 114 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::13 45 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::14 154 # Per bank write bursts 58system.mem_ctrls.perBankRdBursts::15 14 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::0 34 # Per bank write bursts | 52system.mem_ctrls.perBankRdBursts::9 250 # Per bank write bursts 53system.mem_ctrls.perBankRdBursts::10 100 # Per bank write bursts 54system.mem_ctrls.perBankRdBursts::11 44 # Per bank write bursts 55system.mem_ctrls.perBankRdBursts::12 107 # Per bank write bursts 56system.mem_ctrls.perBankRdBursts::13 46 # Per bank write bursts 57system.mem_ctrls.perBankRdBursts::14 157 # Per bank write bursts 58system.mem_ctrls.perBankRdBursts::15 13 # Per bank write bursts 59system.mem_ctrls.perBankWrBursts::0 32 # Per bank write bursts |
| 60system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts | 60system.mem_ctrls.perBankWrBursts::1 0 # Per bank write bursts 61system.mem_ctrls.perBankWrBursts::2 0 # Per bank write bursts 62system.mem_ctrls.perBankWrBursts::3 0 # Per bank write bursts 63system.mem_ctrls.perBankWrBursts::4 7 # Per bank write bursts 64system.mem_ctrls.perBankWrBursts::5 3 # Per bank write bursts 65system.mem_ctrls.perBankWrBursts::6 13 # Per bank write bursts |
| 66system.mem_ctrls.perBankWrBursts::7 74 # Per bank write bursts | 66system.mem_ctrls.perBankWrBursts::7 75 # Per bank write bursts |
| 67system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts | 67system.mem_ctrls.perBankWrBursts::8 60 # Per bank write bursts |
| 68system.mem_ctrls.perBankWrBursts::9 247 # Per bank write bursts | 68system.mem_ctrls.perBankWrBursts::9 250 # Per bank write bursts |
| 69system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts | 69system.mem_ctrls.perBankWrBursts::10 100 # Per bank write bursts |
| 70system.mem_ctrls.perBankWrBursts::11 46 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::12 118 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::13 49 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::14 178 # Per bank write bursts | 70system.mem_ctrls.perBankWrBursts::11 45 # Per bank write bursts 71system.mem_ctrls.perBankWrBursts::12 110 # Per bank write bursts 72system.mem_ctrls.perBankWrBursts::13 48 # Per bank write bursts 73system.mem_ctrls.perBankWrBursts::14 177 # Per bank write bursts |
| 74system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts 75system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 76system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry | 74system.mem_ctrls.perBankWrBursts::15 14 # Per bank write bursts 75system.mem_ctrls.numRdRetry 0 # Number of times read queue was full causing retry 76system.mem_ctrls.numWrRetry 0 # Number of times write queue was full causing retry |
| 77system.mem_ctrls.totGap 100183 # Total gap between requests | 77system.mem_ctrls.totGap 106076 # Total gap between requests |
| 78system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 84system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2) 85system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 91system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2) | 78system.mem_ctrls.readPktSize::0 0 # Read request sizes (log2) 79system.mem_ctrls.readPktSize::1 0 # Read request sizes (log2) 80system.mem_ctrls.readPktSize::2 0 # Read request sizes (log2) 81system.mem_ctrls.readPktSize::3 0 # Read request sizes (log2) 82system.mem_ctrls.readPktSize::4 0 # Read request sizes (log2) 83system.mem_ctrls.readPktSize::5 0 # Read request sizes (log2) 84system.mem_ctrls.readPktSize::6 1472 # Read request sizes (log2) 85system.mem_ctrls.writePktSize::0 0 # Write request sizes (log2) 86system.mem_ctrls.writePktSize::1 0 # Write request sizes (log2) 87system.mem_ctrls.writePktSize::2 0 # Write request sizes (log2) 88system.mem_ctrls.writePktSize::3 0 # Write request sizes (log2) 89system.mem_ctrls.writePktSize::4 0 # Write request sizes (log2) 90system.mem_ctrls.writePktSize::5 0 # Write request sizes (log2) 91system.mem_ctrls.writePktSize::6 1468 # Write request sizes (log2) |
| 92system.mem_ctrls.rdQLenPdf::0 918 # What read queue length does an incoming req see | 92system.mem_ctrls.rdQLenPdf::0 920 # What read queue length does an incoming req see |
| 93system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 131system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see | 93system.mem_ctrls.rdQLenPdf::1 0 # What read queue length does an incoming req see 94system.mem_ctrls.rdQLenPdf::2 0 # What read queue length does an incoming req see 95system.mem_ctrls.rdQLenPdf::3 0 # What read queue length does an incoming req see 96system.mem_ctrls.rdQLenPdf::4 0 # What read queue length does an incoming req see 97system.mem_ctrls.rdQLenPdf::5 0 # What read queue length does an incoming req see 98system.mem_ctrls.rdQLenPdf::6 0 # What read queue length does an incoming req see 99system.mem_ctrls.rdQLenPdf::7 0 # What read queue length does an incoming req see 100system.mem_ctrls.rdQLenPdf::8 0 # What read queue length does an incoming req see --- 30 unchanged lines hidden (view full) --- 131system.mem_ctrls.wrQLenPdf::7 1 # What write queue length does an incoming req see 132system.mem_ctrls.wrQLenPdf::8 1 # What write queue length does an incoming req see 133system.mem_ctrls.wrQLenPdf::9 1 # What write queue length does an incoming req see 134system.mem_ctrls.wrQLenPdf::10 1 # What write queue length does an incoming req see 135system.mem_ctrls.wrQLenPdf::11 1 # What write queue length does an incoming req see 136system.mem_ctrls.wrQLenPdf::12 1 # What write queue length does an incoming req see 137system.mem_ctrls.wrQLenPdf::13 1 # What write queue length does an incoming req see 138system.mem_ctrls.wrQLenPdf::14 1 # What write queue length does an incoming req see |
| 139system.mem_ctrls.wrQLenPdf::15 5 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::16 8 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::17 50 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::18 60 # What write queue length does an incoming req see | 139system.mem_ctrls.wrQLenPdf::15 8 # What write queue length does an incoming req see 140system.mem_ctrls.wrQLenPdf::16 11 # What write queue length does an incoming req see 141system.mem_ctrls.wrQLenPdf::17 51 # What write queue length does an incoming req see 142system.mem_ctrls.wrQLenPdf::18 61 # What write queue length does an incoming req see |
| 143system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see | 143system.mem_ctrls.wrQLenPdf::19 60 # What write queue length does an incoming req see |
| 144system.mem_ctrls.wrQLenPdf::20 67 # What write queue length does an incoming req see | 144system.mem_ctrls.wrQLenPdf::20 61 # What write queue length does an incoming req see |
| 145system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see | 145system.mem_ctrls.wrQLenPdf::21 61 # What write queue length does an incoming req see |
| 146system.mem_ctrls.wrQLenPdf::22 59 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::23 58 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::24 58 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::25 58 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::26 58 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::27 58 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::28 58 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::29 58 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::30 58 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::31 58 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::32 58 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::33 1 # What write queue length does an incoming req see | 146system.mem_ctrls.wrQLenPdf::22 58 # What write queue length does an incoming req see 147system.mem_ctrls.wrQLenPdf::23 59 # What write queue length does an incoming req see 148system.mem_ctrls.wrQLenPdf::24 57 # What write queue length does an incoming req see 149system.mem_ctrls.wrQLenPdf::25 57 # What write queue length does an incoming req see 150system.mem_ctrls.wrQLenPdf::26 57 # What write queue length does an incoming req see 151system.mem_ctrls.wrQLenPdf::27 57 # What write queue length does an incoming req see 152system.mem_ctrls.wrQLenPdf::28 57 # What write queue length does an incoming req see 153system.mem_ctrls.wrQLenPdf::29 57 # What write queue length does an incoming req see 154system.mem_ctrls.wrQLenPdf::30 57 # What write queue length does an incoming req see 155system.mem_ctrls.wrQLenPdf::31 57 # What write queue length does an incoming req see 156system.mem_ctrls.wrQLenPdf::32 57 # What write queue length does an incoming req see 157system.mem_ctrls.wrQLenPdf::33 0 # What write queue length does an incoming req see |
| 158system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 180system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 187system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see | 158system.mem_ctrls.wrQLenPdf::34 0 # What write queue length does an incoming req see 159system.mem_ctrls.wrQLenPdf::35 0 # What write queue length does an incoming req see 160system.mem_ctrls.wrQLenPdf::36 0 # What write queue length does an incoming req see 161system.mem_ctrls.wrQLenPdf::37 0 # What write queue length does an incoming req see 162system.mem_ctrls.wrQLenPdf::38 0 # What write queue length does an incoming req see 163system.mem_ctrls.wrQLenPdf::39 0 # What write queue length does an incoming req see 164system.mem_ctrls.wrQLenPdf::40 0 # What write queue length does an incoming req see 165system.mem_ctrls.wrQLenPdf::41 0 # What write queue length does an incoming req see --- 14 unchanged lines hidden (view full) --- 180system.mem_ctrls.wrQLenPdf::56 0 # What write queue length does an incoming req see 181system.mem_ctrls.wrQLenPdf::57 0 # What write queue length does an incoming req see 182system.mem_ctrls.wrQLenPdf::58 0 # What write queue length does an incoming req see 183system.mem_ctrls.wrQLenPdf::59 0 # What write queue length does an incoming req see 184system.mem_ctrls.wrQLenPdf::60 0 # What write queue length does an incoming req see 185system.mem_ctrls.wrQLenPdf::61 0 # What write queue length does an incoming req see 186system.mem_ctrls.wrQLenPdf::62 0 # What write queue length does an incoming req see 187system.mem_ctrls.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 188system.mem_ctrls.bytesPerActivate::samples 336 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::mean 348.571429 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::gmean 224.382213 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::stdev 328.447975 # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::0-127 77 22.92% 22.92% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::128-255 103 30.65% 53.57% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::256-383 48 14.29% 67.86% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::384-511 26 7.74% 75.60% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::512-639 11 3.27% 78.87% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::640-767 8 2.38% 81.25% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::768-895 13 3.87% 85.12% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::896-1023 7 2.08% 87.20% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::1024-1151 43 12.80% 100.00% # Bytes accessed per row activation 201system.mem_ctrls.bytesPerActivate::total 336 # Bytes accessed per row activation 202system.mem_ctrls.rdPerTurnAround::samples 58 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::mean 15.706897 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::gmean 15.549891 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::stdev 2.720995 # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::12-13 5 8.62% 8.62% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::14-15 26 44.83% 53.45% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::16-17 25 43.10% 96.55% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::18-19 1 1.72% 98.28% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::34-35 1 1.72% 100.00% # Reads before turning the bus around for writes 211system.mem_ctrls.rdPerTurnAround::total 58 # Reads before turning the bus around for writes 212system.mem_ctrls.wrPerTurnAround::samples 58 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::mean 16.258621 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::gmean 16.240724 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::stdev 0.806995 # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::16 52 89.66% 89.66% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::18 4 6.90% 96.55% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::19 1 1.72% 98.28% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::20 1 1.72% 100.00% # Writes before turning the bus around for reads 220system.mem_ctrls.wrPerTurnAround::total 58 # Writes before turning the bus around for reads 221system.mem_ctrls.totQLat 12638 # Total ticks spent queuing 222system.mem_ctrls.totMemAccLat 30080 # Total ticks spent from burst creation until serviced by the DRAM 223system.mem_ctrls.totBusLat 4590 # Total ticks spent in databus transfers 224system.mem_ctrls.avgQLat 13.77 # Average queueing delay per DRAM burst | 188system.mem_ctrls.bytesPerActivate::samples 352 # Bytes accessed per row activation 189system.mem_ctrls.bytesPerActivate::mean 334.181818 # Bytes accessed per row activation 190system.mem_ctrls.bytesPerActivate::gmean 220.342342 # Bytes accessed per row activation 191system.mem_ctrls.bytesPerActivate::stdev 312.466834 # Bytes accessed per row activation 192system.mem_ctrls.bytesPerActivate::0-127 73 20.74% 20.74% # Bytes accessed per row activation 193system.mem_ctrls.bytesPerActivate::128-255 116 32.95% 53.69% # Bytes accessed per row activation 194system.mem_ctrls.bytesPerActivate::256-383 49 13.92% 67.61% # Bytes accessed per row activation 195system.mem_ctrls.bytesPerActivate::384-511 31 8.81% 76.42% # Bytes accessed per row activation 196system.mem_ctrls.bytesPerActivate::512-639 18 5.11% 81.53% # Bytes accessed per row activation 197system.mem_ctrls.bytesPerActivate::640-767 13 3.69% 85.23% # Bytes accessed per row activation 198system.mem_ctrls.bytesPerActivate::768-895 9 2.56% 87.78% # Bytes accessed per row activation 199system.mem_ctrls.bytesPerActivate::896-1023 3 0.85% 88.64% # Bytes accessed per row activation 200system.mem_ctrls.bytesPerActivate::1024-1151 40 11.36% 100.00% # Bytes accessed per row activation 201system.mem_ctrls.bytesPerActivate::total 352 # Bytes accessed per row activation 202system.mem_ctrls.rdPerTurnAround::samples 57 # Reads before turning the bus around for writes 203system.mem_ctrls.rdPerTurnAround::mean 16 # Reads before turning the bus around for writes 204system.mem_ctrls.rdPerTurnAround::gmean 15.842454 # Reads before turning the bus around for writes 205system.mem_ctrls.rdPerTurnAround::stdev 2.738613 # Reads before turning the bus around for writes 206system.mem_ctrls.rdPerTurnAround::12-13 2 3.51% 3.51% # Reads before turning the bus around for writes 207system.mem_ctrls.rdPerTurnAround::14-15 25 43.86% 47.37% # Reads before turning the bus around for writes 208system.mem_ctrls.rdPerTurnAround::16-17 25 43.86% 91.23% # Reads before turning the bus around for writes 209system.mem_ctrls.rdPerTurnAround::18-19 4 7.02% 98.25% # Reads before turning the bus around for writes 210system.mem_ctrls.rdPerTurnAround::34-35 1 1.75% 100.00% # Reads before turning the bus around for writes 211system.mem_ctrls.rdPerTurnAround::total 57 # Reads before turning the bus around for writes 212system.mem_ctrls.wrPerTurnAround::samples 57 # Writes before turning the bus around for reads 213system.mem_ctrls.wrPerTurnAround::mean 16.385965 # Writes before turning the bus around for reads 214system.mem_ctrls.wrPerTurnAround::gmean 16.360622 # Writes before turning the bus around for reads 215system.mem_ctrls.wrPerTurnAround::stdev 0.959062 # Writes before turning the bus around for reads 216system.mem_ctrls.wrPerTurnAround::16 48 84.21% 84.21% # Writes before turning the bus around for reads 217system.mem_ctrls.wrPerTurnAround::17 1 1.75% 85.96% # Writes before turning the bus around for reads 218system.mem_ctrls.wrPerTurnAround::18 4 7.02% 92.98% # Writes before turning the bus around for reads 219system.mem_ctrls.wrPerTurnAround::19 3 5.26% 98.25% # Writes before turning the bus around for reads 220system.mem_ctrls.wrPerTurnAround::20 1 1.75% 100.00% # Writes before turning the bus around for reads 221system.mem_ctrls.wrPerTurnAround::total 57 # Writes before turning the bus around for reads 222system.mem_ctrls.totQLat 18473 # Total ticks spent queuing 223system.mem_ctrls.totMemAccLat 35953 # Total ticks spent from burst creation until serviced by the DRAM 224system.mem_ctrls.totBusLat 4600 # Total ticks spent in databus transfers 225system.mem_ctrls.avgQLat 20.08 # Average queueing delay per DRAM burst |
| 225system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst | 226system.mem_ctrls.avgBusLat 5.00 # Average bus latency per DRAM burst |
| 226system.mem_ctrls.avgMemAccLat 32.77 # Average memory access latency per DRAM burst 227system.mem_ctrls.avgRdBW 586.16 # Average DRAM read bandwidth in MiByte/s 228system.mem_ctrls.avgWrBW 602.12 # Average achieved write bandwidth in MiByte/s 229system.mem_ctrls.avgRdBWSys 939.90 # Average system read bandwidth in MiByte/s 230system.mem_ctrls.avgWrBWSys 937.35 # Average system write bandwidth in MiByte/s | 227system.mem_ctrls.avgMemAccLat 39.08 # Average memory access latency per DRAM burst 228system.mem_ctrls.avgRdBW 554.82 # Average DRAM read bandwidth in MiByte/s 229system.mem_ctrls.avgWrBW 563.26 # Average achieved write bandwidth in MiByte/s 230system.mem_ctrls.avgRdBWSys 887.71 # Average system read bandwidth in MiByte/s 231system.mem_ctrls.avgWrBWSys 885.30 # Average system write bandwidth in MiByte/s |
| 231system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 232system.mem_ctrls.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 232system.mem_ctrls.busUtil 9.28 # Data bus utilization in percentage 233system.mem_ctrls.busUtilRead 4.58 # Data bus utilization in percentage for reads 234system.mem_ctrls.busUtilWrite 4.70 # Data bus utilization in percentage for writes | 233system.mem_ctrls.busUtil 8.73 # Data bus utilization in percentage 234system.mem_ctrls.busUtilRead 4.33 # Data bus utilization in percentage for reads 235system.mem_ctrls.busUtilWrite 4.40 # Data bus utilization in percentage for writes |
| 235system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing | 236system.mem_ctrls.avgRdQLen 1.00 # Average read queue length when enqueuing |
| 236system.mem_ctrls.avgWrQLen 25.54 # Average write queue length when enqueuing 237system.mem_ctrls.readRowHits 642 # Number of row buffer hits during reads 238system.mem_ctrls.writeRowHits 873 # Number of row buffer hits during writes 239system.mem_ctrls.readRowHitRate 69.93 # Row buffer hit rate for reads 240system.mem_ctrls.writeRowHitRate 90.37 # Row buffer hit rate for writes 241system.mem_ctrls.avgGap 34.08 # Average gap between requests 242system.mem_ctrls.pageHitRate 80.41 # Row buffer hit rate, read and write combined 243system.mem_ctrls_0.actEnergy 491400 # Energy for activate commands per rank (pJ) 244system.mem_ctrls_0.preEnergy 273000 # Energy for precharge commands per rank (pJ) 245system.mem_ctrls_0.readEnergy 1547520 # Energy for read commands per rank (pJ) 246system.mem_ctrls_0.writeEnergy 1099008 # Energy for write commands per rank (pJ) 247system.mem_ctrls_0.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 248system.mem_ctrls_0.actBackEnergy 55680336 # Energy for active background per rank (pJ) 249system.mem_ctrls_0.preBackEnergy 7372800 # Energy for precharge background per rank (pJ) 250system.mem_ctrls_0.totalEnergy 72566784 # Total energy per rank (pJ) 251system.mem_ctrls_0.averagePower 774.524869 # Core power per rank (mW) 252system.mem_ctrls_0.memoryStateTime::IDLE 11950 # Time in different power states 253system.mem_ctrls_0.memoryStateTime::REF 3120 # Time in different power states 254system.mem_ctrls_0.memoryStateTime::PRE_PDN 0 # Time in different power states 255system.mem_ctrls_0.memoryStateTime::ACT 78690 # Time in different power states 256system.mem_ctrls_0.memoryStateTime::ACT_PDN 0 # Time in different power states 257system.mem_ctrls_1.actEnergy 1882440 # Energy for activate commands per rank (pJ) 258system.mem_ctrls_1.preEnergy 1045800 # Energy for precharge commands per rank (pJ) 259system.mem_ctrls_1.readEnergy 9247680 # Energy for read commands per rank (pJ) 260system.mem_ctrls_1.writeEnergy 7993728 # Energy for write commands per rank (pJ) 261system.mem_ctrls_1.refreshEnergy 6102720 # Energy for refresh commands per rank (pJ) 262system.mem_ctrls_1.actBackEnergy 63740592 # Energy for active background per rank (pJ) 263system.mem_ctrls_1.preBackEnergy 302400 # Energy for precharge background per rank (pJ) 264system.mem_ctrls_1.totalEnergy 90315360 # Total energy per rank (pJ) 265system.mem_ctrls_1.averagePower 963.960210 # Core power per rank (mW) 266system.mem_ctrls_1.memoryStateTime::IDLE 182 # Time in different power states 267system.mem_ctrls_1.memoryStateTime::REF 3120 # Time in different power states 268system.mem_ctrls_1.memoryStateTime::PRE_PDN 0 # Time in different power states 269system.mem_ctrls_1.memoryStateTime::ACT 90404 # Time in different power states 270system.mem_ctrls_1.memoryStateTime::ACT_PDN 0 # Time in different power states 271system.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 237system.mem_ctrls.avgWrQLen 25.41 # Average write queue length when enqueuing 238system.mem_ctrls.readRowHits 632 # Number of row buffer hits during reads 239system.mem_ctrls.writeRowHits 865 # Number of row buffer hits during writes 240system.mem_ctrls.readRowHitRate 68.70 # Row buffer hit rate for reads 241system.mem_ctrls.writeRowHitRate 90.29 # Row buffer hit rate for writes 242system.mem_ctrls.avgGap 36.08 # Average gap between requests 243system.mem_ctrls.pageHitRate 79.71 # Row buffer hit rate, read and write combined 244system.mem_ctrls_0.actEnergy 542640 # Energy for activate commands per rank (pJ) 245system.mem_ctrls_0.preEnergy 289800 # Energy for precharge commands per rank (pJ) 246system.mem_ctrls_0.readEnergy 1565088 # Energy for read commands per rank (pJ) 247system.mem_ctrls_0.writeEnergy 1085760 # Energy for write commands per rank (pJ) 248system.mem_ctrls_0.refreshEnergy 8604960.000000 # Energy for refresh commands per rank (pJ) 249system.mem_ctrls_0.actBackEnergy 15123696 # Energy for active background per rank (pJ) 250system.mem_ctrls_0.preBackEnergy 297600 # Energy for precharge background per rank (pJ) 251system.mem_ctrls_0.actPowerDownEnergy 24352224 # Energy for active power-down per rank (pJ) 252system.mem_ctrls_0.prePowerDownEnergy 7106304 # Energy for precharge power-down per rank (pJ) 253system.mem_ctrls_0.selfRefreshEnergy 647736.000000 # Energy for self refresh per rank (pJ) 254system.mem_ctrls_0.totalEnergy 59655384 # Total energy per rank (pJ) 255system.mem_ctrls_0.averagePower 562.123760 # Core power per rank (mW) 256system.mem_ctrls_0.totalIdleTime 71087 # Total Idle time Per DRAM Rank 257system.mem_ctrls_0.memoryStateTime::IDLE 340 # Time in different power states 258system.mem_ctrls_0.memoryStateTime::REF 3646 # Time in different power states 259system.mem_ctrls_0.memoryStateTime::SREF 185 # Time in different power states 260system.mem_ctrls_0.memoryStateTime::PRE_PDN 18506 # Time in different power states 261system.mem_ctrls_0.memoryStateTime::ACT 30044 # Time in different power states 262system.mem_ctrls_0.memoryStateTime::ACT_PDN 53404 # Time in different power states 263system.mem_ctrls_1.actEnergy 2006340 # Energy for activate commands per rank (pJ) 264system.mem_ctrls_1.preEnergy 1070328 # Energy for precharge commands per rank (pJ) 265system.mem_ctrls_1.readEnergy 8944992 # Energy for read commands per rank (pJ) 266system.mem_ctrls_1.writeEnergy 6715008 # Energy for write commands per rank (pJ) 267system.mem_ctrls_1.refreshEnergy 7990320.000000 # Energy for refresh commands per rank (pJ) 268system.mem_ctrls_1.actBackEnergy 16837800 # Energy for active background per rank (pJ) 269system.mem_ctrls_1.preBackEnergy 207360 # Energy for precharge background per rank (pJ) 270system.mem_ctrls_1.actPowerDownEnergy 31179912 # Energy for active power-down per rank (pJ) 271system.mem_ctrls_1.prePowerDownEnergy 108672 # Energy for precharge power-down per rank (pJ) 272system.mem_ctrls_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 273system.mem_ctrls_1.totalEnergy 75060732 # Total energy per rank (pJ) 274system.mem_ctrls_1.averagePower 707.286049 # Core power per rank (mW) 275system.mem_ctrls_1.totalIdleTime 68578 # Total Idle time Per DRAM Rank 276system.mem_ctrls_1.memoryStateTime::IDLE 148 # Time in different power states 277system.mem_ctrls_1.memoryStateTime::REF 3380 # Time in different power states 278system.mem_ctrls_1.memoryStateTime::SREF 0 # Time in different power states 279system.mem_ctrls_1.memoryStateTime::PRE_PDN 283 # Time in different power states 280system.mem_ctrls_1.memoryStateTime::ACT 33937 # Time in different power states 281system.mem_ctrls_1.memoryStateTime::ACT_PDN 68377 # Time in different power states 282system.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 272system.cpu.clk_domain.clock 1 # Clock period in ticks 273system.cpu.dtb.read_hits 0 # DTB read hits 274system.cpu.dtb.read_misses 0 # DTB read misses 275system.cpu.dtb.read_accesses 0 # DTB read accesses 276system.cpu.dtb.write_hits 0 # DTB write hits 277system.cpu.dtb.write_misses 0 # DTB write misses 278system.cpu.dtb.write_accesses 0 # DTB write accesses 279system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 284system.cpu.itb.read_accesses 0 # DTB read accesses 285system.cpu.itb.write_hits 0 # DTB write hits 286system.cpu.itb.write_misses 0 # DTB write misses 287system.cpu.itb.write_accesses 0 # DTB write accesses 288system.cpu.itb.hits 0 # DTB hits 289system.cpu.itb.misses 0 # DTB misses 290system.cpu.itb.accesses 0 # DTB accesses 291system.cpu.workload.num_syscalls 7 # Number of system calls | 283system.cpu.clk_domain.clock 1 # Clock period in ticks 284system.cpu.dtb.read_hits 0 # DTB read hits 285system.cpu.dtb.read_misses 0 # DTB read misses 286system.cpu.dtb.read_accesses 0 # DTB read accesses 287system.cpu.dtb.write_hits 0 # DTB write hits 288system.cpu.dtb.write_misses 0 # DTB write misses 289system.cpu.dtb.write_accesses 0 # DTB write accesses 290system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 295system.cpu.itb.read_accesses 0 # DTB read accesses 296system.cpu.itb.write_hits 0 # DTB write hits 297system.cpu.itb.write_misses 0 # DTB write misses 298system.cpu.itb.write_accesses 0 # DTB write accesses 299system.cpu.itb.hits 0 # DTB hits 300system.cpu.itb.misses 0 # DTB misses 301system.cpu.itb.accesses 0 # DTB accesses 302system.cpu.workload.num_syscalls 7 # Number of system calls |
| 292system.cpu.pwrStateResidencyTicks::ON 100232 # Cumulative time (in ticks) in various power states 293system.cpu.numCycles 100232 # number of cpu cycles simulated | 303system.cpu.pwrStateResidencyTicks::ON 106125 # Cumulative time (in ticks) in various power states 304system.cpu.numCycles 106125 # number of cpu cycles simulated |
| 294system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 295system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 296system.cpu.committedInsts 5641 # Number of instructions committed 297system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 298system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 299system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 300system.cpu.num_func_calls 191 # number of times a function call or return occured 301system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 302system.cpu.num_int_insts 4957 # number of integer instructions 303system.cpu.num_fp_insts 2 # number of float instructions 304system.cpu.num_int_register_reads 7072 # number of times the integer registers were read 305system.cpu.num_int_register_writes 3291 # number of times the integer registers were written 306system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 307system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 308system.cpu.num_mem_refs 2037 # number of memory refs 309system.cpu.num_load_insts 1135 # Number of load instructions 310system.cpu.num_store_insts 902 # Number of store instructions 311system.cpu.num_idle_cycles 0 # Number of idle cycles | 305system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 306system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 307system.cpu.committedInsts 5641 # Number of instructions committed 308system.cpu.committedOps 5641 # Number of ops (including micro ops) committed 309system.cpu.num_int_alu_accesses 4957 # Number of integer alu accesses 310system.cpu.num_fp_alu_accesses 2 # Number of float alu accesses 311system.cpu.num_func_calls 191 # number of times a function call or return occured 312system.cpu.num_conditional_control_insts 651 # number of instructions that are conditional controls 313system.cpu.num_int_insts 4957 # number of integer instructions 314system.cpu.num_fp_insts 2 # number of float instructions 315system.cpu.num_int_register_reads 7072 # number of times the integer registers were read 316system.cpu.num_int_register_writes 3291 # number of times the integer registers were written 317system.cpu.num_fp_register_reads 3 # number of times the floating registers were read 318system.cpu.num_fp_register_writes 1 # number of times the floating registers were written 319system.cpu.num_mem_refs 2037 # number of memory refs 320system.cpu.num_load_insts 1135 # Number of load instructions 321system.cpu.num_store_insts 902 # Number of store instructions 322system.cpu.num_idle_cycles 0 # Number of idle cycles |
| 312system.cpu.num_busy_cycles 100232 # Number of busy cycles | 323system.cpu.num_busy_cycles 106125 # Number of busy cycles |
| 313system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 314system.cpu.idle_fraction 0 # Percentage of idle cycles 315system.cpu.Branches 886 # Number of branches fetched 316system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 317system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 318system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 319system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 320system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 344system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 345system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 346system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 347system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 348system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 349system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 350system.cpu.op_class::total 5642 # Class of executed instruction 351system.ruby.clk_domain.clock 1 # Clock period in ticks | 324system.cpu.not_idle_fraction 1 # Percentage of non-idle cycles 325system.cpu.idle_fraction 0 # Percentage of idle cycles 326system.cpu.Branches 886 # Number of branches fetched 327system.cpu.op_class::No_OpClass 641 11.36% 11.36% # Class of executed instruction 328system.cpu.op_class::IntAlu 2960 52.46% 63.82% # Class of executed instruction 329system.cpu.op_class::IntMult 2 0.04% 63.86% # Class of executed instruction 330system.cpu.op_class::IntDiv 0 0.00% 63.86% # Class of executed instruction 331system.cpu.op_class::FloatAdd 2 0.04% 63.90% # Class of executed instruction --- 23 unchanged lines hidden (view full) --- 355system.cpu.op_class::SimdFloatMultAcc 0 0.00% 63.90% # Class of executed instruction 356system.cpu.op_class::SimdFloatSqrt 0 0.00% 63.90% # Class of executed instruction 357system.cpu.op_class::MemRead 1135 20.12% 84.01% # Class of executed instruction 358system.cpu.op_class::MemWrite 902 15.99% 100.00% # Class of executed instruction 359system.cpu.op_class::IprAccess 0 0.00% 100.00% # Class of executed instruction 360system.cpu.op_class::InstPrefetch 0 0.00% 100.00% # Class of executed instruction 361system.cpu.op_class::total 5642 # Class of executed instruction 362system.ruby.clk_domain.clock 1 # Clock period in ticks |
| 352system.ruby.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 363system.ruby.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 353system.ruby.delayHist::bucket_size 1 # delay histogram for all message 354system.ruby.delayHist::max_bucket 9 # delay histogram for all message 355system.ruby.delayHist::samples 2940 # delay histogram for all message 356system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 357system.ruby.delayHist::total 2940 # delay histogram for all message 358system.ruby.outstanding_req_hist_seqr::bucket_size 1 359system.ruby.outstanding_req_hist_seqr::max_bucket 9 360system.ruby.outstanding_req_hist_seqr::samples 7679 361system.ruby.outstanding_req_hist_seqr::mean 1 362system.ruby.outstanding_req_hist_seqr::gmean 1 363system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 364system.ruby.outstanding_req_hist_seqr::total 7679 365system.ruby.latency_hist_seqr::bucket_size 64 366system.ruby.latency_hist_seqr::max_bucket 639 367system.ruby.latency_hist_seqr::samples 7678 | 364system.ruby.delayHist::bucket_size 1 # delay histogram for all message 365system.ruby.delayHist::max_bucket 9 # delay histogram for all message 366system.ruby.delayHist::samples 2940 # delay histogram for all message 367system.ruby.delayHist | 2940 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for all message 368system.ruby.delayHist::total 2940 # delay histogram for all message 369system.ruby.outstanding_req_hist_seqr::bucket_size 1 370system.ruby.outstanding_req_hist_seqr::max_bucket 9 371system.ruby.outstanding_req_hist_seqr::samples 7679 372system.ruby.outstanding_req_hist_seqr::mean 1 373system.ruby.outstanding_req_hist_seqr::gmean 1 374system.ruby.outstanding_req_hist_seqr | 0 0.00% 0.00% | 7679 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 375system.ruby.outstanding_req_hist_seqr::total 7679 376system.ruby.latency_hist_seqr::bucket_size 64 377system.ruby.latency_hist_seqr::max_bucket 639 378system.ruby.latency_hist_seqr::samples 7678 |
| 368system.ruby.latency_hist_seqr::mean 12.054441 369system.ruby.latency_hist_seqr::gmean 2.136034 370system.ruby.latency_hist_seqr::stdev 27.599754 371system.ruby.latency_hist_seqr | 7372 96.01% 96.01% | 253 3.30% 99.31% | 37 0.48% 99.79% | 4 0.05% 99.84% | 6 0.08% 99.92% | 5 0.07% 99.99% | 0 0.00% 99.99% | 1 0.01% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 379system.ruby.latency_hist_seqr::mean 12.821959 380system.ruby.latency_hist_seqr::gmean 2.158431 381system.ruby.latency_hist_seqr::stdev 29.332675 382system.ruby.latency_hist_seqr | 6783 88.34% 88.34% | 834 10.86% 99.21% | 40 0.52% 99.73% | 8 0.10% 99.83% | 8 0.10% 99.93% | 5 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 372system.ruby.latency_hist_seqr::total 7678 373system.ruby.hit_latency_hist_seqr::bucket_size 1 374system.ruby.hit_latency_hist_seqr::max_bucket 9 375system.ruby.hit_latency_hist_seqr::samples 6206 376system.ruby.hit_latency_hist_seqr::mean 1 377system.ruby.hit_latency_hist_seqr::gmean 1 378system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 379system.ruby.hit_latency_hist_seqr::total 6206 380system.ruby.miss_latency_hist_seqr::bucket_size 64 381system.ruby.miss_latency_hist_seqr::max_bucket 639 382system.ruby.miss_latency_hist_seqr::samples 1472 | 383system.ruby.latency_hist_seqr::total 7678 384system.ruby.hit_latency_hist_seqr::bucket_size 1 385system.ruby.hit_latency_hist_seqr::max_bucket 9 386system.ruby.hit_latency_hist_seqr::samples 6206 387system.ruby.hit_latency_hist_seqr::mean 1 388system.ruby.hit_latency_hist_seqr::gmean 1 389system.ruby.hit_latency_hist_seqr | 0 0.00% 0.00% | 6206 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 390system.ruby.hit_latency_hist_seqr::total 6206 391system.ruby.miss_latency_hist_seqr::bucket_size 64 392system.ruby.miss_latency_hist_seqr::max_bucket 639 393system.ruby.miss_latency_hist_seqr::samples 1472 |
| 383system.ruby.miss_latency_hist_seqr::mean 58.660326 384system.ruby.miss_latency_hist_seqr::gmean 52.389786 385system.ruby.miss_latency_hist_seqr::stdev 35.865583 386system.ruby.miss_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 394system.ruby.miss_latency_hist_seqr::mean 62.663723 395system.ruby.miss_latency_hist_seqr::gmean 55.319189 396system.ruby.miss_latency_hist_seqr::stdev 37.614530 397system.ruby.miss_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 387system.ruby.miss_latency_hist_seqr::total 1472 388system.ruby.Directory.incomplete_times_seqr 1471 | 398system.ruby.miss_latency_hist_seqr::total 1472 399system.ruby.Directory.incomplete_times_seqr 1471 |
| 389system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 400system.ruby.dir_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 390system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits 391system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses 392system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses | 401system.ruby.l1_cntrl0.cacheMemory.demand_hits 6206 # Number of cache demand hits 402system.ruby.l1_cntrl0.cacheMemory.demand_misses 1472 # Number of cache demand misses 403system.ruby.l1_cntrl0.cacheMemory.demand_accesses 7678 # Number of cache demand accesses |
| 393system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states 394system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 404system.ruby.l1_cntrl0.sequencer.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 405system.ruby.l1_cntrl0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 395system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks | 406system.ruby.memctrl_clk_domain.clock 3 # Clock period in ticks |
| 396system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states 397system.ruby.network.routers0.percent_links_utilized 7.332987 | 407system.ruby.network.routers0.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 408system.ruby.network.routers0.percent_links_utilized 6.925795 |
| 398system.ruby.network.routers0.msg_count.Control::2 1472 399system.ruby.network.routers0.msg_count.Data::2 1468 400system.ruby.network.routers0.msg_count.Response_Data::4 1472 401system.ruby.network.routers0.msg_count.Writeback_Control::3 1468 402system.ruby.network.routers0.msg_bytes.Control::2 11776 403system.ruby.network.routers0.msg_bytes.Data::2 105696 404system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 405system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 | 409system.ruby.network.routers0.msg_count.Control::2 1472 410system.ruby.network.routers0.msg_count.Data::2 1468 411system.ruby.network.routers0.msg_count.Response_Data::4 1472 412system.ruby.network.routers0.msg_count.Writeback_Control::3 1468 413system.ruby.network.routers0.msg_bytes.Control::2 11776 414system.ruby.network.routers0.msg_bytes.Data::2 105696 415system.ruby.network.routers0.msg_bytes.Response_Data::4 105984 416system.ruby.network.routers0.msg_bytes.Writeback_Control::3 11744 |
| 406system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states 407system.ruby.network.routers1.percent_links_utilized 7.332987 | 417system.ruby.network.routers1.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 418system.ruby.network.routers1.percent_links_utilized 6.925795 |
| 408system.ruby.network.routers1.msg_count.Control::2 1472 409system.ruby.network.routers1.msg_count.Data::2 1468 410system.ruby.network.routers1.msg_count.Response_Data::4 1472 411system.ruby.network.routers1.msg_count.Writeback_Control::3 1468 412system.ruby.network.routers1.msg_bytes.Control::2 11776 413system.ruby.network.routers1.msg_bytes.Data::2 105696 414system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 415system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 | 419system.ruby.network.routers1.msg_count.Control::2 1472 420system.ruby.network.routers1.msg_count.Data::2 1468 421system.ruby.network.routers1.msg_count.Response_Data::4 1472 422system.ruby.network.routers1.msg_count.Writeback_Control::3 1468 423system.ruby.network.routers1.msg_bytes.Control::2 11776 424system.ruby.network.routers1.msg_bytes.Data::2 105696 425system.ruby.network.routers1.msg_bytes.Response_Data::4 105984 426system.ruby.network.routers1.msg_bytes.Writeback_Control::3 11744 |
| 416system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states 417system.ruby.network.routers2.percent_links_utilized 7.332987 | 427system.ruby.network.routers2.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 428system.ruby.network.routers2.percent_links_utilized 6.925795 |
| 418system.ruby.network.routers2.msg_count.Control::2 1472 419system.ruby.network.routers2.msg_count.Data::2 1468 420system.ruby.network.routers2.msg_count.Response_Data::4 1472 421system.ruby.network.routers2.msg_count.Writeback_Control::3 1468 422system.ruby.network.routers2.msg_bytes.Control::2 11776 423system.ruby.network.routers2.msg_bytes.Data::2 105696 424system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 425system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 | 429system.ruby.network.routers2.msg_count.Control::2 1472 430system.ruby.network.routers2.msg_count.Data::2 1468 431system.ruby.network.routers2.msg_count.Response_Data::4 1472 432system.ruby.network.routers2.msg_count.Writeback_Control::3 1468 433system.ruby.network.routers2.msg_bytes.Control::2 11776 434system.ruby.network.routers2.msg_bytes.Data::2 105696 435system.ruby.network.routers2.msg_bytes.Response_Data::4 105984 436system.ruby.network.routers2.msg_bytes.Writeback_Control::3 11744 |
| 426system.ruby.network.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states | 437system.ruby.network.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states |
| 427system.ruby.network.msg_count.Control 4416 428system.ruby.network.msg_count.Data 4404 429system.ruby.network.msg_count.Response_Data 4416 430system.ruby.network.msg_count.Writeback_Control 4404 431system.ruby.network.msg_byte.Control 35328 432system.ruby.network.msg_byte.Data 317088 433system.ruby.network.msg_byte.Response_Data 317952 434system.ruby.network.msg_byte.Writeback_Control 35232 | 438system.ruby.network.msg_count.Control 4416 439system.ruby.network.msg_count.Data 4404 440system.ruby.network.msg_count.Response_Data 4416 441system.ruby.network.msg_count.Writeback_Control 4404 442system.ruby.network.msg_byte.Control 35328 443system.ruby.network.msg_byte.Data 317088 444system.ruby.network.msg_byte.Response_Data 317952 445system.ruby.network.msg_byte.Writeback_Control 35232 |
| 435system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 100232 # Cumulative time (in ticks) in various power states 436system.ruby.network.routers0.throttle0.link_utilization 7.340969 | 446system.sys_port_proxy.pwrStateResidencyTicks::UNDEFINED 106125 # Cumulative time (in ticks) in various power states 447system.ruby.network.routers0.throttle0.link_utilization 6.933333 |
| 437system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 438system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 439system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984 440system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744 | 448system.ruby.network.routers0.throttle0.msg_count.Response_Data::4 1472 449system.ruby.network.routers0.throttle0.msg_count.Writeback_Control::3 1468 450system.ruby.network.routers0.throttle0.msg_bytes.Response_Data::4 105984 451system.ruby.network.routers0.throttle0.msg_bytes.Writeback_Control::3 11744 |
| 441system.ruby.network.routers0.throttle1.link_utilization 7.325006 | 452system.ruby.network.routers0.throttle1.link_utilization 6.918257 |
| 442system.ruby.network.routers0.throttle1.msg_count.Control::2 1472 443system.ruby.network.routers0.throttle1.msg_count.Data::2 1468 444system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776 445system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696 | 453system.ruby.network.routers0.throttle1.msg_count.Control::2 1472 454system.ruby.network.routers0.throttle1.msg_count.Data::2 1468 455system.ruby.network.routers0.throttle1.msg_bytes.Control::2 11776 456system.ruby.network.routers0.throttle1.msg_bytes.Data::2 105696 |
| 446system.ruby.network.routers1.throttle0.link_utilization 7.325006 | 457system.ruby.network.routers1.throttle0.link_utilization 6.918257 |
| 447system.ruby.network.routers1.throttle0.msg_count.Control::2 1472 448system.ruby.network.routers1.throttle0.msg_count.Data::2 1468 449system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776 450system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696 | 458system.ruby.network.routers1.throttle0.msg_count.Control::2 1472 459system.ruby.network.routers1.throttle0.msg_count.Data::2 1468 460system.ruby.network.routers1.throttle0.msg_bytes.Control::2 11776 461system.ruby.network.routers1.throttle0.msg_bytes.Data::2 105696 |
| 451system.ruby.network.routers1.throttle1.link_utilization 7.340969 | 462system.ruby.network.routers1.throttle1.link_utilization 6.933333 |
| 452system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472 453system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468 454system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984 455system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744 | 463system.ruby.network.routers1.throttle1.msg_count.Response_Data::4 1472 464system.ruby.network.routers1.throttle1.msg_count.Writeback_Control::3 1468 465system.ruby.network.routers1.throttle1.msg_bytes.Response_Data::4 105984 466system.ruby.network.routers1.throttle1.msg_bytes.Writeback_Control::3 11744 |
| 456system.ruby.network.routers2.throttle0.link_utilization 7.340969 | 467system.ruby.network.routers2.throttle0.link_utilization 6.933333 |
| 457system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472 458system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468 459system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984 460system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744 | 468system.ruby.network.routers2.throttle0.msg_count.Response_Data::4 1472 469system.ruby.network.routers2.throttle0.msg_count.Writeback_Control::3 1468 470system.ruby.network.routers2.throttle0.msg_bytes.Response_Data::4 105984 471system.ruby.network.routers2.throttle0.msg_bytes.Writeback_Control::3 11744 |
| 461system.ruby.network.routers2.throttle1.link_utilization 7.325006 | 472system.ruby.network.routers2.throttle1.link_utilization 6.918257 |
| 462system.ruby.network.routers2.throttle1.msg_count.Control::2 1472 463system.ruby.network.routers2.throttle1.msg_count.Data::2 1468 464system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776 465system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696 466system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 467system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 468system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1 469system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 470system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1 471system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 472system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 473system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2 474system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 475system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2 476system.ruby.LD.latency_hist_seqr::bucket_size 64 477system.ruby.LD.latency_hist_seqr::max_bucket 639 478system.ruby.LD.latency_hist_seqr::samples 1135 | 473system.ruby.network.routers2.throttle1.msg_count.Control::2 1472 474system.ruby.network.routers2.throttle1.msg_count.Data::2 1468 475system.ruby.network.routers2.throttle1.msg_bytes.Control::2 11776 476system.ruby.network.routers2.throttle1.msg_bytes.Data::2 105696 477system.ruby.delayVCHist.vnet_1::bucket_size 1 # delay histogram for vnet_1 478system.ruby.delayVCHist.vnet_1::max_bucket 9 # delay histogram for vnet_1 479system.ruby.delayVCHist.vnet_1::samples 1472 # delay histogram for vnet_1 480system.ruby.delayVCHist.vnet_1 | 1472 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_1 481system.ruby.delayVCHist.vnet_1::total 1472 # delay histogram for vnet_1 482system.ruby.delayVCHist.vnet_2::bucket_size 1 # delay histogram for vnet_2 483system.ruby.delayVCHist.vnet_2::max_bucket 9 # delay histogram for vnet_2 484system.ruby.delayVCHist.vnet_2::samples 1468 # delay histogram for vnet_2 485system.ruby.delayVCHist.vnet_2 | 1468 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% # delay histogram for vnet_2 486system.ruby.delayVCHist.vnet_2::total 1468 # delay histogram for vnet_2 487system.ruby.LD.latency_hist_seqr::bucket_size 64 488system.ruby.LD.latency_hist_seqr::max_bucket 639 489system.ruby.LD.latency_hist_seqr::samples 1135 |
| 479system.ruby.LD.latency_hist_seqr::mean 33.525991 480system.ruby.LD.latency_hist_seqr::gmean 10.018050 481system.ruby.LD.latency_hist_seqr::stdev 38.312060 482system.ruby.LD.latency_hist_seqr | 999 88.02% 88.02% | 116 10.22% 98.24% | 13 1.15% 99.38% | 0 0.00% 99.38% | 6 0.53% 99.91% | 1 0.09% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 490system.ruby.LD.latency_hist_seqr::mean 35.394714 491system.ruby.LD.latency_hist_seqr::gmean 10.319359 492system.ruby.LD.latency_hist_seqr::stdev 39.399406 493system.ruby.LD.latency_hist_seqr | 768 67.67% 67.67% | 344 30.31% 97.97% | 15 1.32% 99.30% | 4 0.35% 99.65% | 2 0.18% 99.82% | 2 0.18% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 483system.ruby.LD.latency_hist_seqr::total 1135 484system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 485system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 486system.ruby.LD.hit_latency_hist_seqr::samples 466 487system.ruby.LD.hit_latency_hist_seqr::mean 1 488system.ruby.LD.hit_latency_hist_seqr::gmean 1 489system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 490system.ruby.LD.hit_latency_hist_seqr::total 466 491system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 492system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 493system.ruby.LD.miss_latency_hist_seqr::samples 669 | 494system.ruby.LD.latency_hist_seqr::total 1135 495system.ruby.LD.hit_latency_hist_seqr::bucket_size 1 496system.ruby.LD.hit_latency_hist_seqr::max_bucket 9 497system.ruby.LD.hit_latency_hist_seqr::samples 466 498system.ruby.LD.hit_latency_hist_seqr::mean 1 499system.ruby.LD.hit_latency_hist_seqr::gmean 1 500system.ruby.LD.hit_latency_hist_seqr | 0 0.00% 0.00% | 466 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 501system.ruby.LD.hit_latency_hist_seqr::total 466 502system.ruby.LD.miss_latency_hist_seqr::bucket_size 64 503system.ruby.LD.miss_latency_hist_seqr::max_bucket 639 504system.ruby.LD.miss_latency_hist_seqr::samples 669 |
| 494system.ruby.LD.miss_latency_hist_seqr::mean 56.182362 495system.ruby.LD.miss_latency_hist_seqr::gmean 49.875907 496system.ruby.LD.miss_latency_hist_seqr::stdev 35.208867 497system.ruby.LD.miss_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 505system.ruby.LD.miss_latency_hist_seqr::mean 59.352765 506system.ruby.LD.miss_latency_hist_seqr::gmean 52.447495 507system.ruby.LD.miss_latency_hist_seqr::stdev 35.144031 508system.ruby.LD.miss_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 498system.ruby.LD.miss_latency_hist_seqr::total 669 | 509system.ruby.LD.miss_latency_hist_seqr::total 669 |
| 499system.ruby.ST.latency_hist_seqr::bucket_size 64 500system.ruby.ST.latency_hist_seqr::max_bucket 639 | 510system.ruby.ST.latency_hist_seqr::bucket_size 32 511system.ruby.ST.latency_hist_seqr::max_bucket 319 |
| 501system.ruby.ST.latency_hist_seqr::samples 901 | 512system.ruby.ST.latency_hist_seqr::samples 901 |
| 502system.ruby.ST.latency_hist_seqr::mean 13.069922 503system.ruby.ST.latency_hist_seqr::gmean 2.509564 504system.ruby.ST.latency_hist_seqr::stdev 28.093942 505system.ruby.ST.latency_hist_seqr | 870 96.56% 96.56% | 27 3.00% 99.56% | 3 0.33% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 0 0.00% 99.89% | 1 0.11% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 513system.ruby.ST.latency_hist_seqr::mean 13.442841 514system.ruby.ST.latency_hist_seqr::gmean 2.518866 515system.ruby.ST.latency_hist_seqr::stdev 27.757167 516system.ruby.ST.latency_hist_seqr | 684 75.92% 75.92% | 130 14.43% 90.34% | 81 8.99% 99.33% | 0 0.00% 99.33% | 1 0.11% 99.45% | 3 0.33% 99.78% | 0 0.00% 99.78% | 0 0.00% 99.78% | 1 0.11% 99.89% | 1 0.11% 100.00% |
| 506system.ruby.ST.latency_hist_seqr::total 901 507system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 508system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 509system.ruby.ST.hit_latency_hist_seqr::samples 684 510system.ruby.ST.hit_latency_hist_seqr::mean 1 511system.ruby.ST.hit_latency_hist_seqr::gmean 1 512system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 513system.ruby.ST.hit_latency_hist_seqr::total 684 | 517system.ruby.ST.latency_hist_seqr::total 901 518system.ruby.ST.hit_latency_hist_seqr::bucket_size 1 519system.ruby.ST.hit_latency_hist_seqr::max_bucket 9 520system.ruby.ST.hit_latency_hist_seqr::samples 684 521system.ruby.ST.hit_latency_hist_seqr::mean 1 522system.ruby.ST.hit_latency_hist_seqr::gmean 1 523system.ruby.ST.hit_latency_hist_seqr | 0 0.00% 0.00% | 684 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 524system.ruby.ST.hit_latency_hist_seqr::total 684 |
| 514system.ruby.ST.miss_latency_hist_seqr::bucket_size 64 515system.ruby.ST.miss_latency_hist_seqr::max_bucket 639 | 525system.ruby.ST.miss_latency_hist_seqr::bucket_size 32 526system.ruby.ST.miss_latency_hist_seqr::max_bucket 319 |
| 516system.ruby.ST.miss_latency_hist_seqr::samples 217 | 527system.ruby.ST.miss_latency_hist_seqr::samples 217 |
| 517system.ruby.ST.miss_latency_hist_seqr::mean 51.115207 518system.ruby.ST.miss_latency_hist_seqr::gmean 45.620625 519system.ruby.ST.miss_latency_hist_seqr::stdev 37.056021 520system.ruby.ST.miss_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 528system.ruby.ST.miss_latency_hist_seqr::mean 52.663594 529system.ruby.ST.miss_latency_hist_seqr::gmean 46.326875 530system.ruby.ST.miss_latency_hist_seqr::stdev 34.272225 531system.ruby.ST.miss_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% |
| 521system.ruby.ST.miss_latency_hist_seqr::total 217 522system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 523system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 524system.ruby.IFETCH.latency_hist_seqr::samples 5642 | 532system.ruby.ST.miss_latency_hist_seqr::total 217 533system.ruby.IFETCH.latency_hist_seqr::bucket_size 64 534system.ruby.IFETCH.latency_hist_seqr::max_bucket 639 535system.ruby.IFETCH.latency_hist_seqr::samples 5642 |
| 525system.ruby.IFETCH.latency_hist_seqr::mean 7.572847 526system.ruby.IFETCH.latency_hist_seqr::gmean 1.525495 527system.ruby.IFETCH.latency_hist_seqr::stdev 22.420339 528system.ruby.IFETCH.latency_hist_seqr | 5503 97.54% 97.54% | 110 1.95% 99.49% | 21 0.37% 99.86% | 4 0.07% 99.93% | 0 0.00% 99.93% | 4 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 536system.ruby.IFETCH.latency_hist_seqr::mean 8.181850 537system.ruby.IFETCH.latency_hist_seqr::gmean 1.537199 538system.ruby.IFETCH.latency_hist_seqr::stdev 24.735651 539system.ruby.IFETCH.latency_hist_seqr | 5201 92.18% 92.18% | 409 7.25% 99.43% | 21 0.37% 99.81% | 4 0.07% 99.88% | 4 0.07% 99.95% | 3 0.05% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 529system.ruby.IFETCH.latency_hist_seqr::total 5642 530system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 531system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 532system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056 533system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 534system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 535system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 536system.ruby.IFETCH.hit_latency_hist_seqr::total 5056 537system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 538system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 539system.ruby.IFETCH.miss_latency_hist_seqr::samples 586 | 540system.ruby.IFETCH.latency_hist_seqr::total 5642 541system.ruby.IFETCH.hit_latency_hist_seqr::bucket_size 1 542system.ruby.IFETCH.hit_latency_hist_seqr::max_bucket 9 543system.ruby.IFETCH.hit_latency_hist_seqr::samples 5056 544system.ruby.IFETCH.hit_latency_hist_seqr::mean 1 545system.ruby.IFETCH.hit_latency_hist_seqr::gmean 1 546system.ruby.IFETCH.hit_latency_hist_seqr | 0 0.00% 0.00% | 5056 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 547system.ruby.IFETCH.hit_latency_hist_seqr::total 5056 548system.ruby.IFETCH.miss_latency_hist_seqr::bucket_size 64 549system.ruby.IFETCH.miss_latency_hist_seqr::max_bucket 639 550system.ruby.IFETCH.miss_latency_hist_seqr::samples 586 |
| 540system.ruby.IFETCH.miss_latency_hist_seqr::mean 64.283276 541system.ruby.IFETCH.miss_latency_hist_seqr::gmean 58.328027 542system.ruby.IFETCH.miss_latency_hist_seqr::stdev 35.386051 543system.ruby.IFETCH.miss_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 551system.ruby.IFETCH.miss_latency_hist_seqr::mean 70.146758 552system.ruby.IFETCH.miss_latency_hist_seqr::gmean 62.782043 553system.ruby.IFETCH.miss_latency_hist_seqr::stdev 40.099052 554system.ruby.IFETCH.miss_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 544system.ruby.IFETCH.miss_latency_hist_seqr::total 586 545system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 546system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 547system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472 | 555system.ruby.IFETCH.miss_latency_hist_seqr::total 586 556system.ruby.Directory.miss_mach_latency_hist_seqr::bucket_size 64 557system.ruby.Directory.miss_mach_latency_hist_seqr::max_bucket 639 558system.ruby.Directory.miss_mach_latency_hist_seqr::samples 1472 |
| 548system.ruby.Directory.miss_mach_latency_hist_seqr::mean 58.660326 549system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 52.389786 550system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 35.865583 551system.ruby.Directory.miss_mach_latency_hist_seqr | 1166 79.21% 79.21% | 253 17.19% 96.40% | 37 2.51% 98.91% | 4 0.27% 99.18% | 6 0.41% 99.59% | 5 0.34% 99.93% | 0 0.00% 99.93% | 1 0.07% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 559system.ruby.Directory.miss_mach_latency_hist_seqr::mean 62.663723 560system.ruby.Directory.miss_mach_latency_hist_seqr::gmean 55.319189 561system.ruby.Directory.miss_mach_latency_hist_seqr::stdev 37.614530 562system.ruby.Directory.miss_mach_latency_hist_seqr | 577 39.20% 39.20% | 834 56.66% 95.86% | 40 2.72% 98.57% | 8 0.54% 99.12% | 8 0.54% 99.66% | 5 0.34% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 552system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472 553system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 554system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 555system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 556system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 557system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 558system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 559system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 --- 14 unchanged lines hidden (view full) --- 574system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 575system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 576system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 577system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 578system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 579system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 580system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 581system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669 | 563system.ruby.Directory.miss_mach_latency_hist_seqr::total 1472 564system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::bucket_size 1 565system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::max_bucket 9 566system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::samples 1 567system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::stdev nan 568system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request | 1 100.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% 569system.ruby.Directory.miss_latency_hist_seqr.issue_to_initial_request::total 1 570system.ruby.Directory.miss_latency_hist_seqr.initial_to_forward::bucket_size 1 --- 14 unchanged lines hidden (view full) --- 585system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::mean 75 586system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::gmean 75.000000 587system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::stdev nan 588system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 0 0.00% 0.00% | 1 100.00% 100.00% 589system.ruby.Directory.miss_latency_hist_seqr.first_response_to_completion::total 1 590system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 591system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 592system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::samples 669 |
| 582system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 56.182362 583system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 49.875907 584system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.208867 585system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 533 79.67% 79.67% | 116 17.34% 97.01% | 13 1.94% 98.95% | 0 0.00% 98.95% | 6 0.90% 99.85% | 1 0.15% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 593system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::mean 59.352765 594system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::gmean 52.447495 595system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::stdev 35.144031 596system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr | 302 45.14% 45.14% | 344 51.42% 96.56% | 15 2.24% 98.80% | 4 0.60% 99.40% | 2 0.30% 99.70% | 2 0.30% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 586system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669 | 597system.ruby.LD.Directory.miss_type_mach_latency_hist_seqr::total 669 |
| 587system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 588system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 | 598system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::bucket_size 32 599system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::max_bucket 319 |
| 589system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 | 600system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::samples 217 |
| 590system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 51.115207 591system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 45.620625 592system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 37.056021 593system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 186 85.71% 85.71% | 27 12.44% 98.16% | 3 1.38% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 0 0.00% 99.54% | 1 0.46% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 601system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::mean 52.663594 602system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::gmean 46.326875 603system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::stdev 34.272225 604system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr | 0 0.00% 0.00% | 130 59.91% 59.91% | 81 37.33% 97.24% | 0 0.00% 97.24% | 1 0.46% 97.70% | 3 1.38% 99.08% | 0 0.00% 99.08% | 0 0.00% 99.08% | 1 0.46% 99.54% | 1 0.46% 100.00% |
| 594system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 595system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 596system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 597system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 | 605system.ruby.ST.Directory.miss_type_mach_latency_hist_seqr::total 217 606system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::bucket_size 64 607system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::max_bucket 639 608system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::samples 586 |
| 598system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 64.283276 599system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 58.328027 600system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 35.386051 601system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 447 76.28% 76.28% | 110 18.77% 95.05% | 21 3.58% 98.63% | 4 0.68% 99.32% | 0 0.00% 99.32% | 4 0.68% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 609system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::mean 70.146758 610system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::gmean 62.782043 611system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::stdev 40.099052 612system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr | 145 24.74% 24.74% | 409 69.80% 94.54% | 21 3.58% 98.12% | 4 0.68% 98.81% | 4 0.68% 99.49% | 3 0.51% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% | 0 0.00% 100.00% |
| 602system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 603system.ruby.Directory_Controller.GETX 1472 0.00% 0.00% 604system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00% 605system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00% 606system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00% 607system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00% 608system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00% 609system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00% --- 19 unchanged lines hidden --- | 613system.ruby.IFETCH.Directory.miss_type_mach_latency_hist_seqr::total 586 614system.ruby.Directory_Controller.GETX 1472 0.00% 0.00% 615system.ruby.Directory_Controller.PUTX 1468 0.00% 0.00% 616system.ruby.Directory_Controller.Memory_Data 1472 0.00% 0.00% 617system.ruby.Directory_Controller.Memory_Ack 1468 0.00% 0.00% 618system.ruby.Directory_Controller.I.GETX 1472 0.00% 0.00% 619system.ruby.Directory_Controller.M.PUTX 1468 0.00% 0.00% 620system.ruby.Directory_Controller.IM.Memory_Data 1472 0.00% 0.00% --- 19 unchanged lines hidden --- |