| stats.txt (9797:9cd5f91e7a79) | stats.txt (9838:43d22d746e7a) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21805500 # Number of ticks simulated 5final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21805500 # Number of ticks simulated 5final_tick 21805500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 79844 # Simulator instruction rate (inst/s) 8host_op_rate 79828 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 337538221 # Simulator tick rate (ticks/s) 10host_mem_usage 228256 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 44396 # Simulator instruction rate (inst/s) 8host_op_rate 44386 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 187676879 # Simulator tick rate (ticks/s) 10host_mem_usage 228012 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host |
| 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 477 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) | 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 477 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 983238174 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 416775584 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1400013758 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 983238174 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 983238174 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 983238174 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 416775584 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1400013758 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 477 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 477 # Reqs generatd by CPU via cache - shady | 30system.physmem.readReqs 477 # Total number of read requests accepted by DRAM controller 31system.physmem.writeReqs 0 # Total number of write requests accepted by DRAM controller 32system.physmem.readBursts 477 # Total number of DRAM read bursts. Each DRAM read request translates to either one or multiple DRAM read bursts 33system.physmem.writeBursts 0 # Total number of DRAM write bursts. Each DRAM write request translates to either one or multiple DRAM write bursts |
| 33system.physmem.bytesRead 30528 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() | 34system.physmem.bytesRead 30528 # Total number of bytes read from memory 35system.physmem.bytesWritten 0 # Total number of bytes written to memory 36system.physmem.bytesConsumedRd 30528 # bytesRead derated as per pkt->getSize() 37system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() |
| 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q | 38system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by write Q |
| 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 39system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 189system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 191system.physmem.avgGap 45547.17 # Average gap between requests 192system.membus.throughput 1400013758 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 426 # Transaction distribution 194system.membus.trans_dist::ReadResp 426 # Transaction distribution 195system.membus.trans_dist::ReadExReq 51 # Transaction distribution 196system.membus.trans_dist::ReadExResp 51 # Transaction distribution | 39system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed 40system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis --- 143 unchanged lines hidden (view full) --- 190system.physmem.readRowHitRate 78.41 # Row buffer hit rate for reads 191system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 192system.physmem.avgGap 45547.17 # Average gap between requests 193system.membus.throughput 1400013758 # Throughput (bytes/s) 194system.membus.trans_dist::ReadReq 426 # Transaction distribution 195system.membus.trans_dist::ReadResp 426 # Transaction distribution 196system.membus.trans_dist::ReadExReq 51 # Transaction distribution 197system.membus.trans_dist::ReadExResp 51 # Transaction distribution |
| 197system.membus.pkt_count_system.cpu.l2cache.mem_side 954 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 954 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30528 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 30528 # Cumulative packet size per connected master and slave (bytes) | 198system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 199system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 200system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 201system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) |
| 201system.membus.data_through_bus 30528 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 205system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 20.5 # Layer utilization (%) 207system.cpu.branchPred.lookups 2187 # Number of BP lookups 208system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted --- 281 unchanged lines hidden (view full) --- 490system.cpu.fp_regfile_reads 3 # number of floating regfile reads 491system.cpu.fp_regfile_writes 1 # number of floating regfile writes 492system.cpu.misc_regfile_reads 148 # number of misc regfile reads 493system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) 494system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution | 202system.membus.data_through_bus 30528 # Total data (bytes) 203system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 204system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) 205system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 206system.membus.respLayer1.occupancy 4480000 # Layer occupancy (ticks) 207system.membus.respLayer1.utilization 20.5 # Layer utilization (%) 208system.cpu.branchPred.lookups 2187 # Number of BP lookups 209system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted --- 281 unchanged lines hidden (view full) --- 491system.cpu.fp_regfile_reads 3 # number of floating regfile reads 492system.cpu.fp_regfile_writes 1 # number of floating regfile writes 493system.cpu.misc_regfile_reads 148 # number of misc regfile reads 494system.cpu.toL2Bus.throughput 1408818876 # Throughput (bytes/s) 495system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 498system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution |
| 498system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 676 # Packet count per connected master and slave (bytes) 499system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count 960 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21632 # Cumulative packet size per connected master and slave (bytes) 502system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.tot_pkt_size 30720 # Cumulative packet size per connected master and slave (bytes) | 499system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 502system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 504system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) |
| 504system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 505system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 506system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 507system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 508system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) 509system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 510system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) 511system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) | 505system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 506system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 507system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 508system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 509system.cpu.toL2Bus.respLayer0.occupancy 573500 # Layer occupancy (ticks) 510system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) 511system.cpu.toL2Bus.respLayer1.occupancy 230000 # Layer occupancy (ticks) 512system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) |
| 512system.cpu.icache.tags.replacements 17 # number of replacements 513system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use 514system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. 515system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 516system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. 517system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 518system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor 519system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy 520system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy | 513system.cpu.icache.tags.replacements 17 # number of replacements 514system.cpu.icache.tags.tagsinuse 160.845390 # Cycle average of tags in use 515system.cpu.icache.tags.total_refs 1531 # Total number of references to valid blocks. 516system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 517system.cpu.icache.tags.avg_refs 4.529586 # Average number of references to valid blocks. 518system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 519system.cpu.icache.tags.occ_blocks::cpu.inst 160.845390 # Average occupied blocks per requestor 520system.cpu.icache.tags.occ_percent::cpu.inst 0.078538 # Average percentage of cache occupancy 521system.cpu.icache.tags.occ_percent::total 0.078538 # Average percentage of cache occupancy |
| 521system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits 522system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits 523system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits 524system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits 525system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits 526system.cpu.icache.overall_hits::total 1531 # number of overall hits 527system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses 528system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 588system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency 590system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 592system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 594system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 595system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | 522system.cpu.icache.ReadReq_hits::cpu.inst 1531 # number of ReadReq hits 523system.cpu.icache.ReadReq_hits::total 1531 # number of ReadReq hits 524system.cpu.icache.demand_hits::cpu.inst 1531 # number of demand (read+write) hits 525system.cpu.icache.demand_hits::total 1531 # number of demand (read+write) hits 526system.cpu.icache.overall_hits::cpu.inst 1531 # number of overall hits 527system.cpu.icache.overall_hits::total 1531 # number of overall hits 528system.cpu.icache.ReadReq_misses::cpu.inst 454 # number of ReadReq misses 529system.cpu.icache.ReadReq_misses::total 454 # number of ReadReq misses --- 59 unchanged lines hidden (view full) --- 589system.cpu.icache.overall_mshr_miss_rate::total 0.170277 # mshr miss rate for overall accesses 590system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70585.798817 # average ReadReq mshr miss latency 591system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70585.798817 # average ReadReq mshr miss latency 592system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 593system.cpu.icache.demand_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 594system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70585.798817 # average overall mshr miss latency 595system.cpu.icache.overall_avg_mshr_miss_latency::total 70585.798817 # average overall mshr miss latency 596system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 596system.cpu.l2cache.tags.replacements 0 # number of replacements 597system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use 598system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 599system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 600system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 601system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 602system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor 603system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor | 597system.cpu.l2cache.tags.replacements 0 # number of replacements 598system.cpu.l2cache.tags.tagsinuse 220.792115 # Cycle average of tags in use 599system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 600system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 601system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 602system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 603system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.133804 # Average occupied blocks per requestor 604system.cpu.l2cache.tags.occ_blocks::cpu.data 57.658310 # Average occupied blocks per requestor |
| 604system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy 605system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy | 605system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004978 # Average percentage of cache occupancy 606system.cpu.l2cache.tags.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy |
| 606system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy | 607system.cpu.l2cache.tags.occ_percent::total 0.006738 # Average percentage of cache occupancy |
| 607system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 608system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 609system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 610system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 611system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 612system.cpu.l2cache.overall_hits::total 3 # number of overall hits 613system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses --- 98 unchanged lines hidden (view full) --- 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency 714system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 717system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 720system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | 608system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 609system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 610system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 611system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 612system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 613system.cpu.l2cache.overall_hits::total 3 # number of overall hits 614system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses 615system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses --- 98 unchanged lines hidden (view full) --- 714system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63308.823529 # average ReadExReq mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 717system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57459.701493 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64862.676056 # average overall mshr miss latency 720system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59663.522013 # average overall mshr miss latency 721system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate |
| 721system.cpu.dcache.tags.replacements 0 # number of replacements 722system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use 723system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 724system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 725system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 726system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 727system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor 728system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy 729system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy | 722system.cpu.dcache.tags.replacements 0 # number of replacements 723system.cpu.dcache.tags.tagsinuse 91.308892 # Cycle average of tags in use 724system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 725system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 726system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 727system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 728system.cpu.dcache.tags.occ_blocks::cpu.data 91.308892 # Average occupied blocks per requestor 729system.cpu.dcache.tags.occ_percent::cpu.data 0.022292 # Average percentage of cache occupancy 730system.cpu.dcache.tags.occ_percent::total 0.022292 # Average percentage of cache occupancy |
| 730system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 731system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 732system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 733system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 734system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 735system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 736system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 737system.cpu.dcache.overall_hits::total 2395 # number of overall hits --- 91 unchanged lines hidden --- | 731system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 732system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits 733system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 734system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 735system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 736system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 737system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 738system.cpu.dcache.overall_hits::total 2395 # number of overall hits --- 91 unchanged lines hidden --- |