| stats.txt (9620:89aa34e10625) | stats.txt (9729:e2fafd224f43) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17026500 # Number of ticks simulated 5final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21759500 # Number of ticks simulated 5final_tick 21759500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 19281 # Simulator instruction rate (inst/s) 8host_op_rate 19280 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 63663526 # Simulator tick rate (ticks/s) 10host_mem_usage 270344 # Number of bytes of host memory used 11host_seconds 0.27 # Real time elapsed on the host | 7host_inst_rate 43168 # Simulator instruction rate (inst/s) 8host_op_rate 43158 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 182102261 # Simulator tick rate (ticks/s) 10host_mem_usage 228268 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host |
| 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 478 # Number of read requests responded to by this memory | 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 478 # Number of read requests responded to by this memory |
| 22system.physmem.bw_read::cpu.inst 1262972425 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 533756204 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1796728629 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1262972425 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1262972425 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1262972425 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 533756204 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1796728629 # Total bandwidth to/from this memory (bytes/s) | 22system.physmem.bw_read::cpu.inst 988258002 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 417656656 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 1405914658 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 988258002 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 988258002 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 988258002 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 417656656 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 1405914658 # Total bandwidth to/from this memory (bytes/s) |
| 30system.physmem.readReqs 478 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30592 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed | 30system.physmem.readReqs 478 # Total number of read requests seen 31system.physmem.writeReqs 0 # Total number of write requests seen 32system.physmem.cpureqs 478 # Reqs generatd by CPU via cache - shady 33system.physmem.bytesRead 30592 # Total number of bytes read from memory 34system.physmem.bytesWritten 0 # Total number of bytes written to memory 35system.physmem.bytesConsumedRd 30592 # bytesRead derated as per pkt->getSize() 36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize() 37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q 38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed |
| 39system.physmem.perBankRdReqs::0 93 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 11 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 17 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 31 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 23 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 15 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 36 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 35 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 16 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 30 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 51 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 38 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 5 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 28 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 11 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 38 # Track reads on a per bank basis | 39system.physmem.perBankRdReqs::0 30 # Track reads on a per bank basis 40system.physmem.perBankRdReqs::1 0 # Track reads on a per bank basis 41system.physmem.perBankRdReqs::2 1 # Track reads on a per bank basis 42system.physmem.perBankRdReqs::3 0 # Track reads on a per bank basis 43system.physmem.perBankRdReqs::4 7 # Track reads on a per bank basis 44system.physmem.perBankRdReqs::5 3 # Track reads on a per bank basis 45system.physmem.perBankRdReqs::6 13 # Track reads on a per bank basis 46system.physmem.perBankRdReqs::7 54 # Track reads on a per bank basis 47system.physmem.perBankRdReqs::8 64 # Track reads on a per bank basis 48system.physmem.perBankRdReqs::9 77 # Track reads on a per bank basis 49system.physmem.perBankRdReqs::10 44 # Track reads on a per bank basis 50system.physmem.perBankRdReqs::11 20 # Track reads on a per bank basis 51system.physmem.perBankRdReqs::12 51 # Track reads on a per bank basis 52system.physmem.perBankRdReqs::13 29 # Track reads on a per bank basis 53system.physmem.perBankRdReqs::14 77 # Track reads on a per bank basis 54system.physmem.perBankRdReqs::15 8 # Track reads on a per bank basis |
| 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry | 55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis 56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis 57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis 58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis 59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis 60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis 61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis 62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis 63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis 64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis 65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis 66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis 67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis 68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis 69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis 70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis 71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry 72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry |
| 73system.physmem.totGap 16967000 # Total gap between requests | 73system.physmem.totGap 21680500 # Total gap between requests |
| 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 478 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes | 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 478 # Categorize read packet sizes 81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
| 88system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see | 88system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 43 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 3 # What read queue length does an incoming req see |
| 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see | 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 98system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 43 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
| 152system.physmem.totQLat 2843000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 14596750 # Sum of mem lat for all requests | 152system.physmem.bytesPerActivate::samples 103 # Bytes accessed per row activation 153system.physmem.bytesPerActivate::mean 242.330097 # Bytes accessed per row activation 154system.physmem.bytesPerActivate::gmean 156.624939 # Bytes accessed per row activation 155system.physmem.bytesPerActivate::stdev 303.862985 # Bytes accessed per row activation 156system.physmem.bytesPerActivate::64 39 37.86% 37.86% # Bytes accessed per row activation 157system.physmem.bytesPerActivate::128 15 14.56% 52.43% # Bytes accessed per row activation 158system.physmem.bytesPerActivate::192 16 15.53% 67.96% # Bytes accessed per row activation 159system.physmem.bytesPerActivate::256 7 6.80% 74.76% # Bytes accessed per row activation 160system.physmem.bytesPerActivate::320 8 7.77% 82.52% # Bytes accessed per row activation 161system.physmem.bytesPerActivate::384 2 1.94% 84.47% # Bytes accessed per row activation 162system.physmem.bytesPerActivate::448 4 3.88% 88.35% # Bytes accessed per row activation 163system.physmem.bytesPerActivate::512 1 0.97% 89.32% # Bytes accessed per row activation 164system.physmem.bytesPerActivate::576 4 3.88% 93.20% # Bytes accessed per row activation 165system.physmem.bytesPerActivate::704 1 0.97% 94.17% # Bytes accessed per row activation 166system.physmem.bytesPerActivate::832 2 1.94% 96.12% # Bytes accessed per row activation 167system.physmem.bytesPerActivate::960 1 0.97% 97.09% # Bytes accessed per row activation 168system.physmem.bytesPerActivate::1024 2 1.94% 99.03% # Bytes accessed per row activation 169system.physmem.bytesPerActivate::2368 1 0.97% 100.00% # Bytes accessed per row activation 170system.physmem.bytesPerActivate::total 103 # Bytes accessed per row activation 171system.physmem.totQLat 2435500 # Total cycles spent in queuing delays 172system.physmem.totMemAccLat 13501750 # Sum of mem lat for all requests |
| 154system.physmem.totBusLat 2390000 # Total cycles spent in databus access | 173system.physmem.totBusLat 2390000 # Total cycles spent in databus access |
| 155system.physmem.totBankLat 9363750 # Total cycles spent in bank access 156system.physmem.avgQLat 5947.70 # Average queueing delay per request 157system.physmem.avgBankLat 19589.44 # Average bank access latency per request | 174system.physmem.totBankLat 8676250 # Total cycles spent in bank access 175system.physmem.avgQLat 5095.19 # Average queueing delay per request 176system.physmem.avgBankLat 18151.15 # Average bank access latency per request |
| 158system.physmem.avgBusLat 5000.00 # Average bus latency per request | 177system.physmem.avgBusLat 5000.00 # Average bus latency per request |
| 159system.physmem.avgMemAccLat 30537.13 # Average memory access latency 160system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s | 178system.physmem.avgMemAccLat 28246.34 # Average memory access latency 179system.physmem.avgRdBW 1405.91 # Average achieved read bandwidth in MB/s |
| 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s | 180system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s |
| 162system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s | 181system.physmem.avgConsumedRdBW 1405.91 # Average consumed read bandwidth in MB/s |
| 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s | 182system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 183system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s |
| 165system.physmem.busUtil 14.04 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.86 # Average read queue length over time | 184system.physmem.busUtil 10.98 # Data bus utilization in percentage 185system.physmem.avgRdQLen 0.62 # Average read queue length over time |
| 167system.physmem.avgWrQLen 0.00 # Average write queue length over time | 186system.physmem.avgWrQLen 0.00 # Average write queue length over time |
| 168system.physmem.readRowHits 351 # Number of row buffer hits during reads | 187system.physmem.readRowHits 375 # Number of row buffer hits during reads |
| 169system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 188system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 170system.physmem.readRowHitRate 73.43 # Row buffer hit rate for reads | 189system.physmem.readRowHitRate 78.45 # Row buffer hit rate for reads |
| 171system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 190system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 172system.physmem.avgGap 35495.82 # Average gap between requests 173system.cpu.branchPred.lookups 2218 # Number of BP lookups 174system.cpu.branchPred.condPredicted 1500 # Number of conditional branches predicted 175system.cpu.branchPred.condIncorrect 439 # Number of conditional branches incorrect 176system.cpu.branchPred.BTBLookups 1689 # Number of BTB lookups 177system.cpu.branchPred.BTBHits 508 # Number of BTB hits | 191system.physmem.avgGap 45356.69 # Average gap between requests 192system.membus.throughput 1405914658 # Throughput (bytes/s) 193system.membus.trans_dist::ReadReq 427 # Transaction distribution 194system.membus.trans_dist::ReadResp 427 # Transaction distribution 195system.membus.trans_dist::ReadExReq 51 # Transaction distribution 196system.membus.trans_dist::ReadExResp 51 # Transaction distribution 197system.membus.pkt_count_system.cpu.l2cache.mem_side 956 # Packet count per connected master and slave (bytes) 198system.membus.pkt_count 956 # Packet count per connected master and slave (bytes) 199system.membus.tot_pkt_size_system.cpu.l2cache.mem_side 30592 # Cumulative packet size per connected master and slave (bytes) 200system.membus.tot_pkt_size 30592 # Cumulative packet size per connected master and slave (bytes) 201system.membus.data_through_bus 30592 # Total data (bytes) 202system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) 203system.membus.reqLayer0.occupancy 590000 # Layer occupancy (ticks) 204system.membus.reqLayer0.utilization 2.7 # Layer utilization (%) 205system.membus.respLayer1.occupancy 4475750 # Layer occupancy (ticks) 206system.membus.respLayer1.utilization 20.6 # Layer utilization (%) 207system.cpu.branchPred.lookups 2196 # Number of BP lookups 208system.cpu.branchPred.condPredicted 1494 # Number of conditional branches predicted 209system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 210system.cpu.branchPred.BTBLookups 1671 # Number of BTB lookups 211system.cpu.branchPred.BTBHits 505 # Number of BTB hits |
| 178system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 212system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 179system.cpu.branchPred.BTBHitPct 30.076969 # BTB Hit Percentage 180system.cpu.branchPred.usedRAS 271 # Number of times the RAS was used to get a target. 181system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. | 213system.cpu.branchPred.BTBHitPct 30.221424 # BTB Hit Percentage 214system.cpu.branchPred.usedRAS 262 # Number of times the RAS was used to get a target. 215system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. |
| 182system.cpu.dtb.read_hits 0 # DTB read hits 183system.cpu.dtb.read_misses 0 # DTB read misses 184system.cpu.dtb.read_accesses 0 # DTB read accesses 185system.cpu.dtb.write_hits 0 # DTB write hits 186system.cpu.dtb.write_misses 0 # DTB write misses 187system.cpu.dtb.write_accesses 0 # DTB write accesses 188system.cpu.dtb.hits 0 # DTB hits 189system.cpu.dtb.misses 0 # DTB misses 190system.cpu.dtb.accesses 0 # DTB accesses 191system.cpu.itb.read_hits 0 # DTB read hits 192system.cpu.itb.read_misses 0 # DTB read misses 193system.cpu.itb.read_accesses 0 # DTB read accesses 194system.cpu.itb.write_hits 0 # DTB write hits 195system.cpu.itb.write_misses 0 # DTB write misses 196system.cpu.itb.write_accesses 0 # DTB write accesses 197system.cpu.itb.hits 0 # DTB hits 198system.cpu.itb.misses 0 # DTB misses 199system.cpu.itb.accesses 0 # DTB accesses 200system.cpu.workload.num_syscalls 8 # Number of system calls | 216system.cpu.dtb.read_hits 0 # DTB read hits 217system.cpu.dtb.read_misses 0 # DTB read misses 218system.cpu.dtb.read_accesses 0 # DTB read accesses 219system.cpu.dtb.write_hits 0 # DTB write hits 220system.cpu.dtb.write_misses 0 # DTB write misses 221system.cpu.dtb.write_accesses 0 # DTB write accesses 222system.cpu.dtb.hits 0 # DTB hits 223system.cpu.dtb.misses 0 # DTB misses 224system.cpu.dtb.accesses 0 # DTB accesses 225system.cpu.itb.read_hits 0 # DTB read hits 226system.cpu.itb.read_misses 0 # DTB read misses 227system.cpu.itb.read_accesses 0 # DTB read accesses 228system.cpu.itb.write_hits 0 # DTB write hits 229system.cpu.itb.write_misses 0 # DTB write misses 230system.cpu.itb.write_accesses 0 # DTB write accesses 231system.cpu.itb.hits 0 # DTB hits 232system.cpu.itb.misses 0 # DTB misses 233system.cpu.itb.accesses 0 # DTB accesses 234system.cpu.workload.num_syscalls 8 # Number of system calls |
| 201system.cpu.numCycles 34054 # number of cpu cycles simulated | 235system.cpu.numCycles 43520 # number of cpu cycles simulated |
| 202system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 203system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 236system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 237system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 204system.cpu.fetch.icacheStallCycles 8765 # Number of cycles fetch is stalled on an Icache miss 205system.cpu.fetch.Insts 13373 # Number of instructions fetch has processed 206system.cpu.fetch.Branches 2218 # Number of branches that fetch encountered 207system.cpu.fetch.predictedBranches 779 # Number of branches that fetch has predicted taken 208system.cpu.fetch.Cycles 3270 # Number of cycles fetch has run and was not squashing or blocked 209system.cpu.fetch.SquashCycles 1400 # Number of cycles fetch has spent squashing 210system.cpu.fetch.BlockedCycles 1014 # Number of cycles fetch has spent blocked | 238system.cpu.fetch.icacheStallCycles 8865 # Number of cycles fetch is stalled on an Icache miss 239system.cpu.fetch.Insts 13232 # Number of instructions fetch has processed 240system.cpu.fetch.Branches 2196 # Number of branches that fetch encountered 241system.cpu.fetch.predictedBranches 767 # Number of branches that fetch has predicted taken 242system.cpu.fetch.Cycles 3240 # Number of cycles fetch has run and was not squashing or blocked 243system.cpu.fetch.SquashCycles 1388 # Number of cycles fetch has spent squashing 244system.cpu.fetch.BlockedCycles 1327 # Number of cycles fetch has spent blocked |
| 211system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps | 245system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps |
| 212system.cpu.fetch.CacheLines 2012 # Number of cache lines fetched 213system.cpu.fetch.IcacheSquashes 279 # Number of outstanding Icache misses that were squashed 214system.cpu.fetch.rateDist::samples 14123 # Number of instructions fetched each cycle (Total) 215system.cpu.fetch.rateDist::mean 0.946895 # Number of instructions fetched each cycle (Total) 216system.cpu.fetch.rateDist::stdev 2.257314 # Number of instructions fetched each cycle (Total) | 246system.cpu.fetch.CacheLines 1994 # Number of cache lines fetched 247system.cpu.fetch.IcacheSquashes 285 # Number of outstanding Icache misses that were squashed 248system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) 249system.cpu.fetch.rateDist::mean 0.912867 # Number of instructions fetched each cycle (Total) 250system.cpu.fetch.rateDist::stdev 2.222713 # Number of instructions fetched each cycle (Total) |
| 217system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 251system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 218system.cpu.fetch.rateDist::0 10853 76.85% 76.85% # Number of instructions fetched each cycle (Total) 219system.cpu.fetch.rateDist::1 1348 9.54% 86.39% # Number of instructions fetched each cycle (Total) 220system.cpu.fetch.rateDist::2 105 0.74% 87.13% # Number of instructions fetched each cycle (Total) 221system.cpu.fetch.rateDist::3 135 0.96% 88.09% # Number of instructions fetched each cycle (Total) 222system.cpu.fetch.rateDist::4 305 2.16% 90.25% # Number of instructions fetched each cycle (Total) 223system.cpu.fetch.rateDist::5 118 0.84% 91.09% # Number of instructions fetched each cycle (Total) 224system.cpu.fetch.rateDist::6 156 1.10% 92.19% # Number of instructions fetched each cycle (Total) 225system.cpu.fetch.rateDist::7 160 1.13% 93.32% # Number of instructions fetched each cycle (Total) 226system.cpu.fetch.rateDist::8 943 6.68% 100.00% # Number of instructions fetched each cycle (Total) | 252system.cpu.fetch.rateDist::0 11255 77.65% 77.65% # Number of instructions fetched each cycle (Total) 253system.cpu.fetch.rateDist::1 1338 9.23% 86.88% # Number of instructions fetched each cycle (Total) 254system.cpu.fetch.rateDist::2 104 0.72% 87.60% # Number of instructions fetched each cycle (Total) 255system.cpu.fetch.rateDist::3 132 0.91% 88.51% # Number of instructions fetched each cycle (Total) 256system.cpu.fetch.rateDist::4 307 2.12% 90.62% # Number of instructions fetched each cycle (Total) 257system.cpu.fetch.rateDist::5 118 0.81% 91.44% # Number of instructions fetched each cycle (Total) 258system.cpu.fetch.rateDist::6 149 1.03% 92.47% # Number of instructions fetched each cycle (Total) 259system.cpu.fetch.rateDist::7 158 1.09% 93.56% # Number of instructions fetched each cycle (Total) 260system.cpu.fetch.rateDist::8 934 6.44% 100.00% # Number of instructions fetched each cycle (Total) |
| 227system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 228system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 229system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 261system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 262system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 263system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 230system.cpu.fetch.rateDist::total 14123 # Number of instructions fetched each cycle (Total) 231system.cpu.fetch.branchRate 0.065132 # Number of branch fetches per cycle 232system.cpu.fetch.rate 0.392700 # Number of inst fetches per cycle 233system.cpu.decode.IdleCycles 8861 # Number of cycles decode is idle 234system.cpu.decode.BlockedCycles 1237 # Number of cycles decode is blocked 235system.cpu.decode.RunCycles 3093 # Number of cycles decode is running 236system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking 237system.cpu.decode.SquashCycles 888 # Number of cycles decode is squashing | 264system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) 265system.cpu.fetch.branchRate 0.050460 # Number of branch fetches per cycle 266system.cpu.fetch.rate 0.304044 # Number of inst fetches per cycle 267system.cpu.decode.IdleCycles 8953 # Number of cycles decode is idle 268system.cpu.decode.BlockedCycles 1558 # Number of cycles decode is blocked 269system.cpu.decode.RunCycles 3054 # Number of cycles decode is running 270system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 271system.cpu.decode.SquashCycles 877 # Number of cycles decode is squashing |
| 238system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch 239system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction | 272system.cpu.decode.BranchResolved 168 # Number of times decode resolved a branch 273system.cpu.decode.BranchMispred 44 # Number of times decode detected a branch misprediction |
| 240system.cpu.decode.DecodedInsts 12489 # Number of instructions handled by decode | 274system.cpu.decode.DecodedInsts 12351 # Number of instructions handled by decode |
| 241system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode | 275system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode |
| 242system.cpu.rename.SquashCycles 888 # Number of cycles rename is squashing 243system.cpu.rename.IdleCycles 9042 # Number of cycles rename is idle 244system.cpu.rename.BlockCycles 324 # Number of cycles rename is blocking 245system.cpu.rename.serializeStallCycles 802 # count of cycles rename stalled for serializing inst 246system.cpu.rename.RunCycles 2958 # Number of cycles rename is running 247system.cpu.rename.UnblockCycles 109 # Number of cycles rename is unblocking 248system.cpu.rename.RenamedInsts 11987 # Number of instructions processed by rename 249system.cpu.rename.ROBFullEvents 2 # Number of times rename has blocked due to ROB full | 276system.cpu.rename.SquashCycles 877 # Number of cycles rename is squashing 277system.cpu.rename.IdleCycles 9138 # Number of cycles rename is idle 278system.cpu.rename.BlockCycles 511 # Number of cycles rename is blocking 279system.cpu.rename.serializeStallCycles 897 # count of cycles rename stalled for serializing inst 280system.cpu.rename.RunCycles 2924 # Number of cycles rename is running 281system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 282system.cpu.rename.RenamedInsts 11915 # Number of instructions processed by rename 283system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full |
| 250system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full | 284system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full |
| 251system.cpu.rename.LSQFullEvents 93 # Number of times rename has blocked due to LSQ full 252system.cpu.rename.RenamedOperands 7237 # Number of destination operands rename has renamed 253system.cpu.rename.RenameLookups 14212 # Number of register rename lookups that rename has made 254system.cpu.rename.int_rename_lookups 14208 # Number of integer rename lookups | 285system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 286system.cpu.rename.RenamedOperands 7195 # Number of destination operands rename has renamed 287system.cpu.rename.RenameLookups 14132 # Number of register rename lookups that rename has made 288system.cpu.rename.int_rename_lookups 14128 # Number of integer rename lookups |
| 255system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 256system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed | 289system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups 290system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed |
| 257system.cpu.rename.UndoneMaps 3839 # Number of HB maps that are undone due to squashing 258system.cpu.rename.serializingInsts 18 # count of serializing insts renamed 259system.cpu.rename.tempSerializingInsts 12 # count of temporary serializing insts renamed 260system.cpu.rename.skidInsts 276 # count of insts added to the skid buffer 261system.cpu.memDep0.insertedLoads 2482 # Number of loads inserted to the mem dependence unit. 262system.cpu.memDep0.insertedStores 1199 # Number of stores inserted to the mem dependence unit. | 291system.cpu.rename.UndoneMaps 3797 # Number of HB maps that are undone due to squashing 292system.cpu.rename.serializingInsts 17 # count of serializing insts renamed 293system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed 294system.cpu.rename.skidInsts 333 # count of insts added to the skid buffer 295system.cpu.memDep0.insertedLoads 2463 # Number of loads inserted to the mem dependence unit. 296system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. |
| 263system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 264system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. | 297system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 298system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. |
| 265system.cpu.iq.iqInstsAdded 9295 # Number of instructions added to the IQ (excludes non-spec) 266system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ 267system.cpu.iq.iqInstsIssued 8318 # Number of instructions issued 268system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued 269system.cpu.iq.iqSquashedInstsExamined 3635 # Number of squashed instructions iterated over during squash; mainly for profiling 270system.cpu.iq.iqSquashedOperandsExamined 2167 # Number of squashed operands that are examined and possibly removed from graph 271system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed 272system.cpu.iq.issued_per_cycle::samples 14123 # Number of insts issued each cycle 273system.cpu.iq.issued_per_cycle::mean 0.588968 # Number of insts issued each cycle 274system.cpu.iq.issued_per_cycle::stdev 1.255126 # Number of insts issued each cycle | 299system.cpu.iq.iqInstsAdded 9245 # Number of instructions added to the IQ (excludes non-spec) 300system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 301system.cpu.iq.iqInstsIssued 8313 # Number of instructions issued 302system.cpu.iq.iqSquashedInstsIssued 42 # Number of squashed instructions issued 303system.cpu.iq.iqSquashedInstsExamined 3584 # Number of squashed instructions iterated over during squash; mainly for profiling 304system.cpu.iq.iqSquashedOperandsExamined 2108 # Number of squashed operands that are examined and possibly removed from graph 305system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 306system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle 307system.cpu.iq.issued_per_cycle::mean 0.573508 # Number of insts issued each cycle 308system.cpu.iq.issued_per_cycle::stdev 1.239818 # Number of insts issued each cycle |
| 275system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 309system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 276system.cpu.iq.issued_per_cycle::0 10544 74.66% 74.66% # Number of insts issued each cycle 277system.cpu.iq.issued_per_cycle::1 1399 9.91% 84.56% # Number of insts issued each cycle 278system.cpu.iq.issued_per_cycle::2 897 6.35% 90.92% # Number of insts issued each cycle 279system.cpu.iq.issued_per_cycle::3 565 4.00% 94.92% # Number of insts issued each cycle 280system.cpu.iq.issued_per_cycle::4 359 2.54% 97.46% # Number of insts issued each cycle 281system.cpu.iq.issued_per_cycle::5 225 1.59% 99.05% # Number of insts issued each cycle 282system.cpu.iq.issued_per_cycle::6 87 0.62% 99.67% # Number of insts issued each cycle 283system.cpu.iq.issued_per_cycle::7 29 0.21% 99.87% # Number of insts issued each cycle 284system.cpu.iq.issued_per_cycle::8 18 0.13% 100.00% # Number of insts issued each cycle | 310system.cpu.iq.issued_per_cycle::0 10895 75.16% 75.16% # Number of insts issued each cycle 311system.cpu.iq.issued_per_cycle::1 1434 9.89% 85.06% # Number of insts issued each cycle 312system.cpu.iq.issued_per_cycle::2 892 6.15% 91.21% # Number of insts issued each cycle 313system.cpu.iq.issued_per_cycle::3 557 3.84% 95.05% # Number of insts issued each cycle 314system.cpu.iq.issued_per_cycle::4 358 2.47% 97.52% # Number of insts issued each cycle 315system.cpu.iq.issued_per_cycle::5 226 1.56% 99.08% # Number of insts issued each cycle 316system.cpu.iq.issued_per_cycle::6 86 0.59% 99.68% # Number of insts issued each cycle 317system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 318system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle |
| 285system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 286system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 287system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 319system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 320system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 321system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 288system.cpu.iq.issued_per_cycle::total 14123 # Number of insts issued each cycle | 322system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle |
| 289system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 290system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available 291system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available 292system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available 293system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available 294system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available 295system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available 296system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 316system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available 317system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available 318system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available 319system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available 320system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available 321system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 322system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 323system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 323system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 324system.cpu.iq.fu_full::IntAlu 5 3.14% 3.14% # attempts to use FU when none available 325system.cpu.iq.fu_full::IntMult 0 0.00% 3.14% # attempts to use FU when none available 326system.cpu.iq.fu_full::IntDiv 0 0.00% 3.14% # attempts to use FU when none available 327system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.14% # attempts to use FU when none available 328system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.14% # attempts to use FU when none available 329system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.14% # attempts to use FU when none available 330system.cpu.iq.fu_full::FloatMult 0 0.00% 3.14% # attempts to use FU when none available --- 19 unchanged lines hidden (view full) --- 350system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.14% # attempts to use FU when none available 351system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.14% # attempts to use FU when none available 352system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.14% # attempts to use FU when none available 353system.cpu.iq.fu_full::MemRead 100 62.89% 66.04% # attempts to use FU when none available 354system.cpu.iq.fu_full::MemWrite 54 33.96% 100.00% # attempts to use FU when none available 355system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 356system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 357system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 324system.cpu.iq.FU_type_0::IntAlu 4943 59.43% 59.43% # Type of FU issued 325system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.49% # Type of FU issued 326system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.51% # Type of FU issued 327system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.53% # Type of FU issued 328system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.53% # Type of FU issued 329system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.53% # Type of FU issued 330system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.53% # Type of FU issued 331system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.53% # Type of FU issued 332system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.53% # Type of FU issued 333system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.53% # Type of FU issued 334system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.53% # Type of FU issued 335system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.53% # Type of FU issued 336system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.53% # Type of FU issued 337system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.53% # Type of FU issued 338system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.53% # Type of FU issued 339system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.53% # Type of FU issued 340system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.53% # Type of FU issued 341system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.53% # Type of FU issued 342system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.53% # Type of FU issued 343system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.53% # Type of FU issued 344system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.53% # Type of FU issued 345system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.53% # Type of FU issued 346system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.53% # Type of FU issued 347system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.53% # Type of FU issued 348system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.53% # Type of FU issued 349system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.53% # Type of FU issued 350system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.53% # Type of FU issued 351system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.53% # Type of FU issued 352system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.53% # Type of FU issued 353system.cpu.iq.FU_type_0::MemRead 2262 27.19% 86.73% # Type of FU issued 354system.cpu.iq.FU_type_0::MemWrite 1104 13.27% 100.00% # Type of FU issued | 358system.cpu.iq.FU_type_0::IntAlu 4947 59.51% 59.51% # Type of FU issued 359system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.57% # Type of FU issued 360system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.59% # Type of FU issued 361system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.62% # Type of FU issued 362system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.62% # Type of FU issued 363system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.62% # Type of FU issued 364system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.62% # Type of FU issued 365system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.62% # Type of FU issued 366system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.62% # Type of FU issued 367system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.62% # Type of FU issued 368system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.62% # Type of FU issued 369system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.62% # Type of FU issued 370system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.62% # Type of FU issued 371system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.62% # Type of FU issued 372system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.62% # Type of FU issued 373system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.62% # Type of FU issued 374system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.62% # Type of FU issued 375system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.62% # Type of FU issued 376system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.62% # Type of FU issued 377system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.62% # Type of FU issued 378system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.62% # Type of FU issued 379system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.62% # Type of FU issued 380system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.62% # Type of FU issued 381system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.62% # Type of FU issued 382system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.62% # Type of FU issued 383system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.62% # Type of FU issued 384system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.62% # Type of FU issued 385system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.62% # Type of FU issued 386system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.62% # Type of FU issued 387system.cpu.iq.FU_type_0::MemRead 2253 27.10% 86.72% # Type of FU issued 388system.cpu.iq.FU_type_0::MemWrite 1104 13.28% 100.00% # Type of FU issued |
| 355system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 356system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 389system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 390system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 357system.cpu.iq.FU_type_0::total 8318 # Type of FU issued 358system.cpu.iq.rate 0.244259 # Inst issue rate | 391system.cpu.iq.FU_type_0::total 8313 # Type of FU issued 392system.cpu.iq.rate 0.191016 # Inst issue rate |
| 359system.cpu.iq.fu_busy_cnt 159 # FU busy when requested | 393system.cpu.iq.fu_busy_cnt 159 # FU busy when requested |
| 360system.cpu.iq.fu_busy_rate 0.019115 # FU busy rate (busy events/executed inst) 361system.cpu.iq.int_inst_queue_reads 30960 # Number of integer instruction queue reads 362system.cpu.iq.int_inst_queue_writes 12952 # Number of integer instruction queue writes 363system.cpu.iq.int_inst_queue_wakeup_accesses 7465 # Number of integer instruction queue wakeup accesses | 394system.cpu.iq.fu_busy_rate 0.019127 # FU busy rate (busy events/executed inst) 395system.cpu.iq.int_inst_queue_reads 31318 # Number of integer instruction queue reads 396system.cpu.iq.int_inst_queue_writes 12850 # Number of integer instruction queue writes 397system.cpu.iq.int_inst_queue_wakeup_accesses 7467 # Number of integer instruction queue wakeup accesses |
| 364system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 365system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 366system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses | 398system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 399system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 400system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses |
| 367system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses | 401system.cpu.iq.int_alu_accesses 8470 # Number of integer alu accesses |
| 368system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses | 402system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses |
| 369system.cpu.iew.lsq.thread0.forwLoads 62 # Number of loads that had data forwarded from stores | 403system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores |
| 370system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 404system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 371system.cpu.iew.lsq.thread0.squashedLoads 1319 # Number of loads squashed | 405system.cpu.iew.lsq.thread0.squashedLoads 1300 # Number of loads squashed |
| 372system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 373system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations | 406system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 407system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations |
| 374system.cpu.iew.lsq.thread0.squashedStores 274 # Number of stores squashed | 408system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed |
| 375system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 376system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 377system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 378system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked 379system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 409system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 410system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 411system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 412system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked 413system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 380system.cpu.iew.iewSquashCycles 888 # Number of cycles IEW is squashing 381system.cpu.iew.iewBlockCycles 223 # Number of cycles IEW is blocking 382system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 383system.cpu.iew.iewDispatchedInsts 10854 # Number of instructions dispatched to IQ 384system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch 385system.cpu.iew.iewDispLoadInsts 2482 # Number of dispatched load instructions 386system.cpu.iew.iewDispStoreInsts 1199 # Number of dispatched store instructions 387system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions | 414system.cpu.iew.iewSquashCycles 877 # Number of cycles IEW is squashing 415system.cpu.iew.iewBlockCycles 334 # Number of cycles IEW is blocking 416system.cpu.iew.iewUnblockCycles 17 # Number of cycles IEW is unblocking 417system.cpu.iew.iewDispatchedInsts 10786 # Number of instructions dispatched to IQ 418system.cpu.iew.iewDispSquashedInsts 86 # Number of squashed instructions skipped by dispatch 419system.cpu.iew.iewDispLoadInsts 2463 # Number of dispatched load instructions 420system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 421system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions |
| 388system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 389system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 390system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations | 422system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall 423system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 424system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations |
| 391system.cpu.iew.predictedTakenIncorrect 106 # Number of branches that were predicted taken incorrectly | 425system.cpu.iew.predictedTakenIncorrect 102 # Number of branches that were predicted taken incorrectly |
| 392system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly | 426system.cpu.iew.predictedNotTakenIncorrect 359 # Number of branches that were predicted not taken incorrectly |
| 393system.cpu.iew.branchMispredicts 465 # Number of branch mispredicts detected at execute 394system.cpu.iew.iewExecutedInsts 7932 # Number of executed instructions 395system.cpu.iew.iewExecLoadInsts 2125 # Number of load instructions executed 396system.cpu.iew.iewExecSquashedInsts 386 # Number of squashed instructions skipped in execute | 427system.cpu.iew.branchMispredicts 461 # Number of branch mispredicts detected at execute 428system.cpu.iew.iewExecutedInsts 7936 # Number of executed instructions 429system.cpu.iew.iewExecLoadInsts 2118 # Number of load instructions executed 430system.cpu.iew.iewExecSquashedInsts 377 # Number of squashed instructions skipped in execute |
| 397system.cpu.iew.exec_swp 0 # number of swp insts executed | 431system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 398system.cpu.iew.exec_nop 1546 # number of nop insts executed 399system.cpu.iew.exec_refs 3202 # number of memory reference insts executed 400system.cpu.iew.exec_branches 1355 # Number of branches executed 401system.cpu.iew.exec_stores 1077 # Number of stores executed 402system.cpu.iew.exec_rate 0.232924 # Inst execution rate 403system.cpu.iew.wb_sent 7556 # cumulative count of insts sent to commit 404system.cpu.iew.wb_count 7467 # cumulative count of insts written-back 405system.cpu.iew.wb_producers 2949 # num instructions producing a value 406system.cpu.iew.wb_consumers 4258 # num instructions consuming a value | 432system.cpu.iew.exec_nop 1529 # number of nop insts executed 433system.cpu.iew.exec_refs 3196 # number of memory reference insts executed 434system.cpu.iew.exec_branches 1356 # Number of branches executed 435system.cpu.iew.exec_stores 1078 # Number of stores executed 436system.cpu.iew.exec_rate 0.182353 # Inst execution rate 437system.cpu.iew.wb_sent 7562 # cumulative count of insts sent to commit 438system.cpu.iew.wb_count 7469 # cumulative count of insts written-back 439system.cpu.iew.wb_producers 2922 # num instructions producing a value 440system.cpu.iew.wb_consumers 4200 # num instructions consuming a value |
| 407system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 441system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 408system.cpu.iew.wb_rate 0.219269 # insts written-back per cycle 409system.cpu.iew.wb_fanout 0.692579 # average fanout of values written-back | 442system.cpu.iew.wb_rate 0.171622 # insts written-back per cycle 443system.cpu.iew.wb_fanout 0.695714 # average fanout of values written-back |
| 410system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 444system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 411system.cpu.commit.commitSquashedInsts 5033 # The number of squashed insts skipped by commit | 445system.cpu.commit.commitSquashedInsts 4965 # The number of squashed insts skipped by commit |
| 412system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards | 446system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards |
| 413system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted 414system.cpu.commit.committed_per_cycle::samples 13235 # Number of insts commited each cycle 415system.cpu.commit.committed_per_cycle::mean 0.439214 # Number of insts commited each cycle 416system.cpu.commit.committed_per_cycle::stdev 1.223104 # Number of insts commited each cycle | 447system.cpu.commit.branchMispredicts 395 # The number of times a branch was mispredicted 448system.cpu.commit.committed_per_cycle::samples 13618 # Number of insts commited each cycle 449system.cpu.commit.committed_per_cycle::mean 0.426862 # Number of insts commited each cycle 450system.cpu.commit.committed_per_cycle::stdev 1.205287 # Number of insts commited each cycle |
| 417system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 451system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 418system.cpu.commit.committed_per_cycle::0 10851 81.99% 81.99% # Number of insts commited each cycle 419system.cpu.commit.committed_per_cycle::1 966 7.30% 89.29% # Number of insts commited each cycle 420system.cpu.commit.committed_per_cycle::2 635 4.80% 94.08% # Number of insts commited each cycle 421system.cpu.commit.committed_per_cycle::3 328 2.48% 96.56% # Number of insts commited each cycle 422system.cpu.commit.committed_per_cycle::4 148 1.12% 97.68% # Number of insts commited each cycle 423system.cpu.commit.committed_per_cycle::5 96 0.73% 98.41% # Number of insts commited each cycle 424system.cpu.commit.committed_per_cycle::6 63 0.48% 98.88% # Number of insts commited each cycle 425system.cpu.commit.committed_per_cycle::7 41 0.31% 99.19% # Number of insts commited each cycle 426system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle | 452system.cpu.commit.committed_per_cycle::0 11210 82.32% 82.32% # Number of insts commited each cycle 453system.cpu.commit.committed_per_cycle::1 1002 7.36% 89.68% # Number of insts commited each cycle 454system.cpu.commit.committed_per_cycle::2 633 4.65% 94.32% # Number of insts commited each cycle 455system.cpu.commit.committed_per_cycle::3 319 2.34% 96.67% # Number of insts commited each cycle 456system.cpu.commit.committed_per_cycle::4 147 1.08% 97.75% # Number of insts commited each cycle 457system.cpu.commit.committed_per_cycle::5 94 0.69% 98.44% # Number of insts commited each cycle 458system.cpu.commit.committed_per_cycle::6 67 0.49% 98.93% # Number of insts commited each cycle 459system.cpu.commit.committed_per_cycle::7 40 0.29% 99.22% # Number of insts commited each cycle 460system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle |
| 427system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 428system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 429system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 461system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 462system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 463system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 430system.cpu.commit.committed_per_cycle::total 13235 # Number of insts commited each cycle | 464system.cpu.commit.committed_per_cycle::total 13618 # Number of insts commited each cycle |
| 431system.cpu.commit.committedInsts 5813 # Number of instructions committed 432system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 433system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 434system.cpu.commit.refs 2088 # Number of memory references committed 435system.cpu.commit.loads 1163 # Number of loads committed 436system.cpu.commit.membars 0 # Number of memory barriers committed 437system.cpu.commit.branches 915 # Number of branches committed 438system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 439system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 440system.cpu.commit.function_calls 87 # Number of function calls committed. | 465system.cpu.commit.committedInsts 5813 # Number of instructions committed 466system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 467system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 468system.cpu.commit.refs 2088 # Number of memory references committed 469system.cpu.commit.loads 1163 # Number of loads committed 470system.cpu.commit.membars 0 # Number of memory barriers committed 471system.cpu.commit.branches 915 # Number of branches committed 472system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 473system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 474system.cpu.commit.function_calls 87 # Number of function calls committed. |
| 441system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached | 475system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached |
| 442system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 476system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 443system.cpu.rob.rob_reads 23961 # The number of ROB reads 444system.cpu.rob.rob_writes 22589 # The number of ROB writes 445system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself 446system.cpu.idleCycles 19931 # Total number of cycles that the CPU has spent unscheduled due to idling | 477system.cpu.rob.rob_reads 24277 # The number of ROB reads 478system.cpu.rob.rob_writes 22442 # The number of ROB writes 479system.cpu.timesIdled 289 # Number of times that the entire CPU went into an idle state and unscheduled itself 480system.cpu.idleCycles 29025 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 447system.cpu.committedInsts 5156 # Number of Instructions Simulated 448system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 449system.cpu.committedInsts_total 5156 # Number of Instructions Simulated | 481system.cpu.committedInsts 5156 # Number of Instructions Simulated 482system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 483system.cpu.committedInsts_total 5156 # Number of Instructions Simulated |
| 450system.cpu.cpi 6.604732 # CPI: Cycles Per Instruction 451system.cpu.cpi_total 6.604732 # CPI: Total CPI of All Threads 452system.cpu.ipc 0.151407 # IPC: Instructions Per Cycle 453system.cpu.ipc_total 0.151407 # IPC: Total IPC of All Threads 454system.cpu.int_regfile_reads 10750 # number of integer regfile reads 455system.cpu.int_regfile_writes 5236 # number of integer regfile writes | 484system.cpu.cpi 8.440652 # CPI: Cycles Per Instruction 485system.cpu.cpi_total 8.440652 # CPI: Total CPI of All Threads 486system.cpu.ipc 0.118474 # IPC: Instructions Per Cycle 487system.cpu.ipc_total 0.118474 # IPC: Total IPC of All Threads 488system.cpu.int_regfile_reads 10757 # number of integer regfile reads 489system.cpu.int_regfile_writes 5239 # number of integer regfile writes |
| 456system.cpu.fp_regfile_reads 3 # number of floating regfile reads 457system.cpu.fp_regfile_writes 1 # number of floating regfile writes | 490system.cpu.fp_regfile_reads 3 # number of floating regfile reads 491system.cpu.fp_regfile_writes 1 # number of floating regfile writes |
| 458system.cpu.misc_regfile_reads 150 # number of misc regfile reads | 492system.cpu.misc_regfile_reads 148 # number of misc regfile reads 493system.cpu.toL2Bus.throughput 1414738390 # Throughput (bytes/s) 494system.cpu.toL2Bus.trans_dist::ReadReq 430 # Transaction distribution 495system.cpu.toL2Bus.trans_dist::ReadResp 430 # Transaction distribution 496system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 497system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 498system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side 678 # Packet count per connected master and slave (bytes) 499system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side 284 # Packet count per connected master and slave (bytes) 500system.cpu.toL2Bus.pkt_count 962 # Packet count per connected master and slave (bytes) 501system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side 21696 # Cumulative packet size per connected master and slave (bytes) 502system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side 9088 # Cumulative packet size per connected master and slave (bytes) 503system.cpu.toL2Bus.tot_pkt_size 30784 # Cumulative packet size per connected master and slave (bytes) 504system.cpu.toL2Bus.data_through_bus 30784 # Total data (bytes) 505system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 506system.cpu.toL2Bus.reqLayer0.occupancy 240500 # Layer occupancy (ticks) 507system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 508system.cpu.toL2Bus.respLayer0.occupancy 508500 # Layer occupancy (ticks) 509system.cpu.toL2Bus.respLayer0.utilization 2.3 # Layer utilization (%) 510system.cpu.toL2Bus.respLayer1.occupancy 213000 # Layer occupancy (ticks) 511system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 459system.cpu.icache.replacements 17 # number of replacements | 512system.cpu.icache.replacements 17 # number of replacements |
| 460system.cpu.icache.tagsinuse 162.197466 # Cycle average of tags in use 461system.cpu.icache.total_refs 1566 # Total number of references to valid blocks. | 513system.cpu.icache.tagsinuse 161.130962 # Cycle average of tags in use 514system.cpu.icache.total_refs 1541 # Total number of references to valid blocks. |
| 462system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. | 515system.cpu.icache.sampled_refs 339 # Sample count of references to valid blocks. |
| 463system.cpu.icache.avg_refs 4.619469 # Average number of references to valid blocks. | 516system.cpu.icache.avg_refs 4.545723 # Average number of references to valid blocks. |
| 464system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 517system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 465system.cpu.icache.occ_blocks::cpu.inst 162.197466 # Average occupied blocks per requestor 466system.cpu.icache.occ_percent::cpu.inst 0.079198 # Average percentage of cache occupancy 467system.cpu.icache.occ_percent::total 0.079198 # Average percentage of cache occupancy 468system.cpu.icache.ReadReq_hits::cpu.inst 1566 # number of ReadReq hits 469system.cpu.icache.ReadReq_hits::total 1566 # number of ReadReq hits 470system.cpu.icache.demand_hits::cpu.inst 1566 # number of demand (read+write) hits 471system.cpu.icache.demand_hits::total 1566 # number of demand (read+write) hits 472system.cpu.icache.overall_hits::cpu.inst 1566 # number of overall hits 473system.cpu.icache.overall_hits::total 1566 # number of overall hits 474system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses 475system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses 476system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses 477system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses 478system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses 479system.cpu.icache.overall_misses::total 446 # number of overall misses 480system.cpu.icache.ReadReq_miss_latency::cpu.inst 22343000 # number of ReadReq miss cycles 481system.cpu.icache.ReadReq_miss_latency::total 22343000 # number of ReadReq miss cycles 482system.cpu.icache.demand_miss_latency::cpu.inst 22343000 # number of demand (read+write) miss cycles 483system.cpu.icache.demand_miss_latency::total 22343000 # number of demand (read+write) miss cycles 484system.cpu.icache.overall_miss_latency::cpu.inst 22343000 # number of overall miss cycles 485system.cpu.icache.overall_miss_latency::total 22343000 # number of overall miss cycles 486system.cpu.icache.ReadReq_accesses::cpu.inst 2012 # number of ReadReq accesses(hits+misses) 487system.cpu.icache.ReadReq_accesses::total 2012 # number of ReadReq accesses(hits+misses) 488system.cpu.icache.demand_accesses::cpu.inst 2012 # number of demand (read+write) accesses 489system.cpu.icache.demand_accesses::total 2012 # number of demand (read+write) accesses 490system.cpu.icache.overall_accesses::cpu.inst 2012 # number of overall (read+write) accesses 491system.cpu.icache.overall_accesses::total 2012 # number of overall (read+write) accesses 492system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221670 # miss rate for ReadReq accesses 493system.cpu.icache.ReadReq_miss_rate::total 0.221670 # miss rate for ReadReq accesses 494system.cpu.icache.demand_miss_rate::cpu.inst 0.221670 # miss rate for demand accesses 495system.cpu.icache.demand_miss_rate::total 0.221670 # miss rate for demand accesses 496system.cpu.icache.overall_miss_rate::cpu.inst 0.221670 # miss rate for overall accesses 497system.cpu.icache.overall_miss_rate::total 0.221670 # miss rate for overall accesses 498system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 50096.412556 # average ReadReq miss latency 499system.cpu.icache.ReadReq_avg_miss_latency::total 50096.412556 # average ReadReq miss latency 500system.cpu.icache.demand_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency 501system.cpu.icache.demand_avg_miss_latency::total 50096.412556 # average overall miss latency 502system.cpu.icache.overall_avg_miss_latency::cpu.inst 50096.412556 # average overall miss latency 503system.cpu.icache.overall_avg_miss_latency::total 50096.412556 # average overall miss latency 504system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked | 518system.cpu.icache.occ_blocks::cpu.inst 161.130962 # Average occupied blocks per requestor 519system.cpu.icache.occ_percent::cpu.inst 0.078677 # Average percentage of cache occupancy 520system.cpu.icache.occ_percent::total 0.078677 # Average percentage of cache occupancy 521system.cpu.icache.ReadReq_hits::cpu.inst 1541 # number of ReadReq hits 522system.cpu.icache.ReadReq_hits::total 1541 # number of ReadReq hits 523system.cpu.icache.demand_hits::cpu.inst 1541 # number of demand (read+write) hits 524system.cpu.icache.demand_hits::total 1541 # number of demand (read+write) hits 525system.cpu.icache.overall_hits::cpu.inst 1541 # number of overall hits 526system.cpu.icache.overall_hits::total 1541 # number of overall hits 527system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses 528system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses 529system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses 530system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses 531system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses 532system.cpu.icache.overall_misses::total 453 # number of overall misses 533system.cpu.icache.ReadReq_miss_latency::cpu.inst 30806000 # number of ReadReq miss cycles 534system.cpu.icache.ReadReq_miss_latency::total 30806000 # number of ReadReq miss cycles 535system.cpu.icache.demand_miss_latency::cpu.inst 30806000 # number of demand (read+write) miss cycles 536system.cpu.icache.demand_miss_latency::total 30806000 # number of demand (read+write) miss cycles 537system.cpu.icache.overall_miss_latency::cpu.inst 30806000 # number of overall miss cycles 538system.cpu.icache.overall_miss_latency::total 30806000 # number of overall miss cycles 539system.cpu.icache.ReadReq_accesses::cpu.inst 1994 # number of ReadReq accesses(hits+misses) 540system.cpu.icache.ReadReq_accesses::total 1994 # number of ReadReq accesses(hits+misses) 541system.cpu.icache.demand_accesses::cpu.inst 1994 # number of demand (read+write) accesses 542system.cpu.icache.demand_accesses::total 1994 # number of demand (read+write) accesses 543system.cpu.icache.overall_accesses::cpu.inst 1994 # number of overall (read+write) accesses 544system.cpu.icache.overall_accesses::total 1994 # number of overall (read+write) accesses 545system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.227182 # miss rate for ReadReq accesses 546system.cpu.icache.ReadReq_miss_rate::total 0.227182 # miss rate for ReadReq accesses 547system.cpu.icache.demand_miss_rate::cpu.inst 0.227182 # miss rate for demand accesses 548system.cpu.icache.demand_miss_rate::total 0.227182 # miss rate for demand accesses 549system.cpu.icache.overall_miss_rate::cpu.inst 0.227182 # miss rate for overall accesses 550system.cpu.icache.overall_miss_rate::total 0.227182 # miss rate for overall accesses 551system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 68004.415011 # average ReadReq miss latency 552system.cpu.icache.ReadReq_avg_miss_latency::total 68004.415011 # average ReadReq miss latency 553system.cpu.icache.demand_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency 554system.cpu.icache.demand_avg_miss_latency::total 68004.415011 # average overall miss latency 555system.cpu.icache.overall_avg_miss_latency::cpu.inst 68004.415011 # average overall miss latency 556system.cpu.icache.overall_avg_miss_latency::total 68004.415011 # average overall miss latency 557system.cpu.icache.blocked_cycles::no_mshrs 46 # number of cycles access was blocked |
| 505system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 506system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 507system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 558system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 559system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 560system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 508system.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked | 561system.cpu.icache.avg_blocked_cycles::no_mshrs 46 # average number of cycles each access was blocked |
| 509system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 510system.cpu.icache.fast_writes 0 # number of fast writes performed 511system.cpu.icache.cache_copies 0 # number of cache copies performed | 562system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 563system.cpu.icache.fast_writes 0 # number of fast writes performed 564system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 512system.cpu.icache.ReadReq_mshr_hits::cpu.inst 107 # number of ReadReq MSHR hits 513system.cpu.icache.ReadReq_mshr_hits::total 107 # number of ReadReq MSHR hits 514system.cpu.icache.demand_mshr_hits::cpu.inst 107 # number of demand (read+write) MSHR hits 515system.cpu.icache.demand_mshr_hits::total 107 # number of demand (read+write) MSHR hits 516system.cpu.icache.overall_mshr_hits::cpu.inst 107 # number of overall MSHR hits 517system.cpu.icache.overall_mshr_hits::total 107 # number of overall MSHR hits | 565system.cpu.icache.ReadReq_mshr_hits::cpu.inst 114 # number of ReadReq MSHR hits 566system.cpu.icache.ReadReq_mshr_hits::total 114 # number of ReadReq MSHR hits 567system.cpu.icache.demand_mshr_hits::cpu.inst 114 # number of demand (read+write) MSHR hits 568system.cpu.icache.demand_mshr_hits::total 114 # number of demand (read+write) MSHR hits 569system.cpu.icache.overall_mshr_hits::cpu.inst 114 # number of overall MSHR hits 570system.cpu.icache.overall_mshr_hits::total 114 # number of overall MSHR hits |
| 518system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 519system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 520system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 521system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses 522system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 523system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses | 571system.cpu.icache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses 572system.cpu.icache.ReadReq_mshr_misses::total 339 # number of ReadReq MSHR misses 573system.cpu.icache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses 574system.cpu.icache.demand_mshr_misses::total 339 # number of demand (read+write) MSHR misses 575system.cpu.icache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses 576system.cpu.icache.overall_mshr_misses::total 339 # number of overall MSHR misses |
| 524system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17808000 # number of ReadReq MSHR miss cycles 525system.cpu.icache.ReadReq_mshr_miss_latency::total 17808000 # number of ReadReq MSHR miss cycles 526system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17808000 # number of demand (read+write) MSHR miss cycles 527system.cpu.icache.demand_mshr_miss_latency::total 17808000 # number of demand (read+write) MSHR miss cycles 528system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17808000 # number of overall MSHR miss cycles 529system.cpu.icache.overall_mshr_miss_latency::total 17808000 # number of overall MSHR miss cycles 530system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168489 # mshr miss rate for ReadReq accesses 531system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168489 # mshr miss rate for ReadReq accesses 532system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168489 # mshr miss rate for demand accesses 533system.cpu.icache.demand_mshr_miss_rate::total 0.168489 # mshr miss rate for demand accesses 534system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168489 # mshr miss rate for overall accesses 535system.cpu.icache.overall_mshr_miss_rate::total 0.168489 # mshr miss rate for overall accesses 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52530.973451 # average ReadReq mshr miss latency 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52530.973451 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52530.973451 # average overall mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::total 52530.973451 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52530.973451 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total 52530.973451 # average overall mshr miss latency | 577system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 23945500 # number of ReadReq MSHR miss cycles 578system.cpu.icache.ReadReq_mshr_miss_latency::total 23945500 # number of ReadReq MSHR miss cycles 579system.cpu.icache.demand_mshr_miss_latency::cpu.inst 23945500 # number of demand (read+write) MSHR miss cycles 580system.cpu.icache.demand_mshr_miss_latency::total 23945500 # number of demand (read+write) MSHR miss cycles 581system.cpu.icache.overall_mshr_miss_latency::cpu.inst 23945500 # number of overall MSHR miss cycles 582system.cpu.icache.overall_mshr_miss_latency::total 23945500 # number of overall MSHR miss cycles 583system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for ReadReq accesses 584system.cpu.icache.ReadReq_mshr_miss_rate::total 0.170010 # mshr miss rate for ReadReq accesses 585system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for demand accesses 586system.cpu.icache.demand_mshr_miss_rate::total 0.170010 # mshr miss rate for demand accesses 587system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.170010 # mshr miss rate for overall accesses 588system.cpu.icache.overall_mshr_miss_rate::total 0.170010 # mshr miss rate for overall accesses 589system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 70635.693215 # average ReadReq mshr miss latency 590system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 70635.693215 # average ReadReq mshr miss latency 591system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency 592system.cpu.icache.demand_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency 593system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 70635.693215 # average overall mshr miss latency 594system.cpu.icache.overall_avg_mshr_miss_latency::total 70635.693215 # average overall mshr miss latency |
| 542system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 543system.cpu.l2cache.replacements 0 # number of replacements | 595system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 596system.cpu.l2cache.replacements 0 # number of replacements |
| 544system.cpu.l2cache.tagsinuse 222.361606 # Cycle average of tags in use | 597system.cpu.l2cache.tagsinuse 221.094003 # Cycle average of tags in use |
| 545system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 546system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. 547system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. 548system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 598system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 599system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. 600system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. 601system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 549system.cpu.l2cache.occ_blocks::cpu.inst 164.584950 # Average occupied blocks per requestor 550system.cpu.l2cache.occ_blocks::cpu.data 57.776656 # Average occupied blocks per requestor 551system.cpu.l2cache.occ_percent::cpu.inst 0.005023 # Average percentage of cache occupancy 552system.cpu.l2cache.occ_percent::cpu.data 0.001763 # Average percentage of cache occupancy 553system.cpu.l2cache.occ_percent::total 0.006786 # Average percentage of cache occupancy | 602system.cpu.l2cache.occ_blocks::cpu.inst 163.410737 # Average occupied blocks per requestor 603system.cpu.l2cache.occ_blocks::cpu.data 57.683266 # Average occupied blocks per requestor 604system.cpu.l2cache.occ_percent::cpu.inst 0.004987 # Average percentage of cache occupancy 605system.cpu.l2cache.occ_percent::cpu.data 0.001760 # Average percentage of cache occupancy 606system.cpu.l2cache.occ_percent::total 0.006747 # Average percentage of cache occupancy |
| 554system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 555system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 556system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 559system.cpu.l2cache.overall_hits::total 3 # number of overall hits 560system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses 561system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 562system.cpu.l2cache.ReadReq_misses::total 427 # number of ReadReq misses 563system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 564system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 565system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses 566system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 567system.cpu.l2cache.demand_misses::total 478 # number of demand (read+write) misses 568system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses 569system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 570system.cpu.l2cache.overall_misses::total 478 # number of overall misses | 607system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 608system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 609system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 610system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 611system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 612system.cpu.l2cache.overall_hits::total 3 # number of overall hits 613system.cpu.l2cache.ReadReq_misses::cpu.inst 336 # number of ReadReq misses 614system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses 615system.cpu.l2cache.ReadReq_misses::total 427 # number of ReadReq misses 616system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 617system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 618system.cpu.l2cache.demand_misses::cpu.inst 336 # number of demand (read+write) misses 619system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 620system.cpu.l2cache.demand_misses::total 478 # number of demand (read+write) misses 621system.cpu.l2cache.overall_misses::cpu.inst 336 # number of overall misses 622system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 623system.cpu.l2cache.overall_misses::total 478 # number of overall misses |
| 571system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 17438500 # number of ReadReq miss cycles 572system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5913000 # number of ReadReq miss cycles 573system.cpu.l2cache.ReadReq_miss_latency::total 23351500 # number of ReadReq miss cycles 574system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2657000 # number of ReadExReq miss cycles 575system.cpu.l2cache.ReadExReq_miss_latency::total 2657000 # number of ReadExReq miss cycles 576system.cpu.l2cache.demand_miss_latency::cpu.inst 17438500 # number of demand (read+write) miss cycles 577system.cpu.l2cache.demand_miss_latency::cpu.data 8570000 # number of demand (read+write) miss cycles 578system.cpu.l2cache.demand_miss_latency::total 26008500 # number of demand (read+write) miss cycles 579system.cpu.l2cache.overall_miss_latency::cpu.inst 17438500 # number of overall miss cycles 580system.cpu.l2cache.overall_miss_latency::cpu.data 8570000 # number of overall miss cycles 581system.cpu.l2cache.overall_miss_latency::total 26008500 # number of overall miss cycles | 624system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23576500 # number of ReadReq miss cycles 625system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7069500 # number of ReadReq miss cycles 626system.cpu.l2cache.ReadReq_miss_latency::total 30646000 # number of ReadReq miss cycles 627system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3844000 # number of ReadExReq miss cycles 628system.cpu.l2cache.ReadExReq_miss_latency::total 3844000 # number of ReadExReq miss cycles 629system.cpu.l2cache.demand_miss_latency::cpu.inst 23576500 # number of demand (read+write) miss cycles 630system.cpu.l2cache.demand_miss_latency::cpu.data 10913500 # number of demand (read+write) miss cycles 631system.cpu.l2cache.demand_miss_latency::total 34490000 # number of demand (read+write) miss cycles 632system.cpu.l2cache.overall_miss_latency::cpu.inst 23576500 # number of overall miss cycles 633system.cpu.l2cache.overall_miss_latency::cpu.data 10913500 # number of overall miss cycles 634system.cpu.l2cache.overall_miss_latency::total 34490000 # number of overall miss cycles |
| 582system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) 583system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 584system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) 585system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 586system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 587system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses 588system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 589system.cpu.l2cache.demand_accesses::total 481 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 596system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 597system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 598system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991150 # miss rate for demand accesses 599system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 600system.cpu.l2cache.demand_miss_rate::total 0.993763 # miss rate for demand accesses 601system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses 602system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 603system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses | 635system.cpu.l2cache.ReadReq_accesses::cpu.inst 339 # number of ReadReq accesses(hits+misses) 636system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 637system.cpu.l2cache.ReadReq_accesses::total 430 # number of ReadReq accesses(hits+misses) 638system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 639system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 640system.cpu.l2cache.demand_accesses::cpu.inst 339 # number of demand (read+write) accesses 641system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 642system.cpu.l2cache.demand_accesses::total 481 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 649system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 650system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 651system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991150 # miss rate for demand accesses 652system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 653system.cpu.l2cache.demand_miss_rate::total 0.993763 # miss rate for demand accesses 654system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991150 # miss rate for overall accesses 655system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 656system.cpu.l2cache.overall_miss_rate::total 0.993763 # miss rate for overall accesses |
| 604system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 51900.297619 # average ReadReq miss latency 605system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 64978.021978 # average ReadReq miss latency 606system.cpu.l2cache.ReadReq_avg_miss_latency::total 54687.353630 # average ReadReq miss latency 607system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52098.039216 # average ReadExReq miss latency 608system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52098.039216 # average ReadExReq miss latency 609system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency 610system.cpu.l2cache.demand_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency 611system.cpu.l2cache.demand_avg_miss_latency::total 54411.087866 # average overall miss latency 612system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 51900.297619 # average overall miss latency 613system.cpu.l2cache.overall_avg_miss_latency::cpu.data 60352.112676 # average overall miss latency 614system.cpu.l2cache.overall_avg_miss_latency::total 54411.087866 # average overall miss latency | 657system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 70168.154762 # average ReadReq miss latency 658system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77686.813187 # average ReadReq miss latency 659system.cpu.l2cache.ReadReq_avg_miss_latency::total 71770.491803 # average ReadReq miss latency 660system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 75372.549020 # average ReadExReq miss latency 661system.cpu.l2cache.ReadExReq_avg_miss_latency::total 75372.549020 # average ReadExReq miss latency 662system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency 663system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency 664system.cpu.l2cache.demand_avg_miss_latency::total 72154.811715 # average overall miss latency 665system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 70168.154762 # average overall miss latency 666system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76855.633803 # average overall miss latency 667system.cpu.l2cache.overall_avg_miss_latency::total 72154.811715 # average overall miss latency |
| 615system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 616system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 617system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 618system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 619system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 620system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 621system.cpu.l2cache.fast_writes 0 # number of fast writes performed 622system.cpu.l2cache.cache_copies 0 # number of cache copies performed 623system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 624system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 625system.cpu.l2cache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses 626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 627system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 628system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 629system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 630system.cpu.l2cache.demand_mshr_misses::total 478 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 632system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 633system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses | 668system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 669system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 670system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 671system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 672system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 673system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 674system.cpu.l2cache.fast_writes 0 # number of fast writes performed 675system.cpu.l2cache.cache_copies 0 # number of cache copies performed 676system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 336 # number of ReadReq MSHR misses 677system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 678system.cpu.l2cache.ReadReq_mshr_misses::total 427 # number of ReadReq MSHR misses 679system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 680system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 681system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 682system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 683system.cpu.l2cache.demand_mshr_misses::total 478 # number of demand (read+write) MSHR misses 684system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 685system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 686system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses |
| 634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13259027 # number of ReadReq MSHR miss cycles 635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4798293 # number of ReadReq MSHR miss cycles 636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18057320 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles 638system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles 639system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13259027 # number of demand (read+write) MSHR miss cycles 640system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6830321 # number of demand (read+write) MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::total 20089348 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13259027 # number of overall MSHR miss cycles 643system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6830321 # number of overall MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::total 20089348 # number of overall MSHR miss cycles | 687system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19402750 # number of ReadReq MSHR miss cycles 688system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5959000 # number of ReadReq MSHR miss cycles 689system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25361750 # number of ReadReq MSHR miss cycles 690system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3218500 # number of ReadExReq MSHR miss cycles 691system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3218500 # number of ReadExReq MSHR miss cycles 692system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19402750 # number of demand (read+write) MSHR miss cycles 693system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9177500 # number of demand (read+write) MSHR miss cycles 694system.cpu.l2cache.demand_mshr_miss_latency::total 28580250 # number of demand (read+write) MSHR miss cycles 695system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19402750 # number of overall MSHR miss cycles 696system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9177500 # number of overall MSHR miss cycles 697system.cpu.l2cache.overall_mshr_miss_latency::total 28580250 # number of overall MSHR miss cycles |
| 645system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for demand accesses 651system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 652system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses 653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses 654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 655system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses | 698system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses 699system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 700system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses 701system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 702system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 703system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for demand accesses 704system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 705system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses 706system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses 707system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 708system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses |
| 656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39461.389881 # average ReadReq mshr miss latency 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52728.494505 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42288.805621 # average ReadReq mshr miss latency 659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency 663system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39461.389881 # average overall mshr miss latency 665system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48100.852113 # average overall mshr miss latency 666system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42027.924686 # average overall mshr miss latency | 709system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 57746.279762 # average ReadReq mshr miss latency 710system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65483.516484 # average ReadReq mshr miss latency 711system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59395.199063 # average ReadReq mshr miss latency 712system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 63107.843137 # average ReadExReq mshr miss latency 713system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 63107.843137 # average ReadExReq mshr miss latency 714system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency 715system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency 716system.cpu.l2cache.demand_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency 717system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 57746.279762 # average overall mshr miss latency 718system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64630.281690 # average overall mshr miss latency 719system.cpu.l2cache.overall_avg_mshr_miss_latency::total 59791.317992 # average overall mshr miss latency |
| 667system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 668system.cpu.dcache.replacements 0 # number of replacements | 720system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 721system.cpu.dcache.replacements 0 # number of replacements |
| 669system.cpu.dcache.tagsinuse 91.619831 # Cycle average of tags in use 670system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. | 722system.cpu.dcache.tagsinuse 91.370944 # Cycle average of tags in use 723system.cpu.dcache.total_refs 2400 # Total number of references to valid blocks. |
| 671system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. | 724system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. |
| 672system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. | 725system.cpu.dcache.avg_refs 16.901408 # Average number of references to valid blocks. |
| 673system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 726system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 674system.cpu.dcache.occ_blocks::cpu.data 91.619831 # Average occupied blocks per requestor 675system.cpu.dcache.occ_percent::cpu.data 0.022368 # Average percentage of cache occupancy 676system.cpu.dcache.occ_percent::total 0.022368 # Average percentage of cache occupancy 677system.cpu.dcache.ReadReq_hits::cpu.data 1852 # number of ReadReq hits 678system.cpu.dcache.ReadReq_hits::total 1852 # number of ReadReq hits 679system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits 680system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits 681system.cpu.dcache.demand_hits::cpu.data 2424 # number of demand (read+write) hits 682system.cpu.dcache.demand_hits::total 2424 # number of demand (read+write) hits 683system.cpu.dcache.overall_hits::cpu.data 2424 # number of overall hits 684system.cpu.dcache.overall_hits::total 2424 # number of overall hits 685system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 686system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 687system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses 688system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses 689system.cpu.dcache.demand_misses::cpu.data 501 # number of demand (read+write) misses 690system.cpu.dcache.demand_misses::total 501 # number of demand (read+write) misses 691system.cpu.dcache.overall_misses::cpu.data 501 # number of overall misses 692system.cpu.dcache.overall_misses::total 501 # number of overall misses 693system.cpu.dcache.ReadReq_miss_latency::cpu.data 8995500 # number of ReadReq miss cycles 694system.cpu.dcache.ReadReq_miss_latency::total 8995500 # number of ReadReq miss cycles 695system.cpu.dcache.WriteReq_miss_latency::cpu.data 15098999 # number of WriteReq miss cycles 696system.cpu.dcache.WriteReq_miss_latency::total 15098999 # number of WriteReq miss cycles 697system.cpu.dcache.demand_miss_latency::cpu.data 24094499 # number of demand (read+write) miss cycles 698system.cpu.dcache.demand_miss_latency::total 24094499 # number of demand (read+write) miss cycles 699system.cpu.dcache.overall_miss_latency::cpu.data 24094499 # number of overall miss cycles 700system.cpu.dcache.overall_miss_latency::total 24094499 # number of overall miss cycles 701system.cpu.dcache.ReadReq_accesses::cpu.data 2000 # number of ReadReq accesses(hits+misses) 702system.cpu.dcache.ReadReq_accesses::total 2000 # number of ReadReq accesses(hits+misses) | 727system.cpu.dcache.occ_blocks::cpu.data 91.370944 # Average occupied blocks per requestor 728system.cpu.dcache.occ_percent::cpu.data 0.022307 # Average percentage of cache occupancy 729system.cpu.dcache.occ_percent::total 0.022307 # Average percentage of cache occupancy 730system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits 731system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits 732system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits 733system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits 734system.cpu.dcache.demand_hits::cpu.data 2400 # number of demand (read+write) hits 735system.cpu.dcache.demand_hits::total 2400 # number of demand (read+write) hits 736system.cpu.dcache.overall_hits::cpu.data 2400 # number of overall hits 737system.cpu.dcache.overall_hits::total 2400 # number of overall hits 738system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses 739system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses 740system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 741system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 742system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 743system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 744system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 745system.cpu.dcache.overall_misses::total 511 # number of overall misses 746system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242000 # number of ReadReq miss cycles 747system.cpu.dcache.ReadReq_miss_latency::total 10242000 # number of ReadReq miss cycles 748system.cpu.dcache.WriteReq_miss_latency::cpu.data 22669999 # number of WriteReq miss cycles 749system.cpu.dcache.WriteReq_miss_latency::total 22669999 # number of WriteReq miss cycles 750system.cpu.dcache.demand_miss_latency::cpu.data 32911999 # number of demand (read+write) miss cycles 751system.cpu.dcache.demand_miss_latency::total 32911999 # number of demand (read+write) miss cycles 752system.cpu.dcache.overall_miss_latency::cpu.data 32911999 # number of overall miss cycles 753system.cpu.dcache.overall_miss_latency::total 32911999 # number of overall miss cycles 754system.cpu.dcache.ReadReq_accesses::cpu.data 1986 # number of ReadReq accesses(hits+misses) 755system.cpu.dcache.ReadReq_accesses::total 1986 # number of ReadReq accesses(hits+misses) |
| 703system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 704system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) | 756system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 757system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) |
| 705system.cpu.dcache.demand_accesses::cpu.data 2925 # number of demand (read+write) accesses 706system.cpu.dcache.demand_accesses::total 2925 # number of demand (read+write) accesses 707system.cpu.dcache.overall_accesses::cpu.data 2925 # number of overall (read+write) accesses 708system.cpu.dcache.overall_accesses::total 2925 # number of overall (read+write) accesses 709system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074000 # miss rate for ReadReq accesses 710system.cpu.dcache.ReadReq_miss_rate::total 0.074000 # miss rate for ReadReq accesses 711system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses 712system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses 713system.cpu.dcache.demand_miss_rate::cpu.data 0.171282 # miss rate for demand accesses 714system.cpu.dcache.demand_miss_rate::total 0.171282 # miss rate for demand accesses 715system.cpu.dcache.overall_miss_rate::cpu.data 0.171282 # miss rate for overall accesses 716system.cpu.dcache.overall_miss_rate::total 0.171282 # miss rate for overall accesses 717system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 60780.405405 # average ReadReq miss latency 718system.cpu.dcache.ReadReq_avg_miss_latency::total 60780.405405 # average ReadReq miss latency 719system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 42773.368272 # average WriteReq miss latency 720system.cpu.dcache.WriteReq_avg_miss_latency::total 42773.368272 # average WriteReq miss latency 721system.cpu.dcache.demand_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency 722system.cpu.dcache.demand_avg_miss_latency::total 48092.812375 # average overall miss latency 723system.cpu.dcache.overall_avg_miss_latency::cpu.data 48092.812375 # average overall miss latency 724system.cpu.dcache.overall_avg_miss_latency::total 48092.812375 # average overall miss latency 725system.cpu.dcache.blocked_cycles::no_mshrs 488 # number of cycles access was blocked | 758system.cpu.dcache.demand_accesses::cpu.data 2911 # number of demand (read+write) accesses 759system.cpu.dcache.demand_accesses::total 2911 # number of demand (read+write) accesses 760system.cpu.dcache.overall_accesses::cpu.data 2911 # number of overall (read+write) accesses 761system.cpu.dcache.overall_accesses::total 2911 # number of overall (read+write) accesses 762system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075025 # miss rate for ReadReq accesses 763system.cpu.dcache.ReadReq_miss_rate::total 0.075025 # miss rate for ReadReq accesses 764system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 765system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 766system.cpu.dcache.demand_miss_rate::cpu.data 0.175541 # miss rate for demand accesses 767system.cpu.dcache.demand_miss_rate::total 0.175541 # miss rate for demand accesses 768system.cpu.dcache.overall_miss_rate::cpu.data 0.175541 # miss rate for overall accesses 769system.cpu.dcache.overall_miss_rate::total 0.175541 # miss rate for overall accesses 770system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68738.255034 # average ReadReq miss latency 771system.cpu.dcache.ReadReq_avg_miss_latency::total 68738.255034 # average ReadReq miss latency 772system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62624.306630 # average WriteReq miss latency 773system.cpu.dcache.WriteReq_avg_miss_latency::total 62624.306630 # average WriteReq miss latency 774system.cpu.dcache.demand_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency 775system.cpu.dcache.demand_avg_miss_latency::total 64407.043053 # average overall miss latency 776system.cpu.dcache.overall_avg_miss_latency::cpu.data 64407.043053 # average overall miss latency 777system.cpu.dcache.overall_avg_miss_latency::total 64407.043053 # average overall miss latency 778system.cpu.dcache.blocked_cycles::no_mshrs 642 # number of cycles access was blocked |
| 726system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 727system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 728system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 779system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 780system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 781system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 729system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.363636 # average number of cycles each access was blocked | 782system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.363636 # average number of cycles each access was blocked |
| 730system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 731system.cpu.dcache.fast_writes 0 # number of fast writes performed 732system.cpu.dcache.cache_copies 0 # number of cache copies performed | 783system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 784system.cpu.dcache.fast_writes 0 # number of fast writes performed 785system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 733system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 734system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 735system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits 736system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits 737system.cpu.dcache.demand_mshr_hits::cpu.data 359 # number of demand (read+write) MSHR hits 738system.cpu.dcache.demand_mshr_hits::total 359 # number of demand (read+write) MSHR hits 739system.cpu.dcache.overall_mshr_hits::cpu.data 359 # number of overall MSHR hits 740system.cpu.dcache.overall_mshr_hits::total 359 # number of overall MSHR hits | 786system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits 787system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits 788system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 789system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 790system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits 791system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits 792system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits 793system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits |
| 741system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 742system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 743system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 744system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 745system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 746system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 747system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 748system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 794system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 795system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 796system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 797system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 798system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 799system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 800system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 801system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 749system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 6007500 # number of ReadReq MSHR miss cycles 750system.cpu.dcache.ReadReq_mshr_miss_latency::total 6007500 # number of ReadReq MSHR miss cycles 751system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2708999 # number of WriteReq MSHR miss cycles 752system.cpu.dcache.WriteReq_mshr_miss_latency::total 2708999 # number of WriteReq MSHR miss cycles 753system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8716499 # number of demand (read+write) MSHR miss cycles 754system.cpu.dcache.demand_mshr_miss_latency::total 8716499 # number of demand (read+write) MSHR miss cycles 755system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8716499 # number of overall MSHR miss cycles 756system.cpu.dcache.overall_mshr_miss_latency::total 8716499 # number of overall MSHR miss cycles 757system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045500 # mshr miss rate for ReadReq accesses 758system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045500 # mshr miss rate for ReadReq accesses | 802system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7164000 # number of ReadReq MSHR miss cycles 803system.cpu.dcache.ReadReq_mshr_miss_latency::total 7164000 # number of ReadReq MSHR miss cycles 804system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3895999 # number of WriteReq MSHR miss cycles 805system.cpu.dcache.WriteReq_mshr_miss_latency::total 3895999 # number of WriteReq MSHR miss cycles 806system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11059999 # number of demand (read+write) MSHR miss cycles 807system.cpu.dcache.demand_mshr_miss_latency::total 11059999 # number of demand (read+write) MSHR miss cycles 808system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11059999 # number of overall MSHR miss cycles 809system.cpu.dcache.overall_mshr_miss_latency::total 11059999 # number of overall MSHR miss cycles 810system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045821 # mshr miss rate for ReadReq accesses 811system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045821 # mshr miss rate for ReadReq accesses |
| 759system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 760system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses | 812system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 813system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses |
| 761system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for demand accesses 762system.cpu.dcache.demand_mshr_miss_rate::total 0.048547 # mshr miss rate for demand accesses 763system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048547 # mshr miss rate for overall accesses 764system.cpu.dcache.overall_mshr_miss_rate::total 0.048547 # mshr miss rate for overall accesses 765system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 66016.483516 # average ReadReq mshr miss latency 766system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 66016.483516 # average ReadReq mshr miss latency 767system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53117.627451 # average WriteReq mshr miss latency 768system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53117.627451 # average WriteReq mshr miss latency 769system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency 770system.cpu.dcache.demand_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency 771system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 61383.795775 # average overall mshr miss latency 772system.cpu.dcache.overall_avg_mshr_miss_latency::total 61383.795775 # average overall mshr miss latency | 814system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for demand accesses 815system.cpu.dcache.demand_mshr_miss_rate::total 0.048780 # mshr miss rate for demand accesses 816system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048780 # mshr miss rate for overall accesses 817system.cpu.dcache.overall_mshr_miss_rate::total 0.048780 # mshr miss rate for overall accesses 818system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78725.274725 # average ReadReq mshr miss latency 819system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78725.274725 # average ReadReq mshr miss latency 820system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 76392.137255 # average WriteReq mshr miss latency 821system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 76392.137255 # average WriteReq mshr miss latency 822system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency 823system.cpu.dcache.demand_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency 824system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77887.316901 # average overall mshr miss latency 825system.cpu.dcache.overall_avg_mshr_miss_latency::total 77887.316901 # average overall mshr miss latency |
| 773system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 774 775---------- End Simulation Statistics ---------- | 826system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 827 828---------- End Simulation Statistics ---------- |