Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000016 # Number of seconds simulated
4sim_ticks 16437500 # Number of ticks simulated
5final_tick 16437500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000017 # Number of seconds simulated
4sim_ticks 16532500 # Number of ticks simulated
5final_tick 16532500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 79981 # Simulator instruction rate (inst/s)
8host_op_rate 79951 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 254800448 # Simulator tick rate (ticks/s)
10host_mem_usage 217976 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host

7host_inst_rate 48770 # Simulator instruction rate (inst/s)
8host_op_rate 48763 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 156337427 # Simulator tick rate (ticks/s)
10host_mem_usage 215260 # Number of bytes of host memory used
11host_seconds 0.11 # Real time elapsed on the host

12sim_insts 5156 # Number of instructions simulated
13sim_ops 5156 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 21696 # Number of bytes read from this memory

14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory

15system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory

16system.physmem.bytes_read::total 30720 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21696 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21696 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 339 # Number of read requests responded to by this memory

16system.physmem.bytes_read::total 30464 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory

20system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory

21system.physmem.num_reads::total 480 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1319908745 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 548988593 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1868897338 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1319908745 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1319908745 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1319908745 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 548988593 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1868897338 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 480 # Total number of read requests seen

21system.physmem.num_reads::total 476 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 1296839558 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 545833963 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1842673522 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1296839558 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1296839558 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1296839558 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 545833963 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1842673522 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 476 # Total number of read requests seen

31system.physmem.writeReqs 0 # Total number of write requests seen

32system.physmem.cpureqs 480 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 30720 # Total number of bytes read from memory

32system.physmem.cpureqs 476 # Reqs generatd by CPU via cache - shady
33system.physmem.bytesRead 30464 # Total number of bytes read from memory

34system.physmem.bytesWritten 0 # Total number of bytes written to memory

35system.physmem.bytesConsumedRd 30720 # bytesRead derated as per pkt->getSize()

35system.physmem.bytesConsumedRd 30464 # bytesRead derated as per pkt->getSize()

36system.physmem.bytesConsumedWr 0 # bytesWritten derated as per pkt->getSize()
37system.physmem.servicedByWrQ 0 # Number of read reqs serviced by write Q
38system.physmem.neitherReadNorWrite 0 # Reqs where no action is needed
39system.physmem.perBankRdReqs::0 64 # Track reads on a per bank basis
40system.physmem.perBankRdReqs::1 30 # Track reads on a per bank basis
41system.physmem.perBankRdReqs::2 23 # Track reads on a per bank basis
42system.physmem.perBankRdReqs::3 54 # Track reads on a per bank basis
43system.physmem.perBankRdReqs::4 6 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 39 # Track reads on a per bank basis

44system.physmem.perBankRdReqs::5 38 # Track reads on a per bank basis

45system.physmem.perBankRdReqs::6 0 # Track reads on a per bank basis
46system.physmem.perBankRdReqs::7 20 # Track reads on a per bank basis
47system.physmem.perBankRdReqs::8 40 # Track reads on a per bank basis
48system.physmem.perBankRdReqs::9 18 # Track reads on a per bank basis
49system.physmem.perBankRdReqs::10 15 # Track reads on a per bank basis
50system.physmem.perBankRdReqs::11 17 # Track reads on a per bank basis
51system.physmem.perBankRdReqs::12 40 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::13 52 # Track reads on a per bank basis

52system.physmem.perBankRdReqs::13 50 # Track reads on a per bank basis

53system.physmem.perBankRdReqs::14 32 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::15 30 # Track reads on a per bank basis

54system.physmem.perBankRdReqs::15 29 # Track reads on a per bank basis

55system.physmem.perBankWrReqs::0 0 # Track writes on a per bank basis
56system.physmem.perBankWrReqs::1 0 # Track writes on a per bank basis
57system.physmem.perBankWrReqs::2 0 # Track writes on a per bank basis
58system.physmem.perBankWrReqs::3 0 # Track writes on a per bank basis
59system.physmem.perBankWrReqs::4 0 # Track writes on a per bank basis
60system.physmem.perBankWrReqs::5 0 # Track writes on a per bank basis
61system.physmem.perBankWrReqs::6 0 # Track writes on a per bank basis
62system.physmem.perBankWrReqs::7 0 # Track writes on a per bank basis
63system.physmem.perBankWrReqs::8 0 # Track writes on a per bank basis
64system.physmem.perBankWrReqs::9 0 # Track writes on a per bank basis
65system.physmem.perBankWrReqs::10 0 # Track writes on a per bank basis
66system.physmem.perBankWrReqs::11 0 # Track writes on a per bank basis
67system.physmem.perBankWrReqs::12 0 # Track writes on a per bank basis
68system.physmem.perBankWrReqs::13 0 # Track writes on a per bank basis
69system.physmem.perBankWrReqs::14 0 # Track writes on a per bank basis
70system.physmem.perBankWrReqs::15 0 # Track writes on a per bank basis
71system.physmem.numRdRetry 0 # Number of times rd buffer was full causing retry
72system.physmem.numWrRetry 0 # Number of times wr buffer was full causing retry

73system.physmem.totGap 16357500 # Total gap between requests

73system.physmem.totGap 16452500 # Total gap between requests

74system.physmem.readPktSize::0 0 # Categorize read packet sizes
75system.physmem.readPktSize::1 0 # Categorize read packet sizes
76system.physmem.readPktSize::2 0 # Categorize read packet sizes
77system.physmem.readPktSize::3 0 # Categorize read packet sizes
78system.physmem.readPktSize::4 0 # Categorize read packet sizes
79system.physmem.readPktSize::5 0 # Categorize read packet sizes

80system.physmem.readPktSize::6 480 # Categorize read packet sizes

80system.physmem.readPktSize::6 476 # Categorize read packet sizes

81system.physmem.readPktSize::7 0 # Categorize read packet sizes
82system.physmem.readPktSize::8 0 # Categorize read packet sizes
83system.physmem.writePktSize::0 0 # categorize write packet sizes
84system.physmem.writePktSize::1 0 # categorize write packet sizes
85system.physmem.writePktSize::2 0 # categorize write packet sizes
86system.physmem.writePktSize::3 0 # categorize write packet sizes
87system.physmem.writePktSize::4 0 # categorize write packet sizes
88system.physmem.writePktSize::5 0 # categorize write packet sizes

--- 4 unchanged lines hidden (view full) ---

93system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
94system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
95system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
96system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
97system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
98system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
99system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
100system.physmem.neitherpktsize::8 0 # categorize neither packet sizes

101system.physmem.rdQLenPdf::0 255 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 148 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 51 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 21 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see

101system.physmem.rdQLenPdf::0 257 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::1 144 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::2 49 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see

106system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 45 unchanged lines hidden (view full) ---

159system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see

167system.physmem.totQLat 2266480 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 12950480 # Sum of mem lat for all requests
169system.physmem.totBusLat 1920000 # Total cycles spent in databus access
170system.physmem.totBankLat 8764000 # Total cycles spent in bank access
171system.physmem.avgQLat 4721.83 # Average queueing delay per request
172system.physmem.avgBankLat 18258.33 # Average bank access latency per request

167system.physmem.totQLat 2527972 # Total cycles spent in queuing delays
168system.physmem.totMemAccLat 13083972 # Sum of mem lat for all requests
169system.physmem.totBusLat 1904000 # Total cycles spent in databus access
170system.physmem.totBankLat 8652000 # Total cycles spent in bank access
171system.physmem.avgQLat 5310.87 # Average queueing delay per request
172system.physmem.avgBankLat 18176.47 # Average bank access latency per request

173system.physmem.avgBusLat 4000.00 # Average bus latency per request

174system.physmem.avgMemAccLat 26980.17 # Average memory access latency
175system.physmem.avgRdBW 1868.90 # Average achieved read bandwidth in MB/s

174system.physmem.avgMemAccLat 27487.34 # Average memory access latency
175system.physmem.avgRdBW 1842.67 # Average achieved read bandwidth in MB/s

176system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1868.90 # Average consumed read bandwidth in MB/s

177system.physmem.avgConsumedRdBW 1842.67 # Average consumed read bandwidth in MB/s

178system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s
179system.physmem.peakBW 16000.00 # Theoretical peak bandwidth in MB/s

180system.physmem.busUtil 11.68 # Data bus utilization in percentage

180system.physmem.busUtil 11.52 # Data bus utilization in percentage

181system.physmem.avgRdQLen 0.79 # Average read queue length over time
182system.physmem.avgWrQLen 0.00 # Average write queue length over time

183system.physmem.readRowHits 378 # Number of row buffer hits during reads

183system.physmem.readRowHits 376 # Number of row buffer hits during reads

184system.physmem.writeRowHits 0 # Number of row buffer hits during writes

185system.physmem.readRowHitRate 78.75 # Row buffer hit rate for reads

185system.physmem.readRowHitRate 78.99 # Row buffer hit rate for reads

186system.physmem.writeRowHitRate nan # Row buffer hit rate for writes

187system.physmem.avgGap 34078.12 # Average gap between requests

187system.physmem.avgGap 34564.08 # Average gap between requests

188system.cpu.dtb.read_hits 0 # DTB read hits
189system.cpu.dtb.read_misses 0 # DTB read misses
190system.cpu.dtb.read_accesses 0 # DTB read accesses
191system.cpu.dtb.write_hits 0 # DTB write hits
192system.cpu.dtb.write_misses 0 # DTB write misses
193system.cpu.dtb.write_accesses 0 # DTB write accesses
194system.cpu.dtb.hits 0 # DTB hits
195system.cpu.dtb.misses 0 # DTB misses
196system.cpu.dtb.accesses 0 # DTB accesses
197system.cpu.itb.read_hits 0 # DTB read hits
198system.cpu.itb.read_misses 0 # DTB read misses
199system.cpu.itb.read_accesses 0 # DTB read accesses
200system.cpu.itb.write_hits 0 # DTB write hits
201system.cpu.itb.write_misses 0 # DTB write misses
202system.cpu.itb.write_accesses 0 # DTB write accesses
203system.cpu.itb.hits 0 # DTB hits
204system.cpu.itb.misses 0 # DTB misses
205system.cpu.itb.accesses 0 # DTB accesses
206system.cpu.workload.num_syscalls 8 # Number of system calls

207system.cpu.numCycles 32876 # number of cpu cycles simulated

207system.cpu.numCycles 33066 # number of cpu cycles simulated

208system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
209system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

210system.cpu.BPredUnit.lookups 2145 # Number of BP lookups
211system.cpu.BPredUnit.condPredicted 1420 # Number of conditional branches predicted
212system.cpu.BPredUnit.condIncorrect 444 # Number of conditional branches incorrect
213system.cpu.BPredUnit.BTBLookups 1692 # Number of BTB lookups
214system.cpu.BPredUnit.BTBHits 498 # Number of BTB hits

210system.cpu.BPredUnit.lookups 2120 # Number of BP lookups
211system.cpu.BPredUnit.condPredicted 1453 # Number of conditional branches predicted
212system.cpu.BPredUnit.condIncorrect 419 # Number of conditional branches incorrect
213system.cpu.BPredUnit.BTBLookups 1651 # Number of BTB lookups
214system.cpu.BPredUnit.BTBHits 517 # Number of BTB hits

215system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

216system.cpu.BPredUnit.usedRAS 270 # Number of times the RAS was used to get a target.

216system.cpu.BPredUnit.usedRAS 258 # Number of times the RAS was used to get a target.

217system.cpu.BPredUnit.RASInCorrect 68 # Number of incorrect RAS predictions.

218system.cpu.fetch.icacheStallCycles 8858 # Number of cycles fetch is stalled on an Icache miss
219system.cpu.fetch.Insts 13016 # Number of instructions fetch has processed
220system.cpu.fetch.Branches 2145 # Number of branches that fetch encountered
221system.cpu.fetch.predictedBranches 768 # Number of branches that fetch has predicted taken
222system.cpu.fetch.Cycles 3241 # Number of cycles fetch has run and was not squashing or blocked
223system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
224system.cpu.fetch.BlockedCycles 897 # Number of cycles fetch has spent blocked

218system.cpu.fetch.icacheStallCycles 8641 # Number of cycles fetch is stalled on an Icache miss
219system.cpu.fetch.Insts 12896 # Number of instructions fetch has processed
220system.cpu.fetch.Branches 2120 # Number of branches that fetch encountered
221system.cpu.fetch.predictedBranches 775 # Number of branches that fetch has predicted taken
222system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked
223system.cpu.fetch.SquashCycles 1339 # Number of cycles fetch has spent squashing
224system.cpu.fetch.BlockedCycles 1070 # Number of cycles fetch has spent blocked

225system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
226system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps

227system.cpu.fetch.CacheLines 2015 # Number of cache lines fetched
228system.cpu.fetch.IcacheSquashes 287 # Number of outstanding Icache misses that were squashed
229system.cpu.fetch.rateDist::samples 14043 # Number of instructions fetched each cycle (Total)
230system.cpu.fetch.rateDist::mean 0.926867 # Number of instructions fetched each cycle (Total)
231system.cpu.fetch.rateDist::stdev 2.227706 # Number of instructions fetched each cycle (Total)

227system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched
228system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
229system.cpu.fetch.rateDist::samples 13947 # Number of instructions fetched each cycle (Total)
230system.cpu.fetch.rateDist::mean 0.924643 # Number of instructions fetched each cycle (Total)
231system.cpu.fetch.rateDist::stdev 2.229674 # Number of instructions fetched each cycle (Total)

232system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

233system.cpu.fetch.rateDist::0 10802 76.92% 76.92% # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::1 1358 9.67% 86.59% # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::2 113 0.80% 87.40% # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::3 147 1.05% 88.44% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::4 305 2.17% 90.61% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::5 111 0.79% 91.40% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::6 157 1.12% 92.52% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::7 126 0.90% 93.42% # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::8 924 6.58% 100.00% # Number of instructions fetched each cycle (Total)

233system.cpu.fetch.rateDist::0 10748 77.06% 77.06% # Number of instructions fetched each cycle (Total)
234system.cpu.fetch.rateDist::1 1351 9.69% 86.75% # Number of instructions fetched each cycle (Total)
235system.cpu.fetch.rateDist::2 103 0.74% 87.49% # Number of instructions fetched each cycle (Total)
236system.cpu.fetch.rateDist::3 137 0.98% 88.47% # Number of instructions fetched each cycle (Total)
237system.cpu.fetch.rateDist::4 291 2.09% 90.56% # Number of instructions fetched each cycle (Total)
238system.cpu.fetch.rateDist::5 93 0.67% 91.22% # Number of instructions fetched each cycle (Total)
239system.cpu.fetch.rateDist::6 169 1.21% 92.44% # Number of instructions fetched each cycle (Total)
240system.cpu.fetch.rateDist::7 155 1.11% 93.55% # Number of instructions fetched each cycle (Total)
241system.cpu.fetch.rateDist::8 900 6.45% 100.00% # Number of instructions fetched each cycle (Total)

242system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
243system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
244system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

245system.cpu.fetch.rateDist::total 14043 # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.branchRate 0.065245 # Number of branch fetches per cycle
247system.cpu.fetch.rate 0.395912 # Number of inst fetches per cycle
248system.cpu.decode.IdleCycles 8962 # Number of cycles decode is idle
249system.cpu.decode.BlockedCycles 1117 # Number of cycles decode is blocked
250system.cpu.decode.RunCycles 3062 # Number of cycles decode is running
251system.cpu.decode.UnblockCycles 44 # Number of cycles decode is unblocking
252system.cpu.decode.SquashCycles 858 # Number of cycles decode is squashing
253system.cpu.decode.BranchResolved 165 # Number of times decode resolved a branch
254system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction

245system.cpu.fetch.rateDist::total 13947 # Number of instructions fetched each cycle (Total)
246system.cpu.fetch.branchRate 0.064114 # Number of branch fetches per cycle
247system.cpu.fetch.rate 0.390008 # Number of inst fetches per cycle
248system.cpu.decode.IdleCycles 8777 # Number of cycles decode is idle
249system.cpu.decode.BlockedCycles 1236 # Number of cycles decode is blocked
250system.cpu.decode.RunCycles 3037 # Number of cycles decode is running
251system.cpu.decode.UnblockCycles 46 # Number of cycles decode is unblocking
252system.cpu.decode.SquashCycles 851 # Number of cycles decode is squashing
253system.cpu.decode.BranchResolved 137 # Number of times decode resolved a branch
254system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction

255system.cpu.decode.DecodedInsts 12081 # Number of instructions handled by decode

256system.cpu.decode.SquashedInsts 178 # Number of squashed instructions handled by decode
257system.cpu.rename.SquashCycles 858 # Number of cycles rename is squashing
258system.cpu.rename.IdleCycles 9149 # Number of cycles rename is idle
259system.cpu.rename.BlockCycles 246 # Number of cycles rename is blocking

256system.cpu.decode.SquashedInsts 166 # Number of squashed instructions handled by decode
257system.cpu.rename.SquashCycles 851 # Number of cycles rename is squashing
258system.cpu.rename.IdleCycles 8957 # Number of cycles rename is idle
259system.cpu.rename.BlockCycles 360 # Number of cycles rename is blocking

260system.cpu.rename.serializeStallCycles 762 # count of cycles rename stalled for serializing inst

261system.cpu.rename.RunCycles 2921 # Number of cycles rename is running
262system.cpu.rename.UnblockCycles 107 # Number of cycles rename is unblocking
263system.cpu.rename.RenamedInsts 11564 # Number of instructions processed by rename
264system.cpu.rename.LSQFullEvents 95 # Number of times rename has blocked due to LSQ full
265system.cpu.rename.RenamedOperands 7026 # Number of destination operands rename has renamed
266system.cpu.rename.RenameLookups 13727 # Number of register rename lookups that rename has made
267system.cpu.rename.int_rename_lookups 13723 # Number of integer rename lookups

261system.cpu.rename.RunCycles 2904 # Number of cycles rename is running
262system.cpu.rename.UnblockCycles 113 # Number of cycles rename is unblocking
263system.cpu.rename.RenamedInsts 11654 # Number of instructions processed by rename
264system.cpu.rename.ROBFullEvents 1 # Number of times rename has blocked due to ROB full
265system.cpu.rename.LSQFullEvents 97 # Number of times rename has blocked due to LSQ full
266system.cpu.rename.RenamedOperands 7041 # Number of destination operands rename has renamed
267system.cpu.rename.RenameLookups 13857 # Number of register rename lookups that rename has made
268system.cpu.rename.int_rename_lookups 13853 # Number of integer rename lookups

268system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
269system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed

269system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
270system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed

270system.cpu.rename.UndoneMaps 3628 # Number of HB maps that are undone due to squashing

271system.cpu.rename.UndoneMaps 3643 # Number of HB maps that are undone due to squashing

271system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
272system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed

272system.cpu.rename.serializingInsts 17 # count of serializing insts renamed
273system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed

273system.cpu.rename.skidInsts 273 # count of insts added to the skid buffer
274system.cpu.memDep0.insertedLoads 2438 # Number of loads inserted to the mem dependence unit.
275system.cpu.memDep0.insertedStores 1184 # Number of stores inserted to the mem dependence unit.

274system.cpu.rename.skidInsts 265 # count of insts added to the skid buffer
275system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit.
276system.cpu.memDep0.insertedStores 1198 # Number of stores inserted to the mem dependence unit.

276system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
277system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.

277system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
278system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.

278system.cpu.iq.iqInstsAdded 9022 # Number of instructions added to the IQ (excludes non-spec)

279system.cpu.iq.iqInstsAdded 9172 # Number of instructions added to the IQ (excludes non-spec)

279system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ

280system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ

280system.cpu.iq.iqInstsIssued 8202 # Number of instructions issued
281system.cpu.iq.iqSquashedInstsIssued 45 # Number of squashed instructions issued
282system.cpu.iq.iqSquashedInstsExamined 3390 # Number of squashed instructions iterated over during squash; mainly for profiling
283system.cpu.iq.iqSquashedOperandsExamined 1898 # Number of squashed operands that are examined and possibly removed from graph

281system.cpu.iq.iqInstsIssued 8209 # Number of instructions issued
282system.cpu.iq.iqSquashedInstsIssued 55 # Number of squashed instructions issued
283system.cpu.iq.iqSquashedInstsExamined 3542 # Number of squashed instructions iterated over during squash; mainly for profiling
284system.cpu.iq.iqSquashedOperandsExamined 2140 # Number of squashed operands that are examined and possibly removed from graph

284system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed

285system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed

285system.cpu.iq.issued_per_cycle::samples 14043 # Number of insts issued each cycle
286system.cpu.iq.issued_per_cycle::mean 0.584063 # Number of insts issued each cycle
287system.cpu.iq.issued_per_cycle::stdev 1.245002 # Number of insts issued each cycle

286system.cpu.iq.issued_per_cycle::samples 13947 # Number of insts issued each cycle
287system.cpu.iq.issued_per_cycle::mean 0.588585 # Number of insts issued each cycle
288system.cpu.iq.issued_per_cycle::stdev 1.249847 # Number of insts issued each cycle

288system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

289system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

289system.cpu.iq.issued_per_cycle::0 10483 74.65% 74.65% # Number of insts issued each cycle
290system.cpu.iq.issued_per_cycle::1 1421 10.12% 84.77% # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::2 877 6.25% 91.01% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::3 557 3.97% 94.98% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::4 353 2.51% 97.49% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::5 225 1.60% 99.10% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::6 84 0.60% 99.69% # Number of insts issued each cycle

290system.cpu.iq.issued_per_cycle::0 10394 74.52% 74.52% # Number of insts issued each cycle
291system.cpu.iq.issued_per_cycle::1 1403 10.06% 84.58% # Number of insts issued each cycle
292system.cpu.iq.issued_per_cycle::2 889 6.37% 90.96% # Number of insts issued each cycle
293system.cpu.iq.issued_per_cycle::3 554 3.97% 94.93% # Number of insts issued each cycle
294system.cpu.iq.issued_per_cycle::4 357 2.56% 97.49% # Number of insts issued each cycle
295system.cpu.iq.issued_per_cycle::5 219 1.57% 99.06% # Number of insts issued each cycle
296system.cpu.iq.issued_per_cycle::6 88 0.63% 99.69% # Number of insts issued each cycle

296system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle
297system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
298system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
299system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

297system.cpu.iq.issued_per_cycle::7 29 0.21% 99.90% # Number of insts issued each cycle
298system.cpu.iq.issued_per_cycle::8 14 0.10% 100.00% # Number of insts issued each cycle
299system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
300system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
301system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

301system.cpu.iq.issued_per_cycle::total 14043 # Number of insts issued each cycle

302system.cpu.iq.issued_per_cycle::total 13947 # Number of insts issued each cycle

302system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

303system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

303system.cpu.iq.fu_full::IntAlu 3 1.96% 1.96% # attempts to use FU when none available
304system.cpu.iq.fu_full::IntMult 0 0.00% 1.96% # attempts to use FU when none available
305system.cpu.iq.fu_full::IntDiv 0 0.00% 1.96% # attempts to use FU when none available
306system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.96% # attempts to use FU when none available
307system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.96% # attempts to use FU when none available
308system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.96% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatMult 0 0.00% 1.96% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.96% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
312system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.96% # attempts to use FU when none available
313system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.96% # attempts to use FU when none available
314system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.96% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.96% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.96% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.96% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdMult 0 0.00% 1.96% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.96% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdShift 0 0.00% 1.96% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.96% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.96% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.96% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.96% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.96% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.96% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.96% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.96% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.96% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.96% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.96% # attempts to use FU when none available
332system.cpu.iq.fu_full::MemRead 97 63.40% 65.36% # attempts to use FU when none available
333system.cpu.iq.fu_full::MemWrite 53 34.64% 100.00% # attempts to use FU when none available

304system.cpu.iq.fu_full::IntAlu 6 3.73% 3.73% # attempts to use FU when none available
305system.cpu.iq.fu_full::IntMult 0 0.00% 3.73% # attempts to use FU when none available
306system.cpu.iq.fu_full::IntDiv 0 0.00% 3.73% # attempts to use FU when none available
307system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.73% # attempts to use FU when none available
308system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.73% # attempts to use FU when none available
309system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.73% # attempts to use FU when none available
310system.cpu.iq.fu_full::FloatMult 0 0.00% 3.73% # attempts to use FU when none available
311system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.73% # attempts to use FU when none available
312system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
313system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.73% # attempts to use FU when none available
314system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.73% # attempts to use FU when none available
315system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.73% # attempts to use FU when none available
316system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.73% # attempts to use FU when none available
317system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.73% # attempts to use FU when none available
318system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.73% # attempts to use FU when none available
319system.cpu.iq.fu_full::SimdMult 0 0.00% 3.73% # attempts to use FU when none available
320system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.73% # attempts to use FU when none available
321system.cpu.iq.fu_full::SimdShift 0 0.00% 3.73% # attempts to use FU when none available
322system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.73% # attempts to use FU when none available
323system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.73% # attempts to use FU when none available
324system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.73% # attempts to use FU when none available
325system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.73% # attempts to use FU when none available
326system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.73% # attempts to use FU when none available
327system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.73% # attempts to use FU when none available
328system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.73% # attempts to use FU when none available
329system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.73% # attempts to use FU when none available
330system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.73% # attempts to use FU when none available
331system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.73% # attempts to use FU when none available
332system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.73% # attempts to use FU when none available
333system.cpu.iq.fu_full::MemRead 100 62.11% 65.84% # attempts to use FU when none available
334system.cpu.iq.fu_full::MemWrite 55 34.16% 100.00% # attempts to use FU when none available

334system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
335system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
336system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

335system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
336system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
337system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

337system.cpu.iq.FU_type_0::IntAlu 4842 59.03% 59.03% # Type of FU issued
338system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.10% # Type of FU issued
339system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.12% # Type of FU issued
340system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.14% # Type of FU issued
341system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.14% # Type of FU issued
342system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.14% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.14% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.14% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.14% # Type of FU issued
346system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.14% # Type of FU issued
347system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.14% # Type of FU issued
348system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.14% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.14% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.14% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.14% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.14% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.14% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.14% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.14% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.14% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.14% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.14% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.14% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.14% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.14% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.14% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.14% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.14% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.14% # Type of FU issued
366system.cpu.iq.FU_type_0::MemRead 2249 27.42% 86.56% # Type of FU issued
367system.cpu.iq.FU_type_0::MemWrite 1102 13.44% 100.00% # Type of FU issued

338system.cpu.iq.FU_type_0::IntAlu 4835 58.90% 58.90% # Type of FU issued
339system.cpu.iq.FU_type_0::IntMult 5 0.06% 58.96% # Type of FU issued
340system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.98% # Type of FU issued
341system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.01% # Type of FU issued
342system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.01% # Type of FU issued
343system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.01% # Type of FU issued
344system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.01% # Type of FU issued
345system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.01% # Type of FU issued
346system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.01% # Type of FU issued
347system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.01% # Type of FU issued
348system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.01% # Type of FU issued
349system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.01% # Type of FU issued
350system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.01% # Type of FU issued
351system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.01% # Type of FU issued
352system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.01% # Type of FU issued
353system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.01% # Type of FU issued
354system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.01% # Type of FU issued
355system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.01% # Type of FU issued
356system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.01% # Type of FU issued
357system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.01% # Type of FU issued
358system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.01% # Type of FU issued
359system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.01% # Type of FU issued
360system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.01% # Type of FU issued
361system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.01% # Type of FU issued
362system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.01% # Type of FU issued
363system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.01% # Type of FU issued
364system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.01% # Type of FU issued
365system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.01% # Type of FU issued
366system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.01% # Type of FU issued
367system.cpu.iq.FU_type_0::MemRead 2260 27.53% 86.54% # Type of FU issued
368system.cpu.iq.FU_type_0::MemWrite 1105 13.46% 100.00% # Type of FU issued

368system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
369system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

369system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
370system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

370system.cpu.iq.FU_type_0::total 8202 # Type of FU issued
371system.cpu.iq.rate 0.249483 # Inst issue rate
372system.cpu.iq.fu_busy_cnt 153 # FU busy when requested
373system.cpu.iq.fu_busy_rate 0.018654 # FU busy rate (busy events/executed inst)
374system.cpu.iq.int_inst_queue_reads 30641 # Number of integer instruction queue reads
375system.cpu.iq.int_inst_queue_writes 12433 # Number of integer instruction queue writes
376system.cpu.iq.int_inst_queue_wakeup_accesses 7364 # Number of integer instruction queue wakeup accesses

371system.cpu.iq.FU_type_0::total 8209 # Type of FU issued
372system.cpu.iq.rate 0.248261 # Inst issue rate
373system.cpu.iq.fu_busy_cnt 161 # FU busy when requested
374system.cpu.iq.fu_busy_rate 0.019613 # FU busy rate (busy events/executed inst)
375system.cpu.iq.int_inst_queue_reads 30577 # Number of integer instruction queue reads
376system.cpu.iq.int_inst_queue_writes 12735 # Number of integer instruction queue writes
377system.cpu.iq.int_inst_queue_wakeup_accesses 7402 # Number of integer instruction queue wakeup accesses

377system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
378system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
379system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses

378system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
379system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
380system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses

380system.cpu.iq.int_alu_accesses 8353 # Number of integer alu accesses

381system.cpu.iq.int_alu_accesses 8368 # Number of integer alu accesses

381system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses

382system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses

382system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores

383system.cpu.iew.lsq.thread0.forwLoads 67 # Number of loads that had data forwarded from stores

383system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

384system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

384system.cpu.iew.lsq.thread0.squashedLoads 1275 # Number of loads squashed

385system.cpu.iew.lsq.thread0.squashedLoads 1313 # Number of loads squashed

385system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
386system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations

386system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
387system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations

387system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed

388system.cpu.iew.lsq.thread0.squashedStores 273 # Number of stores squashed

388system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
389system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
390system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled

389system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
390system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
391system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled

391system.cpu.iew.lsq.thread0.cacheBlocked 38 # Number of times an access to memory failed due to the cache being blocked

392system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked

392system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

393system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

393system.cpu.iew.iewSquashCycles 858 # Number of cycles IEW is squashing
394system.cpu.iew.iewBlockCycles 190 # Number of cycles IEW is blocking
395system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
396system.cpu.iew.iewDispatchedInsts 10500 # Number of instructions dispatched to IQ
397system.cpu.iew.iewDispSquashedInsts 111 # Number of squashed instructions skipped by dispatch
398system.cpu.iew.iewDispLoadInsts 2438 # Number of dispatched load instructions
399system.cpu.iew.iewDispStoreInsts 1184 # Number of dispatched store instructions

394system.cpu.iew.iewSquashCycles 851 # Number of cycles IEW is squashing
395system.cpu.iew.iewBlockCycles 242 # Number of cycles IEW is blocking
396system.cpu.iew.iewUnblockCycles 12 # Number of cycles IEW is unblocking
397system.cpu.iew.iewDispatchedInsts 10697 # Number of instructions dispatched to IQ
398system.cpu.iew.iewDispSquashedInsts 120 # Number of squashed instructions skipped by dispatch
399system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions
400system.cpu.iew.iewDispStoreInsts 1198 # Number of dispatched store instructions

400system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions

401system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions

401system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall

402system.cpu.iew.iewIQFullEvents 4 # Number of times the IQ has become full, causing a stall

402system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
403system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations

403system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
404system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations

404system.cpu.iew.predictedTakenIncorrect 108 # Number of branches that were predicted taken incorrectly
405system.cpu.iew.predictedNotTakenIncorrect 363 # Number of branches that were predicted not taken incorrectly
406system.cpu.iew.branchMispredicts 471 # Number of branch mispredicts detected at execute
407system.cpu.iew.iewExecutedInsts 7830 # Number of executed instructions
408system.cpu.iew.iewExecLoadInsts 2115 # Number of load instructions executed
409system.cpu.iew.iewExecSquashedInsts 372 # Number of squashed instructions skipped in execute

405system.cpu.iew.predictedTakenIncorrect 103 # Number of branches that were predicted taken incorrectly
406system.cpu.iew.predictedNotTakenIncorrect 330 # Number of branches that were predicted not taken incorrectly
407system.cpu.iew.branchMispredicts 433 # Number of branch mispredicts detected at execute
408system.cpu.iew.iewExecutedInsts 7849 # Number of executed instructions
409system.cpu.iew.iewExecLoadInsts 2119 # Number of load instructions executed
410system.cpu.iew.iewExecSquashedInsts 360 # Number of squashed instructions skipped in execute

410system.cpu.iew.exec_swp 0 # number of swp insts executed

411system.cpu.iew.exec_swp 0 # number of swp insts executed

411system.cpu.iew.exec_nop 1465 # number of nop insts executed
412system.cpu.iew.exec_refs 3191 # number of memory reference insts executed
413system.cpu.iew.exec_branches 1342 # Number of branches executed
414system.cpu.iew.exec_stores 1076 # Number of stores executed
415system.cpu.iew.exec_rate 0.238168 # Inst execution rate
416system.cpu.iew.wb_sent 7455 # cumulative count of insts sent to commit
417system.cpu.iew.wb_count 7366 # cumulative count of insts written-back
418system.cpu.iew.wb_producers 2870 # num instructions producing a value
419system.cpu.iew.wb_consumers 4099 # num instructions consuming a value

412system.cpu.iew.exec_nop 1512 # number of nop insts executed
413system.cpu.iew.exec_refs 3196 # number of memory reference insts executed
414system.cpu.iew.exec_branches 1341 # Number of branches executed
415system.cpu.iew.exec_stores 1077 # Number of stores executed
416system.cpu.iew.exec_rate 0.237374 # Inst execution rate
417system.cpu.iew.wb_sent 7488 # cumulative count of insts sent to commit
418system.cpu.iew.wb_count 7404 # cumulative count of insts written-back
419system.cpu.iew.wb_producers 2925 # num instructions producing a value
420system.cpu.iew.wb_consumers 4228 # num instructions consuming a value

420system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

421system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

421system.cpu.iew.wb_rate 0.224054 # insts written-back per cycle
422system.cpu.iew.wb_fanout 0.700171 # average fanout of values written-back

422system.cpu.iew.wb_rate 0.223916 # insts written-back per cycle
423system.cpu.iew.wb_fanout 0.691816 # average fanout of values written-back

423system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

424system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ

424system.cpu.commit.commitSquashedInsts 4679 # The number of squashed insts skipped by commit

425system.cpu.commit.commitSquashedInsts 4876 # The number of squashed insts skipped by commit

425system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards

426system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards

426system.cpu.commit.branchMispredicts 399 # The number of times a branch was mispredicted
427system.cpu.commit.committed_per_cycle::samples 13185 # Number of insts commited each cycle
428system.cpu.commit.committed_per_cycle::mean 0.440880 # Number of insts commited each cycle
429system.cpu.commit.committed_per_cycle::stdev 1.228954 # Number of insts commited each cycle

427system.cpu.commit.branchMispredicts 377 # The number of times a branch was mispredicted
428system.cpu.commit.committed_per_cycle::samples 13096 # Number of insts commited each cycle
429system.cpu.commit.committed_per_cycle::mean 0.443876 # Number of insts commited each cycle
430system.cpu.commit.committed_per_cycle::stdev 1.229358 # Number of insts commited each cycle

430system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

431system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

431system.cpu.commit.committed_per_cycle::0 10802 81.93% 81.93% # Number of insts commited each cycle
432system.cpu.commit.committed_per_cycle::1 977 7.41% 89.34% # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::2 629 4.77% 94.11% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::3 318 2.41% 96.52% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::4 150 1.14% 97.66% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::5 86 0.65% 98.31% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::6 74 0.56% 98.87% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::7 42 0.32% 99.19% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::8 107 0.81% 100.00% # Number of insts commited each cycle

432system.cpu.commit.committed_per_cycle::0 10722 81.87% 81.87% # Number of insts commited each cycle
433system.cpu.commit.committed_per_cycle::1 944 7.21% 89.08% # Number of insts commited each cycle
434system.cpu.commit.committed_per_cycle::2 654 4.99% 94.07% # Number of insts commited each cycle
435system.cpu.commit.committed_per_cycle::3 320 2.44% 96.52% # Number of insts commited each cycle
436system.cpu.commit.committed_per_cycle::4 142 1.08% 97.60% # Number of insts commited each cycle
437system.cpu.commit.committed_per_cycle::5 103 0.79% 98.39% # Number of insts commited each cycle
438system.cpu.commit.committed_per_cycle::6 65 0.50% 98.89% # Number of insts commited each cycle
439system.cpu.commit.committed_per_cycle::7 40 0.31% 99.19% # Number of insts commited each cycle
440system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle

440system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
441system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

441system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
442system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
443system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

443system.cpu.commit.committed_per_cycle::total 13185 # Number of insts commited each cycle

444system.cpu.commit.committed_per_cycle::total 13096 # Number of insts commited each cycle

444system.cpu.commit.committedInsts 5813 # Number of instructions committed
445system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
446system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
447system.cpu.commit.refs 2088 # Number of memory references committed
448system.cpu.commit.loads 1163 # Number of loads committed
449system.cpu.commit.membars 0 # Number of memory barriers committed
450system.cpu.commit.branches 915 # Number of branches committed
451system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
452system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
453system.cpu.commit.function_calls 87 # Number of function calls committed.

445system.cpu.commit.committedInsts 5813 # Number of instructions committed
446system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
447system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
448system.cpu.commit.refs 2088 # Number of memory references committed
449system.cpu.commit.loads 1163 # Number of loads committed
450system.cpu.commit.membars 0 # Number of memory barriers committed
451system.cpu.commit.branches 915 # Number of branches committed
452system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
453system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
454system.cpu.commit.function_calls 87 # Number of function calls committed.

454system.cpu.commit.bw_lim_events 107 # number cycles where commit BW limit reached

455system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached

455system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

456system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

456system.cpu.rob.rob_reads 23557 # The number of ROB reads
457system.cpu.rob.rob_writes 21850 # The number of ROB writes

457system.cpu.rob.rob_reads 23666 # The number of ROB reads
458system.cpu.rob.rob_writes 22238 # The number of ROB writes

458system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself

459system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself

459system.cpu.idleCycles 18833 # Total number of cycles that the CPU has spent unscheduled due to idling

460system.cpu.idleCycles 19119 # Total number of cycles that the CPU has spent unscheduled due to idling

460system.cpu.committedInsts 5156 # Number of Instructions Simulated
461system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
462system.cpu.committedInsts_total 5156 # Number of Instructions Simulated

461system.cpu.committedInsts 5156 # Number of Instructions Simulated
462system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
463system.cpu.committedInsts_total 5156 # Number of Instructions Simulated

463system.cpu.cpi 6.376261 # CPI: Cycles Per Instruction
464system.cpu.cpi_total 6.376261 # CPI: Total CPI of All Threads
465system.cpu.ipc 0.156832 # IPC: Instructions Per Cycle
466system.cpu.ipc_total 0.156832 # IPC: Total IPC of All Threads
467system.cpu.int_regfile_reads 10643 # number of integer regfile reads
468system.cpu.int_regfile_writes 5150 # number of integer regfile writes

464system.cpu.cpi 6.413111 # CPI: Cycles Per Instruction
465system.cpu.cpi_total 6.413111 # CPI: Total CPI of All Threads
466system.cpu.ipc 0.155931 # IPC: Instructions Per Cycle
467system.cpu.ipc_total 0.155931 # IPC: Total IPC of All Threads
468system.cpu.int_regfile_reads 10670 # number of integer regfile reads
469system.cpu.int_regfile_writes 5185 # number of integer regfile writes

469system.cpu.fp_regfile_reads 3 # number of floating regfile reads
470system.cpu.fp_regfile_writes 1 # number of floating regfile writes

470system.cpu.fp_regfile_reads 3 # number of floating regfile reads
471system.cpu.fp_regfile_writes 1 # number of floating regfile writes

471system.cpu.misc_regfile_reads 154 # number of misc regfile reads

472system.cpu.misc_regfile_reads 147 # number of misc regfile reads

472system.cpu.icache.replacements 17 # number of replacements

473system.cpu.icache.replacements 17 # number of replacements

473system.cpu.icache.tagsinuse 164.359097 # Cycle average of tags in use
474system.cpu.icache.total_refs 1560 # Total number of references to valid blocks.
475system.cpu.icache.sampled_refs 342 # Sample count of references to valid blocks.
476system.cpu.icache.avg_refs 4.561404 # Average number of references to valid blocks.

474system.cpu.icache.tagsinuse 163.149412 # Cycle average of tags in use
475system.cpu.icache.total_refs 1502 # Total number of references to valid blocks.
476system.cpu.icache.sampled_refs 338 # Sample count of references to valid blocks.
477system.cpu.icache.avg_refs 4.443787 # Average number of references to valid blocks.

477system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

478system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

478system.cpu.icache.occ_blocks::cpu.inst 164.359097 # Average occupied blocks per requestor
479system.cpu.icache.occ_percent::cpu.inst 0.080253 # Average percentage of cache occupancy
480system.cpu.icache.occ_percent::total 0.080253 # Average percentage of cache occupancy
481system.cpu.icache.ReadReq_hits::cpu.inst 1560 # number of ReadReq hits
482system.cpu.icache.ReadReq_hits::total 1560 # number of ReadReq hits
483system.cpu.icache.demand_hits::cpu.inst 1560 # number of demand (read+write) hits
484system.cpu.icache.demand_hits::total 1560 # number of demand (read+write) hits
485system.cpu.icache.overall_hits::cpu.inst 1560 # number of overall hits
486system.cpu.icache.overall_hits::total 1560 # number of overall hits
487system.cpu.icache.ReadReq_misses::cpu.inst 455 # number of ReadReq misses
488system.cpu.icache.ReadReq_misses::total 455 # number of ReadReq misses
489system.cpu.icache.demand_misses::cpu.inst 455 # number of demand (read+write) misses
490system.cpu.icache.demand_misses::total 455 # number of demand (read+write) misses
491system.cpu.icache.overall_misses::cpu.inst 455 # number of overall misses
492system.cpu.icache.overall_misses::total 455 # number of overall misses
493system.cpu.icache.ReadReq_miss_latency::cpu.inst 21541500 # number of ReadReq miss cycles
494system.cpu.icache.ReadReq_miss_latency::total 21541500 # number of ReadReq miss cycles
495system.cpu.icache.demand_miss_latency::cpu.inst 21541500 # number of demand (read+write) miss cycles
496system.cpu.icache.demand_miss_latency::total 21541500 # number of demand (read+write) miss cycles
497system.cpu.icache.overall_miss_latency::cpu.inst 21541500 # number of overall miss cycles
498system.cpu.icache.overall_miss_latency::total 21541500 # number of overall miss cycles
499system.cpu.icache.ReadReq_accesses::cpu.inst 2015 # number of ReadReq accesses(hits+misses)
500system.cpu.icache.ReadReq_accesses::total 2015 # number of ReadReq accesses(hits+misses)
501system.cpu.icache.demand_accesses::cpu.inst 2015 # number of demand (read+write) accesses
502system.cpu.icache.demand_accesses::total 2015 # number of demand (read+write) accesses
503system.cpu.icache.overall_accesses::cpu.inst 2015 # number of overall (read+write) accesses
504system.cpu.icache.overall_accesses::total 2015 # number of overall (read+write) accesses
505system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.225806 # miss rate for ReadReq accesses
506system.cpu.icache.ReadReq_miss_rate::total 0.225806 # miss rate for ReadReq accesses
507system.cpu.icache.demand_miss_rate::cpu.inst 0.225806 # miss rate for demand accesses
508system.cpu.icache.demand_miss_rate::total 0.225806 # miss rate for demand accesses
509system.cpu.icache.overall_miss_rate::cpu.inst 0.225806 # miss rate for overall accesses
510system.cpu.icache.overall_miss_rate::total 0.225806 # miss rate for overall accesses
511system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47343.956044 # average ReadReq miss latency
512system.cpu.icache.ReadReq_avg_miss_latency::total 47343.956044 # average ReadReq miss latency
513system.cpu.icache.demand_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency
514system.cpu.icache.demand_avg_miss_latency::total 47343.956044 # average overall miss latency
515system.cpu.icache.overall_avg_miss_latency::cpu.inst 47343.956044 # average overall miss latency
516system.cpu.icache.overall_avg_miss_latency::total 47343.956044 # average overall miss latency
517system.cpu.icache.blocked_cycles::no_mshrs 5 # number of cycles access was blocked

479system.cpu.icache.occ_blocks::cpu.inst 163.149412 # Average occupied blocks per requestor
480system.cpu.icache.occ_percent::cpu.inst 0.079663 # Average percentage of cache occupancy
481system.cpu.icache.occ_percent::total 0.079663 # Average percentage of cache occupancy
482system.cpu.icache.ReadReq_hits::cpu.inst 1502 # number of ReadReq hits
483system.cpu.icache.ReadReq_hits::total 1502 # number of ReadReq hits
484system.cpu.icache.demand_hits::cpu.inst 1502 # number of demand (read+write) hits
485system.cpu.icache.demand_hits::total 1502 # number of demand (read+write) hits
486system.cpu.icache.overall_hits::cpu.inst 1502 # number of overall hits
487system.cpu.icache.overall_hits::total 1502 # number of overall hits
488system.cpu.icache.ReadReq_misses::cpu.inst 446 # number of ReadReq misses
489system.cpu.icache.ReadReq_misses::total 446 # number of ReadReq misses
490system.cpu.icache.demand_misses::cpu.inst 446 # number of demand (read+write) misses
491system.cpu.icache.demand_misses::total 446 # number of demand (read+write) misses
492system.cpu.icache.overall_misses::cpu.inst 446 # number of overall misses
493system.cpu.icache.overall_misses::total 446 # number of overall misses
494system.cpu.icache.ReadReq_miss_latency::cpu.inst 21402000 # number of ReadReq miss cycles
495system.cpu.icache.ReadReq_miss_latency::total 21402000 # number of ReadReq miss cycles
496system.cpu.icache.demand_miss_latency::cpu.inst 21402000 # number of demand (read+write) miss cycles
497system.cpu.icache.demand_miss_latency::total 21402000 # number of demand (read+write) miss cycles
498system.cpu.icache.overall_miss_latency::cpu.inst 21402000 # number of overall miss cycles
499system.cpu.icache.overall_miss_latency::total 21402000 # number of overall miss cycles
500system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses)
501system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses)
502system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses
503system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses
504system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses
505system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses
506system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.228953 # miss rate for ReadReq accesses
507system.cpu.icache.ReadReq_miss_rate::total 0.228953 # miss rate for ReadReq accesses
508system.cpu.icache.demand_miss_rate::cpu.inst 0.228953 # miss rate for demand accesses
509system.cpu.icache.demand_miss_rate::total 0.228953 # miss rate for demand accesses
510system.cpu.icache.overall_miss_rate::cpu.inst 0.228953 # miss rate for overall accesses
511system.cpu.icache.overall_miss_rate::total 0.228953 # miss rate for overall accesses
512system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 47986.547085 # average ReadReq miss latency
513system.cpu.icache.ReadReq_avg_miss_latency::total 47986.547085 # average ReadReq miss latency
514system.cpu.icache.demand_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
515system.cpu.icache.demand_avg_miss_latency::total 47986.547085 # average overall miss latency
516system.cpu.icache.overall_avg_miss_latency::cpu.inst 47986.547085 # average overall miss latency
517system.cpu.icache.overall_avg_miss_latency::total 47986.547085 # average overall miss latency
518system.cpu.icache.blocked_cycles::no_mshrs 6 # number of cycles access was blocked

518system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
519system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
520system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

519system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
520system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
521system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked

521system.cpu.icache.avg_blocked_cycles::no_mshrs 5 # average number of cycles each access was blocked

522system.cpu.icache.avg_blocked_cycles::no_mshrs 6 # average number of cycles each access was blocked

522system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
523system.cpu.icache.fast_writes 0 # number of fast writes performed
524system.cpu.icache.cache_copies 0 # number of cache copies performed

523system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
524system.cpu.icache.fast_writes 0 # number of fast writes performed
525system.cpu.icache.cache_copies 0 # number of cache copies performed

525system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits
526system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
527system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits
528system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits
529system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits
530system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits
531system.cpu.icache.ReadReq_mshr_misses::cpu.inst 342 # number of ReadReq MSHR misses
532system.cpu.icache.ReadReq_mshr_misses::total 342 # number of ReadReq MSHR misses
533system.cpu.icache.demand_mshr_misses::cpu.inst 342 # number of demand (read+write) MSHR misses
534system.cpu.icache.demand_mshr_misses::total 342 # number of demand (read+write) MSHR misses
535system.cpu.icache.overall_mshr_misses::cpu.inst 342 # number of overall MSHR misses
536system.cpu.icache.overall_mshr_misses::total 342 # number of overall MSHR misses
537system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 17063000 # number of ReadReq MSHR miss cycles
538system.cpu.icache.ReadReq_mshr_miss_latency::total 17063000 # number of ReadReq MSHR miss cycles
539system.cpu.icache.demand_mshr_miss_latency::cpu.inst 17063000 # number of demand (read+write) MSHR miss cycles
540system.cpu.icache.demand_mshr_miss_latency::total 17063000 # number of demand (read+write) MSHR miss cycles
541system.cpu.icache.overall_mshr_miss_latency::cpu.inst 17063000 # number of overall MSHR miss cycles
542system.cpu.icache.overall_mshr_miss_latency::total 17063000 # number of overall MSHR miss cycles
543system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for ReadReq accesses
544system.cpu.icache.ReadReq_mshr_miss_rate::total 0.169727 # mshr miss rate for ReadReq accesses
545system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for demand accesses
546system.cpu.icache.demand_mshr_miss_rate::total 0.169727 # mshr miss rate for demand accesses
547system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.169727 # mshr miss rate for overall accesses
548system.cpu.icache.overall_mshr_miss_rate::total 0.169727 # mshr miss rate for overall accesses
549system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 49891.812865 # average ReadReq mshr miss latency
550system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 49891.812865 # average ReadReq mshr miss latency
551system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency
552system.cpu.icache.demand_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency
553system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 49891.812865 # average overall mshr miss latency
554system.cpu.icache.overall_avg_mshr_miss_latency::total 49891.812865 # average overall mshr miss latency

526system.cpu.icache.ReadReq_mshr_hits::cpu.inst 108 # number of ReadReq MSHR hits
527system.cpu.icache.ReadReq_mshr_hits::total 108 # number of ReadReq MSHR hits
528system.cpu.icache.demand_mshr_hits::cpu.inst 108 # number of demand (read+write) MSHR hits
529system.cpu.icache.demand_mshr_hits::total 108 # number of demand (read+write) MSHR hits
530system.cpu.icache.overall_mshr_hits::cpu.inst 108 # number of overall MSHR hits
531system.cpu.icache.overall_mshr_hits::total 108 # number of overall MSHR hits
532system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
533system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
534system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
535system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
536system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
537system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
538system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 16954500 # number of ReadReq MSHR miss cycles
539system.cpu.icache.ReadReq_mshr_miss_latency::total 16954500 # number of ReadReq MSHR miss cycles
540system.cpu.icache.demand_mshr_miss_latency::cpu.inst 16954500 # number of demand (read+write) MSHR miss cycles
541system.cpu.icache.demand_mshr_miss_latency::total 16954500 # number of demand (read+write) MSHR miss cycles
542system.cpu.icache.overall_mshr_miss_latency::cpu.inst 16954500 # number of overall MSHR miss cycles
543system.cpu.icache.overall_mshr_miss_latency::total 16954500 # number of overall MSHR miss cycles
544system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for ReadReq accesses
545system.cpu.icache.ReadReq_mshr_miss_rate::total 0.173511 # mshr miss rate for ReadReq accesses
546system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for demand accesses
547system.cpu.icache.demand_mshr_miss_rate::total 0.173511 # mshr miss rate for demand accesses
548system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.173511 # mshr miss rate for overall accesses
549system.cpu.icache.overall_mshr_miss_rate::total 0.173511 # mshr miss rate for overall accesses
550system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 50161.242604 # average ReadReq mshr miss latency
551system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 50161.242604 # average ReadReq mshr miss latency
552system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
553system.cpu.icache.demand_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency
554system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 50161.242604 # average overall mshr miss latency
555system.cpu.icache.overall_avg_mshr_miss_latency::total 50161.242604 # average overall mshr miss latency

555system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

556system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate

556system.cpu.dcache.replacements 0 # number of replacements
557system.cpu.dcache.tagsinuse 91.458224 # Cycle average of tags in use
558system.cpu.dcache.total_refs 2418 # Total number of references to valid blocks.
559system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
560system.cpu.dcache.avg_refs 17.148936 # Average number of references to valid blocks.
561system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
562system.cpu.dcache.occ_blocks::cpu.data 91.458224 # Average occupied blocks per requestor
563system.cpu.dcache.occ_percent::cpu.data 0.022329 # Average percentage of cache occupancy
564system.cpu.dcache.occ_percent::total 0.022329 # Average percentage of cache occupancy
565system.cpu.dcache.ReadReq_hits::cpu.data 1846 # number of ReadReq hits
566system.cpu.dcache.ReadReq_hits::total 1846 # number of ReadReq hits
567system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
568system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits
569system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits
570system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits
571system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits
572system.cpu.dcache.overall_hits::total 2418 # number of overall hits
573system.cpu.dcache.ReadReq_misses::cpu.data 149 # number of ReadReq misses
574system.cpu.dcache.ReadReq_misses::total 149 # number of ReadReq misses
575system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses
576system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses
577system.cpu.dcache.demand_misses::cpu.data 502 # number of demand (read+write) misses
578system.cpu.dcache.demand_misses::total 502 # number of demand (read+write) misses
579system.cpu.dcache.overall_misses::cpu.data 502 # number of overall misses
580system.cpu.dcache.overall_misses::total 502 # number of overall misses
581system.cpu.dcache.ReadReq_miss_latency::cpu.data 8305500 # number of ReadReq miss cycles
582system.cpu.dcache.ReadReq_miss_latency::total 8305500 # number of ReadReq miss cycles
583system.cpu.dcache.WriteReq_miss_latency::cpu.data 15423499 # number of WriteReq miss cycles
584system.cpu.dcache.WriteReq_miss_latency::total 15423499 # number of WriteReq miss cycles
585system.cpu.dcache.demand_miss_latency::cpu.data 23728999 # number of demand (read+write) miss cycles
586system.cpu.dcache.demand_miss_latency::total 23728999 # number of demand (read+write) miss cycles
587system.cpu.dcache.overall_miss_latency::cpu.data 23728999 # number of overall miss cycles
588system.cpu.dcache.overall_miss_latency::total 23728999 # number of overall miss cycles
589system.cpu.dcache.ReadReq_accesses::cpu.data 1995 # number of ReadReq accesses(hits+misses)
590system.cpu.dcache.ReadReq_accesses::total 1995 # number of ReadReq accesses(hits+misses)
591system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
592system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
593system.cpu.dcache.demand_accesses::cpu.data 2920 # number of demand (read+write) accesses
594system.cpu.dcache.demand_accesses::total 2920 # number of demand (read+write) accesses
595system.cpu.dcache.overall_accesses::cpu.data 2920 # number of overall (read+write) accesses
596system.cpu.dcache.overall_accesses::total 2920 # number of overall (read+write) accesses
597system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074687 # miss rate for ReadReq accesses
598system.cpu.dcache.ReadReq_miss_rate::total 0.074687 # miss rate for ReadReq accesses
599system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses
600system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses
601system.cpu.dcache.demand_miss_rate::cpu.data 0.171918 # miss rate for demand accesses
602system.cpu.dcache.demand_miss_rate::total 0.171918 # miss rate for demand accesses
603system.cpu.dcache.overall_miss_rate::cpu.data 0.171918 # miss rate for overall accesses
604system.cpu.dcache.overall_miss_rate::total 0.171918 # miss rate for overall accesses
605system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 55741.610738 # average ReadReq miss latency
606system.cpu.dcache.ReadReq_avg_miss_latency::total 55741.610738 # average ReadReq miss latency
607system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 43692.631728 # average WriteReq miss latency
608system.cpu.dcache.WriteReq_avg_miss_latency::total 43692.631728 # average WriteReq miss latency
609system.cpu.dcache.demand_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency
610system.cpu.dcache.demand_avg_miss_latency::total 47268.922311 # average overall miss latency
611system.cpu.dcache.overall_avg_miss_latency::cpu.data 47268.922311 # average overall miss latency
612system.cpu.dcache.overall_avg_miss_latency::total 47268.922311 # average overall miss latency
613system.cpu.dcache.blocked_cycles::no_mshrs 489 # number of cycles access was blocked
614system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
615system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
616system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
617system.cpu.dcache.avg_blocked_cycles::no_mshrs 44.454545 # average number of cycles each access was blocked
618system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
619system.cpu.dcache.fast_writes 0 # number of fast writes performed
620system.cpu.dcache.cache_copies 0 # number of cache copies performed
621system.cpu.dcache.ReadReq_mshr_hits::cpu.data 59 # number of ReadReq MSHR hits
622system.cpu.dcache.ReadReq_mshr_hits::total 59 # number of ReadReq MSHR hits
623system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits
624system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits
625system.cpu.dcache.demand_mshr_hits::cpu.data 361 # number of demand (read+write) MSHR hits
626system.cpu.dcache.demand_mshr_hits::total 361 # number of demand (read+write) MSHR hits
627system.cpu.dcache.overall_mshr_hits::cpu.data 361 # number of overall MSHR hits
628system.cpu.dcache.overall_mshr_hits::total 361 # number of overall MSHR hits
629system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
630system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
631system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
632system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
633system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
634system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
635system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
636system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
637system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5420000 # number of ReadReq MSHR miss cycles
638system.cpu.dcache.ReadReq_mshr_miss_latency::total 5420000 # number of ReadReq MSHR miss cycles
639system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2754499 # number of WriteReq MSHR miss cycles
640system.cpu.dcache.WriteReq_mshr_miss_latency::total 2754499 # number of WriteReq MSHR miss cycles
641system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8174499 # number of demand (read+write) MSHR miss cycles
642system.cpu.dcache.demand_mshr_miss_latency::total 8174499 # number of demand (read+write) MSHR miss cycles
643system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8174499 # number of overall MSHR miss cycles
644system.cpu.dcache.overall_mshr_miss_latency::total 8174499 # number of overall MSHR miss cycles
645system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045113 # mshr miss rate for ReadReq accesses
646system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045113 # mshr miss rate for ReadReq accesses
647system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
648system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
649system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for demand accesses
650system.cpu.dcache.demand_mshr_miss_rate::total 0.048288 # mshr miss rate for demand accesses
651system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048288 # mshr miss rate for overall accesses
652system.cpu.dcache.overall_mshr_miss_rate::total 0.048288 # mshr miss rate for overall accesses
653system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 60222.222222 # average ReadReq mshr miss latency
654system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 60222.222222 # average ReadReq mshr miss latency
655system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 54009.784314 # average WriteReq mshr miss latency
656system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 54009.784314 # average WriteReq mshr miss latency
657system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency
658system.cpu.dcache.demand_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency
659system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 57975.170213 # average overall mshr miss latency
660system.cpu.dcache.overall_avg_mshr_miss_latency::total 57975.170213 # average overall mshr miss latency
661system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate

662system.cpu.l2cache.replacements 0 # number of replacements

557system.cpu.l2cache.replacements 0 # number of replacements

663system.cpu.l2cache.tagsinuse 224.543944 # Cycle average of tags in use

558system.cpu.l2cache.tagsinuse 223.784369 # Cycle average of tags in use

664system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.

559system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.

665system.cpu.l2cache.sampled_refs 429 # Sample count of references to valid blocks.
666system.cpu.l2cache.avg_refs 0.006993 # Average number of references to valid blocks.

560system.cpu.l2cache.sampled_refs 425 # Sample count of references to valid blocks.
561system.cpu.l2cache.avg_refs 0.007059 # Average number of references to valid blocks.

667system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

562system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

668system.cpu.l2cache.occ_blocks::cpu.inst 166.808951 # Average occupied blocks per requestor
669system.cpu.l2cache.occ_blocks::cpu.data 57.734994 # Average occupied blocks per requestor
670system.cpu.l2cache.occ_percent::cpu.inst 0.005091 # Average percentage of cache occupancy
671system.cpu.l2cache.occ_percent::cpu.data 0.001762 # Average percentage of cache occupancy
672system.cpu.l2cache.occ_percent::total 0.006853 # Average percentage of cache occupancy

563system.cpu.l2cache.occ_blocks::cpu.inst 165.662974 # Average occupied blocks per requestor
564system.cpu.l2cache.occ_blocks::cpu.data 58.121395 # Average occupied blocks per requestor
565system.cpu.l2cache.occ_percent::cpu.inst 0.005056 # Average percentage of cache occupancy
566system.cpu.l2cache.occ_percent::cpu.data 0.001774 # Average percentage of cache occupancy
567system.cpu.l2cache.occ_percent::total 0.006829 # Average percentage of cache occupancy

673system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
674system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
675system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
676system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
677system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
678system.cpu.l2cache.overall_hits::total 3 # number of overall hits

568system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
569system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
570system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
571system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
572system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
573system.cpu.l2cache.overall_hits::total 3 # number of overall hits

679system.cpu.l2cache.ReadReq_misses::cpu.inst 339 # number of ReadReq misses

574system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses

680system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses

575system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses

681system.cpu.l2cache.ReadReq_misses::total 429 # number of ReadReq misses

576system.cpu.l2cache.ReadReq_misses::total 425 # number of ReadReq misses

682system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
683system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses

577system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
578system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses

684system.cpu.l2cache.demand_misses::cpu.inst 339 # number of demand (read+write) misses

579system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses

685system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses

580system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses

686system.cpu.l2cache.demand_misses::total 480 # number of demand (read+write) misses
687system.cpu.l2cache.overall_misses::cpu.inst 339 # number of overall misses

581system.cpu.l2cache.demand_misses::total 476 # number of demand (read+write) misses
582system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses

688system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses

583system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses

689system.cpu.l2cache.overall_misses::total 480 # number of overall misses
690system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16691000 # number of ReadReq miss cycles
691system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5327000 # number of ReadReq miss cycles
692system.cpu.l2cache.ReadReq_miss_latency::total 22018000 # number of ReadReq miss cycles
693system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702500 # number of ReadExReq miss cycles
694system.cpu.l2cache.ReadExReq_miss_latency::total 2702500 # number of ReadExReq miss cycles
695system.cpu.l2cache.demand_miss_latency::cpu.inst 16691000 # number of demand (read+write) miss cycles
696system.cpu.l2cache.demand_miss_latency::cpu.data 8029500 # number of demand (read+write) miss cycles
697system.cpu.l2cache.demand_miss_latency::total 24720500 # number of demand (read+write) miss cycles
698system.cpu.l2cache.overall_miss_latency::cpu.inst 16691000 # number of overall miss cycles
699system.cpu.l2cache.overall_miss_latency::cpu.data 8029500 # number of overall miss cycles
700system.cpu.l2cache.overall_miss_latency::total 24720500 # number of overall miss cycles
701system.cpu.l2cache.ReadReq_accesses::cpu.inst 342 # number of ReadReq accesses(hits+misses)

584system.cpu.l2cache.overall_misses::total 476 # number of overall misses
585system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 16586500 # number of ReadReq miss cycles
586system.cpu.l2cache.ReadReq_miss_latency::cpu.data 5449500 # number of ReadReq miss cycles
587system.cpu.l2cache.ReadReq_miss_latency::total 22036000 # number of ReadReq miss cycles
588system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 2702000 # number of ReadExReq miss cycles
589system.cpu.l2cache.ReadExReq_miss_latency::total 2702000 # number of ReadExReq miss cycles
590system.cpu.l2cache.demand_miss_latency::cpu.inst 16586500 # number of demand (read+write) miss cycles
591system.cpu.l2cache.demand_miss_latency::cpu.data 8151500 # number of demand (read+write) miss cycles
592system.cpu.l2cache.demand_miss_latency::total 24738000 # number of demand (read+write) miss cycles
593system.cpu.l2cache.overall_miss_latency::cpu.inst 16586500 # number of overall miss cycles
594system.cpu.l2cache.overall_miss_latency::cpu.data 8151500 # number of overall miss cycles
595system.cpu.l2cache.overall_miss_latency::total 24738000 # number of overall miss cycles
596system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)

702system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)

597system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)

703system.cpu.l2cache.ReadReq_accesses::total 432 # number of ReadReq accesses(hits+misses)

598system.cpu.l2cache.ReadReq_accesses::total 428 # number of ReadReq accesses(hits+misses)

704system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
705system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)

599system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
600system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)

706system.cpu.l2cache.demand_accesses::cpu.inst 342 # number of demand (read+write) accesses

601system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses

707system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses

602system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses

708system.cpu.l2cache.demand_accesses::total 483 # number of demand (read+write) accesses
709system.cpu.l2cache.overall_accesses::cpu.inst 342 # number of overall (read+write) accesses

603system.cpu.l2cache.demand_accesses::total 479 # number of demand (read+write) accesses
604system.cpu.l2cache.overall_accesses::cpu.inst 338 # number of overall (read+write) accesses

710system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses

605system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses

711system.cpu.l2cache.overall_accesses::total 483 # number of overall (read+write) accesses
712system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991228 # miss rate for ReadReq accesses

606system.cpu.l2cache.overall_accesses::total 479 # number of overall (read+write) accesses
607system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991124 # miss rate for ReadReq accesses

713system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses

608system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses

714system.cpu.l2cache.ReadReq_miss_rate::total 0.993056 # miss rate for ReadReq accesses

609system.cpu.l2cache.ReadReq_miss_rate::total 0.992991 # miss rate for ReadReq accesses

715system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
716system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

610system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
611system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses

717system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991228 # miss rate for demand accesses

612system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses

718system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses

613system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses

719system.cpu.l2cache.demand_miss_rate::total 0.993789 # miss rate for demand accesses
720system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991228 # miss rate for overall accesses

614system.cpu.l2cache.demand_miss_rate::total 0.993737 # miss rate for demand accesses
615system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses

721system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses

616system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses

722system.cpu.l2cache.overall_miss_rate::total 0.993789 # miss rate for overall accesses
723system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49235.988201 # average ReadReq miss latency
724system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 59188.888889 # average ReadReq miss latency
725system.cpu.l2cache.ReadReq_avg_miss_latency::total 51324.009324 # average ReadReq miss latency
726system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52990.196078 # average ReadExReq miss latency
727system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52990.196078 # average ReadExReq miss latency
728system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency
729system.cpu.l2cache.demand_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency
730system.cpu.l2cache.demand_avg_miss_latency::total 51501.041667 # average overall miss latency
731system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49235.988201 # average overall miss latency
732system.cpu.l2cache.overall_avg_miss_latency::cpu.data 56946.808511 # average overall miss latency
733system.cpu.l2cache.overall_avg_miss_latency::total 51501.041667 # average overall miss latency

617system.cpu.l2cache.overall_miss_rate::total 0.993737 # miss rate for overall accesses
618system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 49511.940299 # average ReadReq miss latency
619system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 60550 # average ReadReq miss latency
620system.cpu.l2cache.ReadReq_avg_miss_latency::total 51849.411765 # average ReadReq miss latency
621system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 52980.392157 # average ReadExReq miss latency
622system.cpu.l2cache.ReadExReq_avg_miss_latency::total 52980.392157 # average ReadExReq miss latency
623system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
624system.cpu.l2cache.demand_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
625system.cpu.l2cache.demand_avg_miss_latency::total 51970.588235 # average overall miss latency
626system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 49511.940299 # average overall miss latency
627system.cpu.l2cache.overall_avg_miss_latency::cpu.data 57812.056738 # average overall miss latency
628system.cpu.l2cache.overall_avg_miss_latency::total 51970.588235 # average overall miss latency

734system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
735system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
736system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
737system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
738system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
739system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
740system.cpu.l2cache.fast_writes 0 # number of fast writes performed
741system.cpu.l2cache.cache_copies 0 # number of cache copies performed

629system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
630system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
631system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
632system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
633system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
634system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
635system.cpu.l2cache.fast_writes 0 # number of fast writes performed
636system.cpu.l2cache.cache_copies 0 # number of cache copies performed

742system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 339 # number of ReadReq MSHR misses

637system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses

743system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses

638system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses

744system.cpu.l2cache.ReadReq_mshr_misses::total 429 # number of ReadReq MSHR misses

639system.cpu.l2cache.ReadReq_mshr_misses::total 425 # number of ReadReq MSHR misses

745system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
746system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses

640system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
641system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses

747system.cpu.l2cache.demand_mshr_misses::cpu.inst 339 # number of demand (read+write) MSHR misses

642system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses

748system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses

643system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses

749system.cpu.l2cache.demand_mshr_misses::total 480 # number of demand (read+write) MSHR misses
750system.cpu.l2cache.overall_mshr_misses::cpu.inst 339 # number of overall MSHR misses

644system.cpu.l2cache.demand_mshr_misses::total 476 # number of demand (read+write) MSHR misses
645system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses

751system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses

646system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses

752system.cpu.l2cache.overall_mshr_misses::total 480 # number of overall MSHR misses
753system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12421544 # number of ReadReq MSHR miss cycles
754system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4218076 # number of ReadReq MSHR miss cycles
755system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16639620 # number of ReadReq MSHR miss cycles

647system.cpu.l2cache.overall_mshr_misses::total 476 # number of overall MSHR misses
648system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 12363045 # number of ReadReq MSHR miss cycles
649system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4340573 # number of ReadReq MSHR miss cycles
650system.cpu.l2cache.ReadReq_mshr_miss_latency::total 16703618 # number of ReadReq MSHR miss cycles

756system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles
757system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles

651system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2071054 # number of ReadExReq MSHR miss cycles
652system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2071054 # number of ReadExReq MSHR miss cycles

758system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12421544 # number of demand (read+write) MSHR miss cycles
759system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6289130 # number of demand (read+write) MSHR miss cycles
760system.cpu.l2cache.demand_mshr_miss_latency::total 18710674 # number of demand (read+write) MSHR miss cycles
761system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12421544 # number of overall MSHR miss cycles
762system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6289130 # number of overall MSHR miss cycles
763system.cpu.l2cache.overall_mshr_miss_latency::total 18710674 # number of overall MSHR miss cycles
764system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for ReadReq accesses

653system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 12363045 # number of demand (read+write) MSHR miss cycles
654system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6411627 # number of demand (read+write) MSHR miss cycles
655system.cpu.l2cache.demand_mshr_miss_latency::total 18774672 # number of demand (read+write) MSHR miss cycles
656system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 12363045 # number of overall MSHR miss cycles
657system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6411627 # number of overall MSHR miss cycles
658system.cpu.l2cache.overall_mshr_miss_latency::total 18774672 # number of overall MSHR miss cycles
659system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses

765system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses

660system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses

766system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993056 # mshr miss rate for ReadReq accesses

661system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992991 # mshr miss rate for ReadReq accesses

767system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
768system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

662system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
663system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses

769system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for demand accesses

664system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses

770system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses

665system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses

771system.cpu.l2cache.demand_mshr_miss_rate::total 0.993789 # mshr miss rate for demand accesses
772system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991228 # mshr miss rate for overall accesses

666system.cpu.l2cache.demand_mshr_miss_rate::total 0.993737 # mshr miss rate for demand accesses
667system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses

773system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses

668system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses

774system.cpu.l2cache.overall_mshr_miss_rate::total 0.993789 # mshr miss rate for overall accesses
775system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36641.722714 # average ReadReq mshr miss latency
776system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 46867.511111 # average ReadReq mshr miss latency
777system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 38786.993007 # average ReadReq mshr miss latency

669system.cpu.l2cache.overall_mshr_miss_rate::total 0.993737 # mshr miss rate for overall accesses
670system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 36904.611940 # average ReadReq mshr miss latency
671system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 48228.588889 # average ReadReq mshr miss latency
672system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 39302.630588 # average ReadReq mshr miss latency

778system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency
779system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency

673system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 40608.901961 # average ReadExReq mshr miss latency
674system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 40608.901961 # average ReadExReq mshr miss latency

780system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency
781system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency
782system.cpu.l2cache.demand_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency
783system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36641.722714 # average overall mshr miss latency
784system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 44603.758865 # average overall mshr miss latency
785system.cpu.l2cache.overall_avg_mshr_miss_latency::total 38980.570833 # average overall mshr miss latency

675system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
676system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
677system.cpu.l2cache.demand_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency
678system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 36904.611940 # average overall mshr miss latency
679system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 45472.531915 # average overall mshr miss latency
680system.cpu.l2cache.overall_avg_mshr_miss_latency::total 39442.588235 # average overall mshr miss latency

786system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

681system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate

682system.cpu.dcache.replacements 0 # number of replacements
683system.cpu.dcache.tagsinuse 92.011405 # Cycle average of tags in use
684system.cpu.dcache.total_refs 2420 # Total number of references to valid blocks.
685system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
686system.cpu.dcache.avg_refs 17.163121 # Average number of references to valid blocks.
687system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.
688system.cpu.dcache.occ_blocks::cpu.data 92.011405 # Average occupied blocks per requestor
689system.cpu.dcache.occ_percent::cpu.data 0.022464 # Average percentage of cache occupancy
690system.cpu.dcache.occ_percent::total 0.022464 # Average percentage of cache occupancy
691system.cpu.dcache.ReadReq_hits::cpu.data 1848 # number of ReadReq hits
692system.cpu.dcache.ReadReq_hits::total 1848 # number of ReadReq hits
693system.cpu.dcache.WriteReq_hits::cpu.data 572 # number of WriteReq hits
694system.cpu.dcache.WriteReq_hits::total 572 # number of WriteReq hits
695system.cpu.dcache.demand_hits::cpu.data 2420 # number of demand (read+write) hits
696system.cpu.dcache.demand_hits::total 2420 # number of demand (read+write) hits
697system.cpu.dcache.overall_hits::cpu.data 2420 # number of overall hits
698system.cpu.dcache.overall_hits::total 2420 # number of overall hits
699system.cpu.dcache.ReadReq_misses::cpu.data 151 # number of ReadReq misses
700system.cpu.dcache.ReadReq_misses::total 151 # number of ReadReq misses
701system.cpu.dcache.WriteReq_misses::cpu.data 353 # number of WriteReq misses
702system.cpu.dcache.WriteReq_misses::total 353 # number of WriteReq misses
703system.cpu.dcache.demand_misses::cpu.data 504 # number of demand (read+write) misses
704system.cpu.dcache.demand_misses::total 504 # number of demand (read+write) misses
705system.cpu.dcache.overall_misses::cpu.data 504 # number of overall misses
706system.cpu.dcache.overall_misses::total 504 # number of overall misses
707system.cpu.dcache.ReadReq_miss_latency::cpu.data 8901000 # number of ReadReq miss cycles
708system.cpu.dcache.ReadReq_miss_latency::total 8901000 # number of ReadReq miss cycles
709system.cpu.dcache.WriteReq_miss_latency::cpu.data 15603499 # number of WriteReq miss cycles
710system.cpu.dcache.WriteReq_miss_latency::total 15603499 # number of WriteReq miss cycles
711system.cpu.dcache.demand_miss_latency::cpu.data 24504499 # number of demand (read+write) miss cycles
712system.cpu.dcache.demand_miss_latency::total 24504499 # number of demand (read+write) miss cycles
713system.cpu.dcache.overall_miss_latency::cpu.data 24504499 # number of overall miss cycles
714system.cpu.dcache.overall_miss_latency::total 24504499 # number of overall miss cycles
715system.cpu.dcache.ReadReq_accesses::cpu.data 1999 # number of ReadReq accesses(hits+misses)
716system.cpu.dcache.ReadReq_accesses::total 1999 # number of ReadReq accesses(hits+misses)
717system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
718system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
719system.cpu.dcache.demand_accesses::cpu.data 2924 # number of demand (read+write) accesses
720system.cpu.dcache.demand_accesses::total 2924 # number of demand (read+write) accesses
721system.cpu.dcache.overall_accesses::cpu.data 2924 # number of overall (read+write) accesses
722system.cpu.dcache.overall_accesses::total 2924 # number of overall (read+write) accesses
723system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.075538 # miss rate for ReadReq accesses
724system.cpu.dcache.ReadReq_miss_rate::total 0.075538 # miss rate for ReadReq accesses
725system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381622 # miss rate for WriteReq accesses
726system.cpu.dcache.WriteReq_miss_rate::total 0.381622 # miss rate for WriteReq accesses
727system.cpu.dcache.demand_miss_rate::cpu.data 0.172367 # miss rate for demand accesses
728system.cpu.dcache.demand_miss_rate::total 0.172367 # miss rate for demand accesses
729system.cpu.dcache.overall_miss_rate::cpu.data 0.172367 # miss rate for overall accesses
730system.cpu.dcache.overall_miss_rate::total 0.172367 # miss rate for overall accesses
731system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 58947.019868 # average ReadReq miss latency
732system.cpu.dcache.ReadReq_avg_miss_latency::total 58947.019868 # average ReadReq miss latency
733system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 44202.546742 # average WriteReq miss latency
734system.cpu.dcache.WriteReq_avg_miss_latency::total 44202.546742 # average WriteReq miss latency
735system.cpu.dcache.demand_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
736system.cpu.dcache.demand_avg_miss_latency::total 48620.037698 # average overall miss latency
737system.cpu.dcache.overall_avg_miss_latency::cpu.data 48620.037698 # average overall miss latency
738system.cpu.dcache.overall_avg_miss_latency::total 48620.037698 # average overall miss latency
739system.cpu.dcache.blocked_cycles::no_mshrs 502 # number of cycles access was blocked
740system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
741system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
742system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
743system.cpu.dcache.avg_blocked_cycles::no_mshrs 45.636364 # average number of cycles each access was blocked
744system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
745system.cpu.dcache.fast_writes 0 # number of fast writes performed
746system.cpu.dcache.cache_copies 0 # number of cache copies performed
747system.cpu.dcache.ReadReq_mshr_hits::cpu.data 61 # number of ReadReq MSHR hits
748system.cpu.dcache.ReadReq_mshr_hits::total 61 # number of ReadReq MSHR hits
749system.cpu.dcache.WriteReq_mshr_hits::cpu.data 302 # number of WriteReq MSHR hits
750system.cpu.dcache.WriteReq_mshr_hits::total 302 # number of WriteReq MSHR hits
751system.cpu.dcache.demand_mshr_hits::cpu.data 363 # number of demand (read+write) MSHR hits
752system.cpu.dcache.demand_mshr_hits::total 363 # number of demand (read+write) MSHR hits
753system.cpu.dcache.overall_mshr_hits::cpu.data 363 # number of overall MSHR hits
754system.cpu.dcache.overall_mshr_hits::total 363 # number of overall MSHR hits
755system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
756system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses
757system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
758system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
759system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
760system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
761system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
762system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
763system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 5543000 # number of ReadReq MSHR miss cycles
764system.cpu.dcache.ReadReq_mshr_miss_latency::total 5543000 # number of ReadReq MSHR miss cycles
765system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2753999 # number of WriteReq MSHR miss cycles
766system.cpu.dcache.WriteReq_mshr_miss_latency::total 2753999 # number of WriteReq MSHR miss cycles
767system.cpu.dcache.demand_mshr_miss_latency::cpu.data 8296999 # number of demand (read+write) MSHR miss cycles
768system.cpu.dcache.demand_mshr_miss_latency::total 8296999 # number of demand (read+write) MSHR miss cycles
769system.cpu.dcache.overall_mshr_miss_latency::cpu.data 8296999 # number of overall MSHR miss cycles
770system.cpu.dcache.overall_mshr_miss_latency::total 8296999 # number of overall MSHR miss cycles
771system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045023 # mshr miss rate for ReadReq accesses
772system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045023 # mshr miss rate for ReadReq accesses
773system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
774system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
775system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for demand accesses
776system.cpu.dcache.demand_mshr_miss_rate::total 0.048222 # mshr miss rate for demand accesses
777system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048222 # mshr miss rate for overall accesses
778system.cpu.dcache.overall_mshr_miss_rate::total 0.048222 # mshr miss rate for overall accesses
779system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 61588.888889 # average ReadReq mshr miss latency
780system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 61588.888889 # average ReadReq mshr miss latency
781system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 53999.980392 # average WriteReq mshr miss latency
782system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 53999.980392 # average WriteReq mshr miss latency
783system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
784system.cpu.dcache.demand_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
785system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 58843.964539 # average overall mshr miss latency
786system.cpu.dcache.overall_avg_mshr_miss_latency::total 58843.964539 # average overall mshr miss latency
787system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate