Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/stats.txt

1
2---------- Begin Simulation Statistics ----------

3sim_seconds 0.000012 # Number of seconds simulated
4sim_ticks 12478500 # Number of ticks simulated
5final_tick 12478500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

3sim_seconds 0.000013 # Number of seconds simulated
4sim_ticks 13016500 # Number of ticks simulated
5final_tick 13016500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)

6sim_freq 1000000000000 # Frequency of simulated ticks

7host_inst_rate 84509 # Simulator instruction rate (inst/s)
8host_op_rate 84485 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 203899861 # Simulator tick rate (ticks/s)
10host_mem_usage 220092 # Number of bytes of host memory used
11host_seconds 0.06 # Real time elapsed on the host

7host_inst_rate 54505 # Simulator instruction rate (inst/s)
8host_op_rate 54495 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 137205108 # Simulator tick rate (ticks/s)
10host_mem_usage 220060 # Number of bytes of host memory used
11host_seconds 0.10 # Real time elapsed on the host

12sim_insts 5169 # Number of instructions simulated
13sim_ops 5169 # Number of ops (including micro ops) simulated

14system.physmem.bytes_read::cpu.inst 21632 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9152 # Number of bytes read from this memory

14system.physmem.bytes_read::cpu.inst 21760 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory

16system.physmem.bytes_read::total 30784 # Number of bytes read from this memory

17system.physmem.bytes_inst_read::cpu.inst 21632 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21632 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 338 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 143 # Number of read requests responded to by this memory

17system.physmem.bytes_inst_read::cpu.inst 21760 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21760 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 340 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory

21system.physmem.num_reads::total 481 # Number of read requests responded to by this memory

22system.physmem.bw_read::cpu.inst 1733541692 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 733421485 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2466963177 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1733541692 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1733541692 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1733541692 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 733421485 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2466963177 # Total bandwidth to/from this memory (bytes/s)

22system.physmem.bw_read::cpu.inst 1671724350 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 693273922 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 2364998271 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 1671724350 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 1671724350 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 1671724350 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 693273922 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 2364998271 # Total bandwidth to/from this memory (bytes/s)

30system.cpu.dtb.read_hits 0 # DTB read hits
31system.cpu.dtb.read_misses 0 # DTB read misses
32system.cpu.dtb.read_accesses 0 # DTB read accesses
33system.cpu.dtb.write_hits 0 # DTB write hits
34system.cpu.dtb.write_misses 0 # DTB write misses
35system.cpu.dtb.write_accesses 0 # DTB write accesses
36system.cpu.dtb.hits 0 # DTB hits
37system.cpu.dtb.misses 0 # DTB misses
38system.cpu.dtb.accesses 0 # DTB accesses
39system.cpu.itb.read_hits 0 # DTB read hits
40system.cpu.itb.read_misses 0 # DTB read misses
41system.cpu.itb.read_accesses 0 # DTB read accesses
42system.cpu.itb.write_hits 0 # DTB write hits
43system.cpu.itb.write_misses 0 # DTB write misses
44system.cpu.itb.write_accesses 0 # DTB write accesses
45system.cpu.itb.hits 0 # DTB hits
46system.cpu.itb.misses 0 # DTB misses
47system.cpu.itb.accesses 0 # DTB accesses
48system.cpu.workload.num_syscalls 8 # Number of system calls

49system.cpu.numCycles 24958 # number of cpu cycles simulated

49system.cpu.numCycles 26034 # number of cpu cycles simulated

50system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
51system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed

52system.cpu.BPredUnit.lookups 2172 # Number of BP lookups
53system.cpu.BPredUnit.condPredicted 1452 # Number of conditional branches predicted
54system.cpu.BPredUnit.condIncorrect 447 # Number of conditional branches incorrect
55system.cpu.BPredUnit.BTBLookups 1660 # Number of BTB lookups
56system.cpu.BPredUnit.BTBHits 457 # Number of BTB hits

52system.cpu.BPredUnit.lookups 2148 # Number of BP lookups
53system.cpu.BPredUnit.condPredicted 1448 # Number of conditional branches predicted
54system.cpu.BPredUnit.condIncorrect 450 # Number of conditional branches incorrect
55system.cpu.BPredUnit.BTBLookups 1662 # Number of BTB lookups
56system.cpu.BPredUnit.BTBHits 462 # Number of BTB hits

57system.cpu.BPredUnit.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.

58system.cpu.BPredUnit.usedRAS 278 # Number of times the RAS was used to get a target.
59system.cpu.BPredUnit.RASInCorrect 71 # Number of incorrect RAS predictions.
60system.cpu.fetch.icacheStallCycles 8142 # Number of cycles fetch is stalled on an Icache miss
61system.cpu.fetch.Insts 13207 # Number of instructions fetch has processed
62system.cpu.fetch.Branches 2172 # Number of branches that fetch encountered
63system.cpu.fetch.predictedBranches 735 # Number of branches that fetch has predicted taken
64system.cpu.fetch.Cycles 3199 # Number of cycles fetch has run and was not squashing or blocked
65system.cpu.fetch.SquashCycles 1325 # Number of cycles fetch has spent squashing
66system.cpu.fetch.BlockedCycles 670 # Number of cycles fetch has spent blocked

58system.cpu.BPredUnit.usedRAS 263 # Number of times the RAS was used to get a target.
59system.cpu.BPredUnit.RASInCorrect 67 # Number of incorrect RAS predictions.
60system.cpu.fetch.icacheStallCycles 8866 # Number of cycles fetch is stalled on an Icache miss
61system.cpu.fetch.Insts 13061 # Number of instructions fetch has processed
62system.cpu.fetch.Branches 2148 # Number of branches that fetch encountered
63system.cpu.fetch.predictedBranches 725 # Number of branches that fetch has predicted taken
64system.cpu.fetch.Cycles 3176 # Number of cycles fetch has run and was not squashing or blocked
65system.cpu.fetch.SquashCycles 1340 # Number of cycles fetch has spent squashing
66system.cpu.fetch.BlockedCycles 826 # Number of cycles fetch has spent blocked

67system.cpu.fetch.MiscStallCycles 1 # Number of cycles fetch has spent waiting on interrupts, or bad addresses, or out of MSHRs
68system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps

69system.cpu.fetch.CacheLines 1938 # Number of cache lines fetched
70system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed
71system.cpu.fetch.rateDist::samples 13025 # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::mean 1.013973 # Number of instructions fetched each cycle (Total)
73system.cpu.fetch.rateDist::stdev 2.329859 # Number of instructions fetched each cycle (Total)

69system.cpu.fetch.CacheLines 1948 # Number of cache lines fetched
70system.cpu.fetch.IcacheSquashes 270 # Number of outstanding Icache misses that were squashed
71system.cpu.fetch.rateDist::samples 13893 # Number of instructions fetched each cycle (Total)
72system.cpu.fetch.rateDist::mean 0.940114 # Number of instructions fetched each cycle (Total)
73system.cpu.fetch.rateDist::stdev 2.257377 # Number of instructions fetched each cycle (Total)

74system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)

75system.cpu.fetch.rateDist::0 9826 75.44% 75.44% # Number of instructions fetched each cycle (Total)
76system.cpu.fetch.rateDist::1 1298 9.97% 85.40% # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.rateDist::2 113 0.87% 86.27% # Number of instructions fetched each cycle (Total)
78system.cpu.fetch.rateDist::3 139 1.07% 87.34% # Number of instructions fetched each cycle (Total)
79system.cpu.fetch.rateDist::4 293 2.25% 89.59% # Number of instructions fetched each cycle (Total)
80system.cpu.fetch.rateDist::5 102 0.78% 90.37% # Number of instructions fetched each cycle (Total)
81system.cpu.fetch.rateDist::6 157 1.21% 91.58% # Number of instructions fetched each cycle (Total)
82system.cpu.fetch.rateDist::7 134 1.03% 92.61% # Number of instructions fetched each cycle (Total)
83system.cpu.fetch.rateDist::8 963 7.39% 100.00% # Number of instructions fetched each cycle (Total)

75system.cpu.fetch.rateDist::0 10717 77.14% 77.14% # Number of instructions fetched each cycle (Total)
76system.cpu.fetch.rateDist::1 1298 9.34% 86.48% # Number of instructions fetched each cycle (Total)
77system.cpu.fetch.rateDist::2 110 0.79% 87.27% # Number of instructions fetched each cycle (Total)
78system.cpu.fetch.rateDist::3 134 0.96% 88.24% # Number of instructions fetched each cycle (Total)
79system.cpu.fetch.rateDist::4 300 2.16% 90.40% # Number of instructions fetched each cycle (Total)
80system.cpu.fetch.rateDist::5 103 0.74% 91.14% # Number of instructions fetched each cycle (Total)
81system.cpu.fetch.rateDist::6 148 1.07% 92.20% # Number of instructions fetched each cycle (Total)
82system.cpu.fetch.rateDist::7 126 0.91% 93.11% # Number of instructions fetched each cycle (Total)
83system.cpu.fetch.rateDist::8 957 6.89% 100.00% # Number of instructions fetched each cycle (Total)

84system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
85system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
86system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)

87system.cpu.fetch.rateDist::total 13025 # Number of instructions fetched each cycle (Total)
88system.cpu.fetch.branchRate 0.087026 # Number of branch fetches per cycle
89system.cpu.fetch.rate 0.529169 # Number of inst fetches per cycle
90system.cpu.decode.IdleCycles 8327 # Number of cycles decode is idle
91system.cpu.decode.BlockedCycles 818 # Number of cycles decode is blocked
92system.cpu.decode.RunCycles 3014 # Number of cycles decode is running
93system.cpu.decode.UnblockCycles 41 # Number of cycles decode is unblocking
94system.cpu.decode.SquashCycles 825 # Number of cycles decode is squashing
95system.cpu.decode.BranchResolved 136 # Number of times decode resolved a branch
96system.cpu.decode.BranchMispred 46 # Number of times decode detected a branch misprediction
97system.cpu.decode.DecodedInsts 12256 # Number of instructions handled by decode

87system.cpu.fetch.rateDist::total 13893 # Number of instructions fetched each cycle (Total)
88system.cpu.fetch.branchRate 0.082507 # Number of branch fetches per cycle
89system.cpu.fetch.rate 0.501690 # Number of inst fetches per cycle
90system.cpu.decode.IdleCycles 9037 # Number of cycles decode is idle
91system.cpu.decode.BlockedCycles 974 # Number of cycles decode is blocked
92system.cpu.decode.RunCycles 2996 # Number of cycles decode is running
93system.cpu.decode.UnblockCycles 51 # Number of cycles decode is unblocking
94system.cpu.decode.SquashCycles 835 # Number of cycles decode is squashing
95system.cpu.decode.BranchResolved 145 # Number of times decode resolved a branch
96system.cpu.decode.BranchMispred 47 # Number of times decode detected a branch misprediction
97system.cpu.decode.DecodedInsts 12168 # Number of instructions handled by decode

98system.cpu.decode.SquashedInsts 188 # Number of squashed instructions handled by decode

99system.cpu.rename.SquashCycles 825 # Number of cycles rename is squashing
100system.cpu.rename.IdleCycles 8509 # Number of cycles rename is idle
101system.cpu.rename.BlockCycles 222 # Number of cycles rename is blocking
102system.cpu.rename.serializeStallCycles 499 # count of cycles rename stalled for serializing inst
103system.cpu.rename.RunCycles 2873 # Number of cycles rename is running
104system.cpu.rename.UnblockCycles 97 # Number of cycles rename is unblocking
105system.cpu.rename.RenamedInsts 11712 # Number of instructions processed by rename
106system.cpu.rename.LSQFullEvents 88 # Number of times rename has blocked due to LSQ full
107system.cpu.rename.RenamedOperands 7146 # Number of destination operands rename has renamed
108system.cpu.rename.RenameLookups 13901 # Number of register rename lookups that rename has made
109system.cpu.rename.int_rename_lookups 13897 # Number of integer rename lookups

99system.cpu.rename.SquashCycles 835 # Number of cycles rename is squashing
100system.cpu.rename.IdleCycles 9227 # Number of cycles rename is idle
101system.cpu.rename.BlockCycles 288 # Number of cycles rename is blocking
102system.cpu.rename.serializeStallCycles 540 # count of cycles rename stalled for serializing inst
103system.cpu.rename.RunCycles 2860 # Number of cycles rename is running
104system.cpu.rename.UnblockCycles 143 # Number of cycles rename is unblocking
105system.cpu.rename.RenamedInsts 11638 # Number of instructions processed by rename
106system.cpu.rename.LSQFullEvents 129 # Number of times rename has blocked due to LSQ full
107system.cpu.rename.RenamedOperands 7046 # Number of destination operands rename has renamed
108system.cpu.rename.RenameLookups 13805 # Number of register rename lookups that rename has made
109system.cpu.rename.int_rename_lookups 13801 # Number of integer rename lookups

110system.cpu.rename.fp_rename_lookups 4 # Number of floating rename lookups
111system.cpu.rename.CommittedMaps 3410 # Number of HB maps that are committed

112system.cpu.rename.UndoneMaps 3736 # Number of HB maps that are undone due to squashing
113system.cpu.rename.serializingInsts 18 # count of serializing insts renamed
114system.cpu.rename.tempSerializingInsts 11 # count of temporary serializing insts renamed
115system.cpu.rename.skidInsts 266 # count of insts added to the skid buffer
116system.cpu.memDep0.insertedLoads 2476 # Number of loads inserted to the mem dependence unit.

112system.cpu.rename.UndoneMaps 3636 # Number of HB maps that are undone due to squashing
113system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
114system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
115system.cpu.rename.skidInsts 308 # count of insts added to the skid buffer
116system.cpu.memDep0.insertedLoads 2447 # Number of loads inserted to the mem dependence unit.

117system.cpu.memDep0.insertedStores 1180 # Number of stores inserted to the mem dependence unit.
118system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
119system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.

120system.cpu.iq.iqInstsAdded 9032 # Number of instructions added to the IQ (excludes non-spec)
121system.cpu.iq.iqNonSpecInstsAdded 13 # Number of non-speculative instructions added to the IQ
122system.cpu.iq.iqInstsIssued 8121 # Number of instructions issued
123system.cpu.iq.iqSquashedInstsIssued 52 # Number of squashed instructions issued
124system.cpu.iq.iqSquashedInstsExamined 3346 # Number of squashed instructions iterated over during squash; mainly for profiling
125system.cpu.iq.iqSquashedOperandsExamined 2009 # Number of squashed operands that are examined and possibly removed from graph
126system.cpu.iq.iqSquashedNonSpecRemoved 3 # Number of squashed non-spec instructions that were removed
127system.cpu.iq.issued_per_cycle::samples 13025 # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::mean 0.623493 # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::stdev 1.295831 # Number of insts issued each cycle

120system.cpu.iq.iqInstsAdded 9050 # Number of instructions added to the IQ (excludes non-spec)
121system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
122system.cpu.iq.iqInstsIssued 8137 # Number of instructions issued
123system.cpu.iq.iqSquashedInstsIssued 46 # Number of squashed instructions issued
124system.cpu.iq.iqSquashedInstsExamined 3435 # Number of squashed instructions iterated over during squash; mainly for profiling
125system.cpu.iq.iqSquashedOperandsExamined 1984 # Number of squashed operands that are examined and possibly removed from graph
126system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
127system.cpu.iq.issued_per_cycle::samples 13893 # Number of insts issued each cycle
128system.cpu.iq.issued_per_cycle::mean 0.585691 # Number of insts issued each cycle
129system.cpu.iq.issued_per_cycle::stdev 1.249798 # Number of insts issued each cycle

130system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle

131system.cpu.iq.issued_per_cycle::0 9566 73.44% 73.44% # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::1 1360 10.44% 83.88% # Number of insts issued each cycle
133system.cpu.iq.issued_per_cycle::2 840 6.45% 90.33% # Number of insts issued each cycle
134system.cpu.iq.issued_per_cycle::3 535 4.11% 94.44% # Number of insts issued each cycle
135system.cpu.iq.issued_per_cycle::4 357 2.74% 97.18% # Number of insts issued each cycle
136system.cpu.iq.issued_per_cycle::5 221 1.70% 98.88% # Number of insts issued each cycle
137system.cpu.iq.issued_per_cycle::6 96 0.74% 99.62% # Number of insts issued each cycle
138system.cpu.iq.issued_per_cycle::7 33 0.25% 99.87% # Number of insts issued each cycle
139system.cpu.iq.issued_per_cycle::8 17 0.13% 100.00% # Number of insts issued each cycle

131system.cpu.iq.issued_per_cycle::0 10352 74.51% 74.51% # Number of insts issued each cycle
132system.cpu.iq.issued_per_cycle::1 1446 10.41% 84.92% # Number of insts issued each cycle
133system.cpu.iq.issued_per_cycle::2 850 6.12% 91.04% # Number of insts issued each cycle
134system.cpu.iq.issued_per_cycle::3 537 3.87% 94.90% # Number of insts issued each cycle
135system.cpu.iq.issued_per_cycle::4 350 2.52% 97.42% # Number of insts issued each cycle
136system.cpu.iq.issued_per_cycle::5 226 1.63% 99.05% # Number of insts issued each cycle
137system.cpu.iq.issued_per_cycle::6 89 0.64% 99.69% # Number of insts issued each cycle
138system.cpu.iq.issued_per_cycle::7 28 0.20% 99.89% # Number of insts issued each cycle
139system.cpu.iq.issued_per_cycle::8 15 0.11% 100.00% # Number of insts issued each cycle

140system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
141system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
142system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle

143system.cpu.iq.issued_per_cycle::total 13025 # Number of insts issued each cycle

143system.cpu.iq.issued_per_cycle::total 13893 # Number of insts issued each cycle

144system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available

145system.cpu.iq.fu_full::IntAlu 4 2.63% 2.63% # attempts to use FU when none available
146system.cpu.iq.fu_full::IntMult 0 0.00% 2.63% # attempts to use FU when none available
147system.cpu.iq.fu_full::IntDiv 0 0.00% 2.63% # attempts to use FU when none available
148system.cpu.iq.fu_full::FloatAdd 0 0.00% 2.63% # attempts to use FU when none available
149system.cpu.iq.fu_full::FloatCmp 0 0.00% 2.63% # attempts to use FU when none available
150system.cpu.iq.fu_full::FloatCvt 0 0.00% 2.63% # attempts to use FU when none available
151system.cpu.iq.fu_full::FloatMult 0 0.00% 2.63% # attempts to use FU when none available
152system.cpu.iq.fu_full::FloatDiv 0 0.00% 2.63% # attempts to use FU when none available
153system.cpu.iq.fu_full::FloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdAdd 0 0.00% 2.63% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 2.63% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdAlu 0 0.00% 2.63% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdCmp 0 0.00% 2.63% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdCvt 0 0.00% 2.63% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdMisc 0 0.00% 2.63% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdMult 0 0.00% 2.63% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 2.63% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdShift 0 0.00% 2.63% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 2.63% # attempts to use FU when none available
164system.cpu.iq.fu_full::SimdSqrt 0 0.00% 2.63% # attempts to use FU when none available
165system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 2.63% # attempts to use FU when none available
166system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 2.63% # attempts to use FU when none available
167system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 2.63% # attempts to use FU when none available
168system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 2.63% # attempts to use FU when none available
169system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 2.63% # attempts to use FU when none available
170system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 2.63% # attempts to use FU when none available
171system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 2.63% # attempts to use FU when none available
172system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 2.63% # attempts to use FU when none available
173system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 2.63% # attempts to use FU when none available
174system.cpu.iq.fu_full::MemRead 96 63.16% 65.79% # attempts to use FU when none available

145system.cpu.iq.fu_full::IntAlu 3 1.97% 1.97% # attempts to use FU when none available
146system.cpu.iq.fu_full::IntMult 0 0.00% 1.97% # attempts to use FU when none available
147system.cpu.iq.fu_full::IntDiv 0 0.00% 1.97% # attempts to use FU when none available
148system.cpu.iq.fu_full::FloatAdd 0 0.00% 1.97% # attempts to use FU when none available
149system.cpu.iq.fu_full::FloatCmp 0 0.00% 1.97% # attempts to use FU when none available
150system.cpu.iq.fu_full::FloatCvt 0 0.00% 1.97% # attempts to use FU when none available
151system.cpu.iq.fu_full::FloatMult 0 0.00% 1.97% # attempts to use FU when none available
152system.cpu.iq.fu_full::FloatDiv 0 0.00% 1.97% # attempts to use FU when none available
153system.cpu.iq.fu_full::FloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
154system.cpu.iq.fu_full::SimdAdd 0 0.00% 1.97% # attempts to use FU when none available
155system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 1.97% # attempts to use FU when none available
156system.cpu.iq.fu_full::SimdAlu 0 0.00% 1.97% # attempts to use FU when none available
157system.cpu.iq.fu_full::SimdCmp 0 0.00% 1.97% # attempts to use FU when none available
158system.cpu.iq.fu_full::SimdCvt 0 0.00% 1.97% # attempts to use FU when none available
159system.cpu.iq.fu_full::SimdMisc 0 0.00% 1.97% # attempts to use FU when none available
160system.cpu.iq.fu_full::SimdMult 0 0.00% 1.97% # attempts to use FU when none available
161system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 1.97% # attempts to use FU when none available
162system.cpu.iq.fu_full::SimdShift 0 0.00% 1.97% # attempts to use FU when none available
163system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 1.97% # attempts to use FU when none available
164system.cpu.iq.fu_full::SimdSqrt 0 0.00% 1.97% # attempts to use FU when none available
165system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 1.97% # attempts to use FU when none available
166system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 1.97% # attempts to use FU when none available
167system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 1.97% # attempts to use FU when none available
168system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 1.97% # attempts to use FU when none available
169system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 1.97% # attempts to use FU when none available
170system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 1.97% # attempts to use FU when none available
171system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 1.97% # attempts to use FU when none available
172system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 1.97% # attempts to use FU when none available
173system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 1.97% # attempts to use FU when none available
174system.cpu.iq.fu_full::MemRead 97 63.82% 65.79% # attempts to use FU when none available

175system.cpu.iq.fu_full::MemWrite 52 34.21% 100.00% # attempts to use FU when none available
176system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
177system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
178system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued

179system.cpu.iq.FU_type_0::IntAlu 4783 58.90% 58.90% # Type of FU issued
180system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.95% # Type of FU issued
181system.cpu.iq.FU_type_0::IntDiv 2 0.02% 58.97% # Type of FU issued
182system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.00% # Type of FU issued
183system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.00% # Type of FU issued
184system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.00% # Type of FU issued
185system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.00% # Type of FU issued
186system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.00% # Type of FU issued
187system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.00% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.00% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.00% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.00% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.00% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.00% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.00% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.00% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.00% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.00% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.00% # Type of FU issued
198system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.00% # Type of FU issued
199system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.00% # Type of FU issued
200system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.00% # Type of FU issued
201system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.00% # Type of FU issued
202system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.00% # Type of FU issued
203system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.00% # Type of FU issued
204system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.00% # Type of FU issued
205system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.00% # Type of FU issued
206system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.00% # Type of FU issued
207system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.00% # Type of FU issued
208system.cpu.iq.FU_type_0::MemRead 2243 27.62% 86.61% # Type of FU issued
209system.cpu.iq.FU_type_0::MemWrite 1087 13.39% 100.00% # Type of FU issued

179system.cpu.iq.FU_type_0::IntAlu 4825 59.30% 59.30% # Type of FU issued
180system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.36% # Type of FU issued
181system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.38% # Type of FU issued
182system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.41% # Type of FU issued
183system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.41% # Type of FU issued
184system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.41% # Type of FU issued
185system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.41% # Type of FU issued
186system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.41% # Type of FU issued
187system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.41% # Type of FU issued
188system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.41% # Type of FU issued
189system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.41% # Type of FU issued
190system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.41% # Type of FU issued
191system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.41% # Type of FU issued
192system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.41% # Type of FU issued
193system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.41% # Type of FU issued
194system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.41% # Type of FU issued
195system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.41% # Type of FU issued
196system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.41% # Type of FU issued
197system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.41% # Type of FU issued
198system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.41% # Type of FU issued
199system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.41% # Type of FU issued
200system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.41% # Type of FU issued
201system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.41% # Type of FU issued
202system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.41% # Type of FU issued
203system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.41% # Type of FU issued
204system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.41% # Type of FU issued
205system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.41% # Type of FU issued
206system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.41% # Type of FU issued
207system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.41% # Type of FU issued
208system.cpu.iq.FU_type_0::MemRead 2212 27.18% 86.59% # Type of FU issued
209system.cpu.iq.FU_type_0::MemWrite 1091 13.41% 100.00% # Type of FU issued

210system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
211system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued

212system.cpu.iq.FU_type_0::total 8121 # Type of FU issued
213system.cpu.iq.rate 0.325387 # Inst issue rate

212system.cpu.iq.FU_type_0::total 8137 # Type of FU issued
213system.cpu.iq.rate 0.312553 # Inst issue rate

214system.cpu.iq.fu_busy_cnt 152 # FU busy when requested

215system.cpu.iq.fu_busy_rate 0.018717 # FU busy rate (busy events/executed inst)
216system.cpu.iq.int_inst_queue_reads 29467 # Number of integer instruction queue reads
217system.cpu.iq.int_inst_queue_writes 12396 # Number of integer instruction queue writes
218system.cpu.iq.int_inst_queue_wakeup_accesses 7292 # Number of integer instruction queue wakeup accesses

215system.cpu.iq.fu_busy_rate 0.018680 # FU busy rate (busy events/executed inst)
216system.cpu.iq.int_inst_queue_reads 30361 # Number of integer instruction queue reads
217system.cpu.iq.int_inst_queue_writes 12504 # Number of integer instruction queue writes
218system.cpu.iq.int_inst_queue_wakeup_accesses 7339 # Number of integer instruction queue wakeup accesses

219system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
220system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
221system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses

222system.cpu.iq.int_alu_accesses 8271 # Number of integer alu accesses

222system.cpu.iq.int_alu_accesses 8287 # Number of integer alu accesses

223system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses

224system.cpu.iew.lsq.thread0.forwLoads 61 # Number of loads that had data forwarded from stores

224system.cpu.iew.lsq.thread0.forwLoads 60 # Number of loads that had data forwarded from stores

225system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address

226system.cpu.iew.lsq.thread0.squashedLoads 1312 # Number of loads squashed
227system.cpu.iew.lsq.thread0.ignoredResponses 4 # Number of memory responses ignored because the instruction is squashed
228system.cpu.iew.lsq.thread0.memOrderViolation 7 # Number of memory ordering violations

226system.cpu.iew.lsq.thread0.squashedLoads 1283 # Number of loads squashed
227system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
228system.cpu.iew.lsq.thread0.memOrderViolation 9 # Number of memory ordering violations

229system.cpu.iew.lsq.thread0.squashedStores 255 # Number of stores squashed
230system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
231system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
232system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
233system.cpu.iew.lsq.thread0.cacheBlocked 0 # Number of times an access to memory failed due to the cache being blocked
234system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle

235system.cpu.iew.iewSquashCycles 825 # Number of cycles IEW is squashing
236system.cpu.iew.iewBlockCycles 149 # Number of cycles IEW is blocking
237system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking
238system.cpu.iew.iewDispatchedInsts 10514 # Number of instructions dispatched to IQ
239system.cpu.iew.iewDispSquashedInsts 112 # Number of squashed instructions skipped by dispatch
240system.cpu.iew.iewDispLoadInsts 2476 # Number of dispatched load instructions

235system.cpu.iew.iewSquashCycles 835 # Number of cycles IEW is squashing
236system.cpu.iew.iewBlockCycles 148 # Number of cycles IEW is blocking
237system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
238system.cpu.iew.iewDispatchedInsts 10551 # Number of instructions dispatched to IQ
239system.cpu.iew.iewDispSquashedInsts 78 # Number of squashed instructions skipped by dispatch
240system.cpu.iew.iewDispLoadInsts 2447 # Number of dispatched load instructions

241system.cpu.iew.iewDispStoreInsts 1180 # Number of dispatched store instructions

242system.cpu.iew.iewDispNonSpecInsts 13 # Number of dispatched non-speculative instructions

242system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions

243system.cpu.iew.iewIQFullEvents 2 # Number of times the IQ has become full, causing a stall
244system.cpu.iew.iewLSQFullEvents 1 # Number of times the LSQ has become full, causing a stall

245system.cpu.iew.memOrderViolationEvents 7 # Number of memory order violations
246system.cpu.iew.predictedTakenIncorrect 107 # Number of branches that were predicted taken incorrectly
247system.cpu.iew.predictedNotTakenIncorrect 373 # Number of branches that were predicted not taken incorrectly
248system.cpu.iew.branchMispredicts 480 # Number of branch mispredicts detected at execute
249system.cpu.iew.iewExecutedInsts 7766 # Number of executed instructions
250system.cpu.iew.iewExecLoadInsts 2126 # Number of load instructions executed
251system.cpu.iew.iewExecSquashedInsts 355 # Number of squashed instructions skipped in execute

245system.cpu.iew.memOrderViolationEvents 9 # Number of memory order violations
246system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
247system.cpu.iew.predictedNotTakenIncorrect 378 # Number of branches that were predicted not taken incorrectly
248system.cpu.iew.branchMispredicts 479 # Number of branch mispredicts detected at execute
249system.cpu.iew.iewExecutedInsts 7784 # Number of executed instructions
250system.cpu.iew.iewExecLoadInsts 2096 # Number of load instructions executed
251system.cpu.iew.iewExecSquashedInsts 353 # Number of squashed instructions skipped in execute

252system.cpu.iew.exec_swp 0 # number of swp insts executed

253system.cpu.iew.exec_nop 1469 # number of nop insts executed
254system.cpu.iew.exec_refs 3191 # number of memory reference insts executed
255system.cpu.iew.exec_branches 1304 # Number of branches executed
256system.cpu.iew.exec_stores 1065 # Number of stores executed
257system.cpu.iew.exec_rate 0.311163 # Inst execution rate
258system.cpu.iew.wb_sent 7392 # cumulative count of insts sent to commit
259system.cpu.iew.wb_count 7294 # cumulative count of insts written-back
260system.cpu.iew.wb_producers 2836 # num instructions producing a value
261system.cpu.iew.wb_consumers 4075 # num instructions consuming a value

253system.cpu.iew.exec_nop 1489 # number of nop insts executed
254system.cpu.iew.exec_refs 3163 # number of memory reference insts executed
255system.cpu.iew.exec_branches 1325 # Number of branches executed
256system.cpu.iew.exec_stores 1067 # Number of stores executed
257system.cpu.iew.exec_rate 0.298994 # Inst execution rate
258system.cpu.iew.wb_sent 7431 # cumulative count of insts sent to commit
259system.cpu.iew.wb_count 7341 # cumulative count of insts written-back
260system.cpu.iew.wb_producers 2840 # num instructions producing a value
261system.cpu.iew.wb_consumers 4066 # num instructions consuming a value

262system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ

263system.cpu.iew.wb_rate 0.292251 # insts written-back per cycle
264system.cpu.iew.wb_fanout 0.695951 # average fanout of values written-back

263system.cpu.iew.wb_rate 0.281977 # insts written-back per cycle
264system.cpu.iew.wb_fanout 0.698475 # average fanout of values written-back

265system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
266system.cpu.commit.commitCommittedInsts 5826 # The number of committed instructions
267system.cpu.commit.commitCommittedOps 5826 # The number of committed instructions

268system.cpu.commit.commitSquashedInsts 4683 # The number of squashed insts skipped by commit

268system.cpu.commit.commitSquashedInsts 4721 # The number of squashed insts skipped by commit

269system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards

270system.cpu.commit.branchMispredicts 402 # The number of times a branch was mispredicted
271system.cpu.commit.committed_per_cycle::samples 12200 # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::mean 0.477541 # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::stdev 1.256570 # Number of insts commited each cycle

270system.cpu.commit.branchMispredicts 404 # The number of times a branch was mispredicted
271system.cpu.commit.committed_per_cycle::samples 13058 # Number of insts commited each cycle
272system.cpu.commit.committed_per_cycle::mean 0.446163 # Number of insts commited each cycle
273system.cpu.commit.committed_per_cycle::stdev 1.225344 # Number of insts commited each cycle

274system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle

275system.cpu.commit.committed_per_cycle::0 9781 80.17% 80.17% # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::1 1000 8.20% 88.37% # Number of insts commited each cycle
277system.cpu.commit.committed_per_cycle::2 629 5.16% 93.52% # Number of insts commited each cycle
278system.cpu.commit.committed_per_cycle::3 333 2.73% 96.25% # Number of insts commited each cycle
279system.cpu.commit.committed_per_cycle::4 158 1.30% 97.55% # Number of insts commited each cycle
280system.cpu.commit.committed_per_cycle::5 93 0.76% 98.31% # Number of insts commited each cycle
281system.cpu.commit.committed_per_cycle::6 67 0.55% 98.86% # Number of insts commited each cycle
282system.cpu.commit.committed_per_cycle::7 42 0.34% 99.20% # Number of insts commited each cycle
283system.cpu.commit.committed_per_cycle::8 97 0.80% 100.00% # Number of insts commited each cycle

275system.cpu.commit.committed_per_cycle::0 10619 81.32% 81.32% # Number of insts commited each cycle
276system.cpu.commit.committed_per_cycle::1 1036 7.93% 89.26% # Number of insts commited each cycle
277system.cpu.commit.committed_per_cycle::2 643 4.92% 94.18% # Number of insts commited each cycle
278system.cpu.commit.committed_per_cycle::3 305 2.34% 96.52% # Number of insts commited each cycle
279system.cpu.commit.committed_per_cycle::4 154 1.18% 97.69% # Number of insts commited each cycle
280system.cpu.commit.committed_per_cycle::5 84 0.64% 98.34% # Number of insts commited each cycle
281system.cpu.commit.committed_per_cycle::6 72 0.55% 98.89% # Number of insts commited each cycle
282system.cpu.commit.committed_per_cycle::7 39 0.30% 99.19% # Number of insts commited each cycle
283system.cpu.commit.committed_per_cycle::8 106 0.81% 100.00% # Number of insts commited each cycle

284system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
285system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
286system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle

287system.cpu.commit.committed_per_cycle::total 12200 # Number of insts commited each cycle

287system.cpu.commit.committed_per_cycle::total 13058 # Number of insts commited each cycle

288system.cpu.commit.committedInsts 5826 # Number of instructions committed
289system.cpu.commit.committedOps 5826 # Number of ops (including micro ops) committed
290system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
291system.cpu.commit.refs 2089 # Number of memory references committed
292system.cpu.commit.loads 1164 # Number of loads committed
293system.cpu.commit.membars 0 # Number of memory barriers committed
294system.cpu.commit.branches 916 # Number of branches committed
295system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
296system.cpu.commit.int_insts 5124 # Number of committed integer instructions.
297system.cpu.commit.function_calls 87 # Number of function calls committed.

298system.cpu.commit.bw_lim_events 97 # number cycles where commit BW limit reached

298system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached

299system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits

300system.cpu.rob.rob_reads 22599 # The number of ROB reads
301system.cpu.rob.rob_writes 21853 # The number of ROB writes
302system.cpu.timesIdled 249 # Number of times that the entire CPU went into an idle state and unscheduled itself
303system.cpu.idleCycles 11933 # Total number of cycles that the CPU has spent unscheduled due to idling

300system.cpu.rob.rob_reads 23486 # The number of ROB reads
301system.cpu.rob.rob_writes 21936 # The number of ROB writes
302system.cpu.timesIdled 270 # Number of times that the entire CPU went into an idle state and unscheduled itself
303system.cpu.idleCycles 12141 # Total number of cycles that the CPU has spent unscheduled due to idling

304system.cpu.committedInsts 5169 # Number of Instructions Simulated
305system.cpu.committedOps 5169 # Number of Ops (including micro ops) Simulated
306system.cpu.committedInsts_total 5169 # Number of Instructions Simulated

307system.cpu.cpi 4.828400 # CPI: Cycles Per Instruction
308system.cpu.cpi_total 4.828400 # CPI: Total CPI of All Threads
309system.cpu.ipc 0.207108 # IPC: Instructions Per Cycle
310system.cpu.ipc_total 0.207108 # IPC: Total IPC of All Threads
311system.cpu.int_regfile_reads 10560 # number of integer regfile reads
312system.cpu.int_regfile_writes 5130 # number of integer regfile writes

307system.cpu.cpi 5.036564 # CPI: Cycles Per Instruction
308system.cpu.cpi_total 5.036564 # CPI: Total CPI of All Threads
309system.cpu.ipc 0.198548 # IPC: Instructions Per Cycle
310system.cpu.ipc_total 0.198548 # IPC: Total IPC of All Threads
311system.cpu.int_regfile_reads 10600 # number of integer regfile reads
312system.cpu.int_regfile_writes 5152 # number of integer regfile writes

313system.cpu.fp_regfile_reads 3 # number of floating regfile reads
314system.cpu.fp_regfile_writes 1 # number of floating regfile writes

315system.cpu.misc_regfile_reads 150 # number of misc regfile reads

315system.cpu.misc_regfile_reads 155 # number of misc regfile reads

316system.cpu.icache.replacements 17 # number of replacements

317system.cpu.icache.tagsinuse 163.784522 # Cycle average of tags in use
318system.cpu.icache.total_refs 1503 # Total number of references to valid blocks.
319system.cpu.icache.sampled_refs 341 # Sample count of references to valid blocks.
320system.cpu.icache.avg_refs 4.407625 # Average number of references to valid blocks.

317system.cpu.icache.tagsinuse 163.172601 # Cycle average of tags in use
318system.cpu.icache.total_refs 1511 # Total number of references to valid blocks.
319system.cpu.icache.sampled_refs 343 # Sample count of references to valid blocks.
320system.cpu.icache.avg_refs 4.405248 # Average number of references to valid blocks.

321system.cpu.icache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

322system.cpu.icache.occ_blocks::cpu.inst 163.784522 # Average occupied blocks per requestor
323system.cpu.icache.occ_percent::cpu.inst 0.079973 # Average percentage of cache occupancy
324system.cpu.icache.occ_percent::total 0.079973 # Average percentage of cache occupancy
325system.cpu.icache.ReadReq_hits::cpu.inst 1503 # number of ReadReq hits
326system.cpu.icache.ReadReq_hits::total 1503 # number of ReadReq hits
327system.cpu.icache.demand_hits::cpu.inst 1503 # number of demand (read+write) hits
328system.cpu.icache.demand_hits::total 1503 # number of demand (read+write) hits
329system.cpu.icache.overall_hits::cpu.inst 1503 # number of overall hits
330system.cpu.icache.overall_hits::total 1503 # number of overall hits
331system.cpu.icache.ReadReq_misses::cpu.inst 435 # number of ReadReq misses
332system.cpu.icache.ReadReq_misses::total 435 # number of ReadReq misses
333system.cpu.icache.demand_misses::cpu.inst 435 # number of demand (read+write) misses
334system.cpu.icache.demand_misses::total 435 # number of demand (read+write) misses
335system.cpu.icache.overall_misses::cpu.inst 435 # number of overall misses
336system.cpu.icache.overall_misses::total 435 # number of overall misses
337system.cpu.icache.ReadReq_miss_latency::cpu.inst 15599500 # number of ReadReq miss cycles
338system.cpu.icache.ReadReq_miss_latency::total 15599500 # number of ReadReq miss cycles
339system.cpu.icache.demand_miss_latency::cpu.inst 15599500 # number of demand (read+write) miss cycles
340system.cpu.icache.demand_miss_latency::total 15599500 # number of demand (read+write) miss cycles
341system.cpu.icache.overall_miss_latency::cpu.inst 15599500 # number of overall miss cycles
342system.cpu.icache.overall_miss_latency::total 15599500 # number of overall miss cycles
343system.cpu.icache.ReadReq_accesses::cpu.inst 1938 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 1938 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 1938 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 1938 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 1938 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 1938 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224458 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.224458 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.224458 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.224458 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.224458 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.224458 # miss rate for overall accesses
355system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35860.919540 # average ReadReq miss latency
356system.cpu.icache.ReadReq_avg_miss_latency::total 35860.919540 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency
358system.cpu.icache.demand_avg_miss_latency::total 35860.919540 # average overall miss latency
359system.cpu.icache.overall_avg_miss_latency::cpu.inst 35860.919540 # average overall miss latency
360system.cpu.icache.overall_avg_miss_latency::total 35860.919540 # average overall miss latency

322system.cpu.icache.occ_blocks::cpu.inst 163.172601 # Average occupied blocks per requestor
323system.cpu.icache.occ_percent::cpu.inst 0.079674 # Average percentage of cache occupancy
324system.cpu.icache.occ_percent::total 0.079674 # Average percentage of cache occupancy
325system.cpu.icache.ReadReq_hits::cpu.inst 1511 # number of ReadReq hits
326system.cpu.icache.ReadReq_hits::total 1511 # number of ReadReq hits
327system.cpu.icache.demand_hits::cpu.inst 1511 # number of demand (read+write) hits
328system.cpu.icache.demand_hits::total 1511 # number of demand (read+write) hits
329system.cpu.icache.overall_hits::cpu.inst 1511 # number of overall hits
330system.cpu.icache.overall_hits::total 1511 # number of overall hits
331system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
332system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
333system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
334system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
335system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
336system.cpu.icache.overall_misses::total 437 # number of overall misses
337system.cpu.icache.ReadReq_miss_latency::cpu.inst 15987000 # number of ReadReq miss cycles
338system.cpu.icache.ReadReq_miss_latency::total 15987000 # number of ReadReq miss cycles
339system.cpu.icache.demand_miss_latency::cpu.inst 15987000 # number of demand (read+write) miss cycles
340system.cpu.icache.demand_miss_latency::total 15987000 # number of demand (read+write) miss cycles
341system.cpu.icache.overall_miss_latency::cpu.inst 15987000 # number of overall miss cycles
342system.cpu.icache.overall_miss_latency::total 15987000 # number of overall miss cycles
343system.cpu.icache.ReadReq_accesses::cpu.inst 1948 # number of ReadReq accesses(hits+misses)
344system.cpu.icache.ReadReq_accesses::total 1948 # number of ReadReq accesses(hits+misses)
345system.cpu.icache.demand_accesses::cpu.inst 1948 # number of demand (read+write) accesses
346system.cpu.icache.demand_accesses::total 1948 # number of demand (read+write) accesses
347system.cpu.icache.overall_accesses::cpu.inst 1948 # number of overall (read+write) accesses
348system.cpu.icache.overall_accesses::total 1948 # number of overall (read+write) accesses
349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.224333 # miss rate for ReadReq accesses
350system.cpu.icache.ReadReq_miss_rate::total 0.224333 # miss rate for ReadReq accesses
351system.cpu.icache.demand_miss_rate::cpu.inst 0.224333 # miss rate for demand accesses
352system.cpu.icache.demand_miss_rate::total 0.224333 # miss rate for demand accesses
353system.cpu.icache.overall_miss_rate::cpu.inst 0.224333 # miss rate for overall accesses
354system.cpu.icache.overall_miss_rate::total 0.224333 # miss rate for overall accesses
355system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 36583.524027 # average ReadReq miss latency
356system.cpu.icache.ReadReq_avg_miss_latency::total 36583.524027 # average ReadReq miss latency
357system.cpu.icache.demand_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency
358system.cpu.icache.demand_avg_miss_latency::total 36583.524027 # average overall miss latency
359system.cpu.icache.overall_avg_miss_latency::cpu.inst 36583.524027 # average overall miss latency
360system.cpu.icache.overall_avg_miss_latency::total 36583.524027 # average overall miss latency

361system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
362system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
363system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
364system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
365system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
366system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
367system.cpu.icache.fast_writes 0 # number of fast writes performed
368system.cpu.icache.cache_copies 0 # number of cache copies performed
369system.cpu.icache.ReadReq_mshr_hits::cpu.inst 94 # number of ReadReq MSHR hits
370system.cpu.icache.ReadReq_mshr_hits::total 94 # number of ReadReq MSHR hits
371system.cpu.icache.demand_mshr_hits::cpu.inst 94 # number of demand (read+write) MSHR hits
372system.cpu.icache.demand_mshr_hits::total 94 # number of demand (read+write) MSHR hits
373system.cpu.icache.overall_mshr_hits::cpu.inst 94 # number of overall MSHR hits
374system.cpu.icache.overall_mshr_hits::total 94 # number of overall MSHR hits

375system.cpu.icache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses
376system.cpu.icache.ReadReq_mshr_misses::total 341 # number of ReadReq MSHR misses
377system.cpu.icache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses
378system.cpu.icache.demand_mshr_misses::total 341 # number of demand (read+write) MSHR misses
379system.cpu.icache.overall_mshr_misses::cpu.inst 341 # number of overall MSHR misses
380system.cpu.icache.overall_mshr_misses::total 341 # number of overall MSHR misses
381system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 11963500 # number of ReadReq MSHR miss cycles
382system.cpu.icache.ReadReq_mshr_miss_latency::total 11963500 # number of ReadReq MSHR miss cycles
383system.cpu.icache.demand_mshr_miss_latency::cpu.inst 11963500 # number of demand (read+write) MSHR miss cycles
384system.cpu.icache.demand_mshr_miss_latency::total 11963500 # number of demand (read+write) MSHR miss cycles
385system.cpu.icache.overall_mshr_miss_latency::cpu.inst 11963500 # number of overall MSHR miss cycles
386system.cpu.icache.overall_mshr_miss_latency::total 11963500 # number of overall MSHR miss cycles
387system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for ReadReq accesses
388system.cpu.icache.ReadReq_mshr_miss_rate::total 0.175955 # mshr miss rate for ReadReq accesses
389system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for demand accesses
390system.cpu.icache.demand_mshr_miss_rate::total 0.175955 # mshr miss rate for demand accesses
391system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.175955 # mshr miss rate for overall accesses
392system.cpu.icache.overall_mshr_miss_rate::total 0.175955 # mshr miss rate for overall accesses
393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35083.577713 # average ReadReq mshr miss latency
394system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35083.577713 # average ReadReq mshr miss latency
395system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency
396system.cpu.icache.demand_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency
397system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35083.577713 # average overall mshr miss latency
398system.cpu.icache.overall_avg_mshr_miss_latency::total 35083.577713 # average overall mshr miss latency

375system.cpu.icache.ReadReq_mshr_misses::cpu.inst 343 # number of ReadReq MSHR misses
376system.cpu.icache.ReadReq_mshr_misses::total 343 # number of ReadReq MSHR misses
377system.cpu.icache.demand_mshr_misses::cpu.inst 343 # number of demand (read+write) MSHR misses
378system.cpu.icache.demand_mshr_misses::total 343 # number of demand (read+write) MSHR misses
379system.cpu.icache.overall_mshr_misses::cpu.inst 343 # number of overall MSHR misses
380system.cpu.icache.overall_mshr_misses::total 343 # number of overall MSHR misses
381system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12452000 # number of ReadReq MSHR miss cycles
382system.cpu.icache.ReadReq_mshr_miss_latency::total 12452000 # number of ReadReq MSHR miss cycles
383system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12452000 # number of demand (read+write) MSHR miss cycles
384system.cpu.icache.demand_mshr_miss_latency::total 12452000 # number of demand (read+write) MSHR miss cycles
385system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12452000 # number of overall MSHR miss cycles
386system.cpu.icache.overall_mshr_miss_latency::total 12452000 # number of overall MSHR miss cycles
387system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for ReadReq accesses
388system.cpu.icache.ReadReq_mshr_miss_rate::total 0.176078 # mshr miss rate for ReadReq accesses
389system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for demand accesses
390system.cpu.icache.demand_mshr_miss_rate::total 0.176078 # mshr miss rate for demand accesses
391system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.176078 # mshr miss rate for overall accesses
392system.cpu.icache.overall_mshr_miss_rate::total 0.176078 # mshr miss rate for overall accesses
393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 36303.206997 # average ReadReq mshr miss latency
394system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 36303.206997 # average ReadReq mshr miss latency
395system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency
396system.cpu.icache.demand_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency
397system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 36303.206997 # average overall mshr miss latency
398system.cpu.icache.overall_avg_mshr_miss_latency::total 36303.206997 # average overall mshr miss latency

399system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
400system.cpu.dcache.replacements 0 # number of replacements

401system.cpu.dcache.tagsinuse 92.268506 # Cycle average of tags in use
402system.cpu.dcache.total_refs 2489 # Total number of references to valid blocks.
403system.cpu.dcache.sampled_refs 143 # Sample count of references to valid blocks.
404system.cpu.dcache.avg_refs 17.405594 # Average number of references to valid blocks.

401system.cpu.dcache.tagsinuse 91.140441 # Cycle average of tags in use
402system.cpu.dcache.total_refs 2441 # Total number of references to valid blocks.
403system.cpu.dcache.sampled_refs 141 # Sample count of references to valid blocks.
404system.cpu.dcache.avg_refs 17.312057 # Average number of references to valid blocks.

405system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

406system.cpu.dcache.occ_blocks::cpu.data 92.268506 # Average occupied blocks per requestor
407system.cpu.dcache.occ_percent::cpu.data 0.022526 # Average percentage of cache occupancy
408system.cpu.dcache.occ_percent::total 0.022526 # Average percentage of cache occupancy
409system.cpu.dcache.ReadReq_hits::cpu.data 1903 # number of ReadReq hits
410system.cpu.dcache.ReadReq_hits::total 1903 # number of ReadReq hits
411system.cpu.dcache.WriteReq_hits::cpu.data 586 # number of WriteReq hits
412system.cpu.dcache.WriteReq_hits::total 586 # number of WriteReq hits
413system.cpu.dcache.demand_hits::cpu.data 2489 # number of demand (read+write) hits
414system.cpu.dcache.demand_hits::total 2489 # number of demand (read+write) hits
415system.cpu.dcache.overall_hits::cpu.data 2489 # number of overall hits
416system.cpu.dcache.overall_hits::total 2489 # number of overall hits
417system.cpu.dcache.ReadReq_misses::cpu.data 133 # number of ReadReq misses
418system.cpu.dcache.ReadReq_misses::total 133 # number of ReadReq misses
419system.cpu.dcache.WriteReq_misses::cpu.data 339 # number of WriteReq misses
420system.cpu.dcache.WriteReq_misses::total 339 # number of WriteReq misses
421system.cpu.dcache.demand_misses::cpu.data 472 # number of demand (read+write) misses
422system.cpu.dcache.demand_misses::total 472 # number of demand (read+write) misses
423system.cpu.dcache.overall_misses::cpu.data 472 # number of overall misses
424system.cpu.dcache.overall_misses::total 472 # number of overall misses
425system.cpu.dcache.ReadReq_miss_latency::cpu.data 4784500 # number of ReadReq miss cycles
426system.cpu.dcache.ReadReq_miss_latency::total 4784500 # number of ReadReq miss cycles
427system.cpu.dcache.WriteReq_miss_latency::cpu.data 11421000 # number of WriteReq miss cycles
428system.cpu.dcache.WriteReq_miss_latency::total 11421000 # number of WriteReq miss cycles
429system.cpu.dcache.demand_miss_latency::cpu.data 16205500 # number of demand (read+write) miss cycles
430system.cpu.dcache.demand_miss_latency::total 16205500 # number of demand (read+write) miss cycles
431system.cpu.dcache.overall_miss_latency::cpu.data 16205500 # number of overall miss cycles
432system.cpu.dcache.overall_miss_latency::total 16205500 # number of overall miss cycles
433system.cpu.dcache.ReadReq_accesses::cpu.data 2036 # number of ReadReq accesses(hits+misses)
434system.cpu.dcache.ReadReq_accesses::total 2036 # number of ReadReq accesses(hits+misses)

406system.cpu.dcache.occ_blocks::cpu.data 91.140441 # Average occupied blocks per requestor
407system.cpu.dcache.occ_percent::cpu.data 0.022251 # Average percentage of cache occupancy
408system.cpu.dcache.occ_percent::total 0.022251 # Average percentage of cache occupancy
409system.cpu.dcache.ReadReq_hits::cpu.data 1863 # number of ReadReq hits
410system.cpu.dcache.ReadReq_hits::total 1863 # number of ReadReq hits
411system.cpu.dcache.WriteReq_hits::cpu.data 578 # number of WriteReq hits
412system.cpu.dcache.WriteReq_hits::total 578 # number of WriteReq hits
413system.cpu.dcache.demand_hits::cpu.data 2441 # number of demand (read+write) hits
414system.cpu.dcache.demand_hits::total 2441 # number of demand (read+write) hits
415system.cpu.dcache.overall_hits::cpu.data 2441 # number of overall hits
416system.cpu.dcache.overall_hits::total 2441 # number of overall hits
417system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses
418system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses
419system.cpu.dcache.WriteReq_misses::cpu.data 347 # number of WriteReq misses
420system.cpu.dcache.WriteReq_misses::total 347 # number of WriteReq misses
421system.cpu.dcache.demand_misses::cpu.data 495 # number of demand (read+write) misses
422system.cpu.dcache.demand_misses::total 495 # number of demand (read+write) misses
423system.cpu.dcache.overall_misses::cpu.data 495 # number of overall misses
424system.cpu.dcache.overall_misses::total 495 # number of overall misses
425system.cpu.dcache.ReadReq_miss_latency::cpu.data 5658500 # number of ReadReq miss cycles
426system.cpu.dcache.ReadReq_miss_latency::total 5658500 # number of ReadReq miss cycles
427system.cpu.dcache.WriteReq_miss_latency::cpu.data 13040000 # number of WriteReq miss cycles
428system.cpu.dcache.WriteReq_miss_latency::total 13040000 # number of WriteReq miss cycles
429system.cpu.dcache.demand_miss_latency::cpu.data 18698500 # number of demand (read+write) miss cycles
430system.cpu.dcache.demand_miss_latency::total 18698500 # number of demand (read+write) miss cycles
431system.cpu.dcache.overall_miss_latency::cpu.data 18698500 # number of overall miss cycles
432system.cpu.dcache.overall_miss_latency::total 18698500 # number of overall miss cycles
433system.cpu.dcache.ReadReq_accesses::cpu.data 2011 # number of ReadReq accesses(hits+misses)
434system.cpu.dcache.ReadReq_accesses::total 2011 # number of ReadReq accesses(hits+misses)

435system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
436system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)

437system.cpu.dcache.demand_accesses::cpu.data 2961 # number of demand (read+write) accesses
438system.cpu.dcache.demand_accesses::total 2961 # number of demand (read+write) accesses
439system.cpu.dcache.overall_accesses::cpu.data 2961 # number of overall (read+write) accesses
440system.cpu.dcache.overall_accesses::total 2961 # number of overall (read+write) accesses
441system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065324 # miss rate for ReadReq accesses
442system.cpu.dcache.ReadReq_miss_rate::total 0.065324 # miss rate for ReadReq accesses
443system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses
444system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses
445system.cpu.dcache.demand_miss_rate::cpu.data 0.159406 # miss rate for demand accesses
446system.cpu.dcache.demand_miss_rate::total 0.159406 # miss rate for demand accesses
447system.cpu.dcache.overall_miss_rate::cpu.data 0.159406 # miss rate for overall accesses
448system.cpu.dcache.overall_miss_rate::total 0.159406 # miss rate for overall accesses
449system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 35973.684211 # average ReadReq miss latency
450system.cpu.dcache.ReadReq_avg_miss_latency::total 35973.684211 # average ReadReq miss latency
451system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33690.265487 # average WriteReq miss latency
452system.cpu.dcache.WriteReq_avg_miss_latency::total 33690.265487 # average WriteReq miss latency
453system.cpu.dcache.demand_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency
454system.cpu.dcache.demand_avg_miss_latency::total 34333.686441 # average overall miss latency
455system.cpu.dcache.overall_avg_miss_latency::cpu.data 34333.686441 # average overall miss latency
456system.cpu.dcache.overall_avg_miss_latency::total 34333.686441 # average overall miss latency

437system.cpu.dcache.demand_accesses::cpu.data 2936 # number of demand (read+write) accesses
438system.cpu.dcache.demand_accesses::total 2936 # number of demand (read+write) accesses
439system.cpu.dcache.overall_accesses::cpu.data 2936 # number of overall (read+write) accesses
440system.cpu.dcache.overall_accesses::total 2936 # number of overall (read+write) accesses
441system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.073595 # miss rate for ReadReq accesses
442system.cpu.dcache.ReadReq_miss_rate::total 0.073595 # miss rate for ReadReq accesses
443system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.375135 # miss rate for WriteReq accesses
444system.cpu.dcache.WriteReq_miss_rate::total 0.375135 # miss rate for WriteReq accesses
445system.cpu.dcache.demand_miss_rate::cpu.data 0.168597 # miss rate for demand accesses
446system.cpu.dcache.demand_miss_rate::total 0.168597 # miss rate for demand accesses
447system.cpu.dcache.overall_miss_rate::cpu.data 0.168597 # miss rate for overall accesses
448system.cpu.dcache.overall_miss_rate::total 0.168597 # miss rate for overall accesses
449system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 38233.108108 # average ReadReq miss latency
450system.cpu.dcache.ReadReq_avg_miss_latency::total 38233.108108 # average ReadReq miss latency
451system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 37579.250720 # average WriteReq miss latency
452system.cpu.dcache.WriteReq_avg_miss_latency::total 37579.250720 # average WriteReq miss latency
453system.cpu.dcache.demand_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency
454system.cpu.dcache.demand_avg_miss_latency::total 37774.747475 # average overall miss latency
455system.cpu.dcache.overall_avg_miss_latency::cpu.data 37774.747475 # average overall miss latency
456system.cpu.dcache.overall_avg_miss_latency::total 37774.747475 # average overall miss latency

457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked
460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
463system.cpu.dcache.fast_writes 0 # number of fast writes performed
464system.cpu.dcache.cache_copies 0 # number of cache copies performed

465system.cpu.dcache.ReadReq_mshr_hits::cpu.data 41 # number of ReadReq MSHR hits
466system.cpu.dcache.ReadReq_mshr_hits::total 41 # number of ReadReq MSHR hits
467system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits
468system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits
469system.cpu.dcache.demand_mshr_hits::cpu.data 329 # number of demand (read+write) MSHR hits
470system.cpu.dcache.demand_mshr_hits::total 329 # number of demand (read+write) MSHR hits
471system.cpu.dcache.overall_mshr_hits::cpu.data 329 # number of overall MSHR hits
472system.cpu.dcache.overall_mshr_hits::total 329 # number of overall MSHR hits
473system.cpu.dcache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses
474system.cpu.dcache.ReadReq_mshr_misses::total 92 # number of ReadReq MSHR misses

465system.cpu.dcache.ReadReq_mshr_hits::cpu.data 58 # number of ReadReq MSHR hits
466system.cpu.dcache.ReadReq_mshr_hits::total 58 # number of ReadReq MSHR hits
467system.cpu.dcache.WriteReq_mshr_hits::cpu.data 296 # number of WriteReq MSHR hits
468system.cpu.dcache.WriteReq_mshr_hits::total 296 # number of WriteReq MSHR hits
469system.cpu.dcache.demand_mshr_hits::cpu.data 354 # number of demand (read+write) MSHR hits
470system.cpu.dcache.demand_mshr_hits::total 354 # number of demand (read+write) MSHR hits
471system.cpu.dcache.overall_mshr_hits::cpu.data 354 # number of overall MSHR hits
472system.cpu.dcache.overall_mshr_hits::total 354 # number of overall MSHR hits
473system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses
474system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses

475system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
476system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses

477system.cpu.dcache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses
478system.cpu.dcache.demand_mshr_misses::total 143 # number of demand (read+write) MSHR misses
479system.cpu.dcache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses
480system.cpu.dcache.overall_mshr_misses::total 143 # number of overall MSHR misses
481system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3306000 # number of ReadReq MSHR miss cycles
482system.cpu.dcache.ReadReq_mshr_miss_latency::total 3306000 # number of ReadReq MSHR miss cycles
483system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845000 # number of WriteReq MSHR miss cycles
484system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845000 # number of WriteReq MSHR miss cycles
485system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5151000 # number of demand (read+write) MSHR miss cycles
486system.cpu.dcache.demand_mshr_miss_latency::total 5151000 # number of demand (read+write) MSHR miss cycles
487system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5151000 # number of overall MSHR miss cycles
488system.cpu.dcache.overall_mshr_miss_latency::total 5151000 # number of overall MSHR miss cycles
489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045187 # mshr miss rate for ReadReq accesses
490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045187 # mshr miss rate for ReadReq accesses

477system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
478system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
479system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
480system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
481system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 3847000 # number of ReadReq MSHR miss cycles
482system.cpu.dcache.ReadReq_mshr_miss_latency::total 3847000 # number of ReadReq MSHR miss cycles
483system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 2081000 # number of WriteReq MSHR miss cycles
484system.cpu.dcache.WriteReq_mshr_miss_latency::total 2081000 # number of WriteReq MSHR miss cycles
485system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5928000 # number of demand (read+write) MSHR miss cycles
486system.cpu.dcache.demand_mshr_miss_latency::total 5928000 # number of demand (read+write) MSHR miss cycles
487system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5928000 # number of overall MSHR miss cycles
488system.cpu.dcache.overall_mshr_miss_latency::total 5928000 # number of overall MSHR miss cycles
489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044754 # mshr miss rate for ReadReq accesses
490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044754 # mshr miss rate for ReadReq accesses

491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses

493system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for demand accesses
494system.cpu.dcache.demand_mshr_miss_rate::total 0.048294 # mshr miss rate for demand accesses
495system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048294 # mshr miss rate for overall accesses
496system.cpu.dcache.overall_mshr_miss_rate::total 0.048294 # mshr miss rate for overall accesses
497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35934.782609 # average ReadReq mshr miss latency
498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35934.782609 # average ReadReq mshr miss latency
499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36176.470588 # average WriteReq mshr miss latency
500system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36176.470588 # average WriteReq mshr miss latency
501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency
502system.cpu.dcache.demand_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency
503system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36020.979021 # average overall mshr miss latency
504system.cpu.dcache.overall_avg_mshr_miss_latency::total 36020.979021 # average overall mshr miss latency

493system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for demand accesses
494system.cpu.dcache.demand_mshr_miss_rate::total 0.048025 # mshr miss rate for demand accesses
495system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048025 # mshr miss rate for overall accesses
496system.cpu.dcache.overall_mshr_miss_rate::total 0.048025 # mshr miss rate for overall accesses
497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 42744.444444 # average ReadReq mshr miss latency
498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 42744.444444 # average ReadReq mshr miss latency
499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 40803.921569 # average WriteReq mshr miss latency
500system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 40803.921569 # average WriteReq mshr miss latency
501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency
502system.cpu.dcache.demand_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency
503system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 42042.553191 # average overall mshr miss latency
504system.cpu.dcache.overall_avg_mshr_miss_latency::total 42042.553191 # average overall mshr miss latency

505system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
506system.cpu.l2cache.replacements 0 # number of replacements

507system.cpu.l2cache.tagsinuse 224.190745 # Cycle average of tags in use

507system.cpu.l2cache.tagsinuse 222.725864 # Cycle average of tags in use

508system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks.
509system.cpu.l2cache.sampled_refs 430 # Sample count of references to valid blocks.
510system.cpu.l2cache.avg_refs 0.006977 # Average number of references to valid blocks.
511system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit.

512system.cpu.l2cache.occ_blocks::cpu.inst 165.976213 # Average occupied blocks per requestor
513system.cpu.l2cache.occ_blocks::cpu.data 58.214532 # Average occupied blocks per requestor
514system.cpu.l2cache.occ_percent::cpu.inst 0.005065 # Average percentage of cache occupancy
515system.cpu.l2cache.occ_percent::cpu.data 0.001777 # Average percentage of cache occupancy
516system.cpu.l2cache.occ_percent::total 0.006842 # Average percentage of cache occupancy

512system.cpu.l2cache.occ_blocks::cpu.inst 165.335127 # Average occupied blocks per requestor
513system.cpu.l2cache.occ_blocks::cpu.data 57.390737 # Average occupied blocks per requestor
514system.cpu.l2cache.occ_percent::cpu.inst 0.005046 # Average percentage of cache occupancy
515system.cpu.l2cache.occ_percent::cpu.data 0.001751 # Average percentage of cache occupancy
516system.cpu.l2cache.occ_percent::total 0.006797 # Average percentage of cache occupancy

517system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
518system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
519system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
520system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
521system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
522system.cpu.l2cache.overall_hits::total 3 # number of overall hits

523system.cpu.l2cache.ReadReq_misses::cpu.inst 338 # number of ReadReq misses
524system.cpu.l2cache.ReadReq_misses::cpu.data 92 # number of ReadReq misses

523system.cpu.l2cache.ReadReq_misses::cpu.inst 340 # number of ReadReq misses
524system.cpu.l2cache.ReadReq_misses::cpu.data 90 # number of ReadReq misses

525system.cpu.l2cache.ReadReq_misses::total 430 # number of ReadReq misses
526system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
527system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses

528system.cpu.l2cache.demand_misses::cpu.inst 338 # number of demand (read+write) misses
529system.cpu.l2cache.demand_misses::cpu.data 143 # number of demand (read+write) misses

528system.cpu.l2cache.demand_misses::cpu.inst 340 # number of demand (read+write) misses
529system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses

530system.cpu.l2cache.demand_misses::total 481 # number of demand (read+write) misses

531system.cpu.l2cache.overall_misses::cpu.inst 338 # number of overall misses
532system.cpu.l2cache.overall_misses::cpu.data 143 # number of overall misses

531system.cpu.l2cache.overall_misses::cpu.inst 340 # number of overall misses
532system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses

533system.cpu.l2cache.overall_misses::total 481 # number of overall misses

534system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 11593500 # number of ReadReq miss cycles
535system.cpu.l2cache.ReadReq_miss_latency::cpu.data 3178500 # number of ReadReq miss cycles
536system.cpu.l2cache.ReadReq_miss_latency::total 14772000 # number of ReadReq miss cycles
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539system.cpu.l2cache.demand_miss_latency::cpu.inst 11593500 # number of demand (read+write) miss cycles
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542system.cpu.l2cache.overall_miss_latency::cpu.inst 11593500 # number of overall miss cycles
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546system.cpu.l2cache.ReadReq_accesses::cpu.data 92 # number of ReadReq accesses(hits+misses)

534system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 12086500 # number of ReadReq miss cycles
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538system.cpu.l2cache.ReadExReq_miss_latency::total 1998000 # number of ReadExReq miss cycles
539system.cpu.l2cache.demand_miss_latency::cpu.inst 12086500 # number of demand (read+write) miss cycles
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542system.cpu.l2cache.overall_miss_latency::cpu.inst 12086500 # number of overall miss cycles
543system.cpu.l2cache.overall_miss_latency::cpu.data 5736500 # number of overall miss cycles
544system.cpu.l2cache.overall_miss_latency::total 17823000 # number of overall miss cycles
545system.cpu.l2cache.ReadReq_accesses::cpu.inst 343 # number of ReadReq accesses(hits+misses)
546system.cpu.l2cache.ReadReq_accesses::cpu.data 90 # number of ReadReq accesses(hits+misses)

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551system.cpu.l2cache.demand_accesses::cpu.data 143 # number of demand (read+write) accesses

550system.cpu.l2cache.demand_accesses::cpu.inst 343 # number of demand (read+write) accesses
551system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses

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553system.cpu.l2cache.overall_accesses::cpu.inst 341 # number of overall (read+write) accesses
554system.cpu.l2cache.overall_accesses::cpu.data 143 # number of overall (read+write) accesses

553system.cpu.l2cache.overall_accesses::cpu.inst 343 # number of overall (read+write) accesses
554system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses

555system.cpu.l2cache.overall_accesses::total 484 # number of overall (read+write) accesses

556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991202 # miss rate for ReadReq accesses

556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991254 # miss rate for ReadReq accesses

557system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses
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561system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991254 # miss rate for demand accesses

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564system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991254 # miss rate for overall accesses

565system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
566system.cpu.l2cache.overall_miss_rate::total 0.993802 # miss rate for overall accesses

567system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34300.295858 # average ReadReq miss latency
568system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34548.913043 # average ReadReq miss latency
569system.cpu.l2cache.ReadReq_avg_miss_latency::total 34353.488372 # average ReadReq miss latency
570system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34676.470588 # average ReadExReq miss latency
571system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34676.470588 # average ReadExReq miss latency
572system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency
573system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency
574system.cpu.l2cache.demand_avg_miss_latency::total 34387.733888 # average overall miss latency
575system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34300.295858 # average overall miss latency
576system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34594.405594 # average overall miss latency
577system.cpu.l2cache.overall_avg_miss_latency::total 34387.733888 # average overall miss latency

567system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 35548.529412 # average ReadReq miss latency
568system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 41538.888889 # average ReadReq miss latency
569system.cpu.l2cache.ReadReq_avg_miss_latency::total 36802.325581 # average ReadReq miss latency
570system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 39176.470588 # average ReadExReq miss latency
571system.cpu.l2cache.ReadExReq_avg_miss_latency::total 39176.470588 # average ReadExReq miss latency
572system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency
573system.cpu.l2cache.demand_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency
574system.cpu.l2cache.demand_avg_miss_latency::total 37054.054054 # average overall miss latency
575system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 35548.529412 # average overall miss latency
576system.cpu.l2cache.overall_avg_miss_latency::cpu.data 40684.397163 # average overall miss latency
577system.cpu.l2cache.overall_avg_miss_latency::total 37054.054054 # average overall miss latency

578system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
579system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
580system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
581system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
582system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
583system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
584system.cpu.l2cache.fast_writes 0 # number of fast writes performed
585system.cpu.l2cache.cache_copies 0 # number of cache copies performed

586system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
587system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 92 # number of ReadReq MSHR misses

586system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses
587system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses

588system.cpu.l2cache.ReadReq_mshr_misses::total 430 # number of ReadReq MSHR misses
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590system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses

591system.cpu.l2cache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
592system.cpu.l2cache.demand_mshr_misses::cpu.data 143 # number of demand (read+write) MSHR misses

591system.cpu.l2cache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses
592system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses

593system.cpu.l2cache.demand_mshr_misses::total 481 # number of demand (read+write) MSHR misses

594system.cpu.l2cache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
595system.cpu.l2cache.overall_mshr_misses::cpu.data 143 # number of overall MSHR misses

594system.cpu.l2cache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses
595system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses

596system.cpu.l2cache.overall_mshr_misses::total 481 # number of overall MSHR misses

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601system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 1604000 # number of ReadExReq MSHR miss cycles
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609system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
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613system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991254 # mshr miss rate for demand accesses

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623system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 36068.627451 # average ReadExReq mshr miss latency
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627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 32350 # average overall mshr miss latency
628system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 37606.382979 # average overall mshr miss latency
629system.cpu.l2cache.overall_avg_mshr_miss_latency::total 33890.852391 # average overall mshr miss latency