| stats.txt (8983:8800b05e1cb3) | stats.txt (9055:38f1926fb599) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 12671500 # Number of ticks simulated 5final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 12671500 # Number of ticks simulated 5final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 56172 # Simulator instruction rate (inst/s) 8host_op_rate 56163 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137660070 # Simulator tick rate (ticks/s) 10host_mem_usage 215596 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host | 7host_inst_rate 63611 # Simulator instruction rate (inst/s) 8host_op_rate 63597 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 155871053 # Simulator tick rate (ticks/s) 10host_mem_usage 216124 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 5169 # Number of instructions simulated 13sim_ops 5169 # Number of ops (including micro ops) simulated | 12sim_insts 5169 # Number of instructions simulated 13sim_ops 5169 # Number of ops (including micro ops) simulated |
| 14system.physmem.bytes_read 30912 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 483 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory 20system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s) 21system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s) 22system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s) | 14system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30912 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory 20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 21system.physmem.num_reads::total 483 # Number of read requests responded to by this memory 22system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s) 23system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s) 24system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s) 26system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s) 27system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s) 28system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s) 29system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s) |
| 23system.cpu.dtb.read_hits 0 # DTB read hits 24system.cpu.dtb.read_misses 0 # DTB read misses 25system.cpu.dtb.read_accesses 0 # DTB read accesses 26system.cpu.dtb.write_hits 0 # DTB write hits 27system.cpu.dtb.write_misses 0 # DTB write misses 28system.cpu.dtb.write_accesses 0 # DTB write accesses 29system.cpu.dtb.hits 0 # DTB hits 30system.cpu.dtb.misses 0 # DTB misses --- 304 unchanged lines hidden (view full) --- 335system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles 336system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) 337system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) 338system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses 339system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses 340system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses 341system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses 342system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses | 30system.cpu.dtb.read_hits 0 # DTB read hits 31system.cpu.dtb.read_misses 0 # DTB read misses 32system.cpu.dtb.read_accesses 0 # DTB read accesses 33system.cpu.dtb.write_hits 0 # DTB write hits 34system.cpu.dtb.write_misses 0 # DTB write misses 35system.cpu.dtb.write_accesses 0 # DTB write accesses 36system.cpu.dtb.hits 0 # DTB hits 37system.cpu.dtb.misses 0 # DTB misses --- 304 unchanged lines hidden (view full) --- 342system.cpu.icache.overall_miss_latency::total 15909500 # number of overall miss cycles 343system.cpu.icache.ReadReq_accesses::cpu.inst 2039 # number of ReadReq accesses(hits+misses) 344system.cpu.icache.ReadReq_accesses::total 2039 # number of ReadReq accesses(hits+misses) 345system.cpu.icache.demand_accesses::cpu.inst 2039 # number of demand (read+write) accesses 346system.cpu.icache.demand_accesses::total 2039 # number of demand (read+write) accesses 347system.cpu.icache.overall_accesses::cpu.inst 2039 # number of overall (read+write) accesses 348system.cpu.icache.overall_accesses::total 2039 # number of overall (read+write) accesses 349system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219225 # miss rate for ReadReq accesses |
| 350system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses |
|
| 343system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses | 351system.cpu.icache.demand_miss_rate::cpu.inst 0.219225 # miss rate for demand accesses |
| 352system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses |
|
| 344system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses | 353system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses |
| 354system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses |
|
| 345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency | 355system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency |
| 356system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency |
|
| 346system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency | 357system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency |
| 358system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency |
|
| 347system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency | 359system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency |
| 360system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency |
|
| 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 367system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses 368system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles 369system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles 370system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles 371system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles 372system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles 373system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles 374system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses | 361system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 362system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 363system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 364system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 365system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 366system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 367system.cpu.icache.fast_writes 0 # number of fast writes performed 368system.cpu.icache.cache_copies 0 # number of cache copies performed --- 11 unchanged lines hidden (view full) --- 380system.cpu.icache.overall_mshr_misses::total 344 # number of overall MSHR misses 381system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 12065000 # number of ReadReq MSHR miss cycles 382system.cpu.icache.ReadReq_mshr_miss_latency::total 12065000 # number of ReadReq MSHR miss cycles 383system.cpu.icache.demand_mshr_miss_latency::cpu.inst 12065000 # number of demand (read+write) MSHR miss cycles 384system.cpu.icache.demand_mshr_miss_latency::total 12065000 # number of demand (read+write) MSHR miss cycles 385system.cpu.icache.overall_mshr_miss_latency::cpu.inst 12065000 # number of overall MSHR miss cycles 386system.cpu.icache.overall_mshr_miss_latency::total 12065000 # number of overall MSHR miss cycles 387system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for ReadReq accesses |
| 388system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses |
|
| 375system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses | 389system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for demand accesses |
| 390system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses |
|
| 376system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses | 391system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.168710 # mshr miss rate for overall accesses |
| 392system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses |
|
| 377system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency | 393system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 35072.674419 # average ReadReq mshr miss latency |
| 394system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency |
|
| 378system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency | 395system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency |
| 396system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency |
|
| 379system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency | 397system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 35072.674419 # average overall mshr miss latency |
| 398system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency |
|
| 380system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 381system.cpu.dcache.replacements 0 # number of replacements 382system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use 383system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. 384system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 385system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. 386system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 387system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 415system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) 416system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 417system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 418system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 419system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 420system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 421system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 422system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses | 399system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 400system.cpu.dcache.replacements 0 # number of replacements 401system.cpu.dcache.tagsinuse 92.322697 # Cycle average of tags in use 402system.cpu.dcache.total_refs 2472 # Total number of references to valid blocks. 403system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 404system.cpu.dcache.avg_refs 17.408451 # Average number of references to valid blocks. 405system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 406system.cpu.dcache.occ_blocks::cpu.data 92.322697 # Average occupied blocks per requestor --- 27 unchanged lines hidden (view full) --- 434system.cpu.dcache.ReadReq_accesses::total 2019 # number of ReadReq accesses(hits+misses) 435system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 436system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 437system.cpu.dcache.demand_accesses::cpu.data 2944 # number of demand (read+write) accesses 438system.cpu.dcache.demand_accesses::total 2944 # number of demand (read+write) accesses 439system.cpu.dcache.overall_accesses::cpu.data 2944 # number of overall (read+write) accesses 440system.cpu.dcache.overall_accesses::total 2944 # number of overall (read+write) accesses 441system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.065874 # miss rate for ReadReq accesses |
| 442system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses |
|
| 423system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses | 443system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.366486 # miss rate for WriteReq accesses |
| 444system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses |
|
| 424system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses | 445system.cpu.dcache.demand_miss_rate::cpu.data 0.160326 # miss rate for demand accesses |
| 446system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses |
|
| 425system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses | 447system.cpu.dcache.overall_miss_rate::cpu.data 0.160326 # miss rate for overall accesses |
| 448system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses |
|
| 426system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency | 449system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency |
| 450system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency |
|
| 427system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency | 451system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency |
| 452system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency |
|
| 428system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency | 453system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency |
| 454system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency |
|
| 429system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency | 455system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency |
| 456system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency |
|
| 430system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 431system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 433system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 434system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 435system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 436system.cpu.dcache.fast_writes 0 # number of fast writes performed 437system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 455system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles 456system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles 457system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles 458system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles 459system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles 460system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles 461system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles 462system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses | 457system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 458system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 459system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 460system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 461system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 462system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 463system.cpu.dcache.fast_writes 0 # number of fast writes performed 464system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 17 unchanged lines hidden (view full) --- 482system.cpu.dcache.ReadReq_mshr_miss_latency::total 3267500 # number of ReadReq MSHR miss cycles 483system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 1845500 # number of WriteReq MSHR miss cycles 484system.cpu.dcache.WriteReq_mshr_miss_latency::total 1845500 # number of WriteReq MSHR miss cycles 485system.cpu.dcache.demand_mshr_miss_latency::cpu.data 5113000 # number of demand (read+write) MSHR miss cycles 486system.cpu.dcache.demand_mshr_miss_latency::total 5113000 # number of demand (read+write) MSHR miss cycles 487system.cpu.dcache.overall_mshr_miss_latency::cpu.data 5113000 # number of overall MSHR miss cycles 488system.cpu.dcache.overall_mshr_miss_latency::total 5113000 # number of overall MSHR miss cycles 489system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045072 # mshr miss rate for ReadReq accesses |
| 490system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses |
|
| 463system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses | 491system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses |
| 492system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses |
|
| 464system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses | 493system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for demand accesses |
| 494system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses |
|
| 465system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses | 495system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048234 # mshr miss rate for overall accesses |
| 496system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses |
|
| 466system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency | 497system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 35906.593407 # average ReadReq mshr miss latency |
| 498system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency |
|
| 467system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency | 499system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 36186.274510 # average WriteReq mshr miss latency |
| 500system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency |
|
| 468system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency | 501system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency |
| 502system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency |
|
| 469system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency | 503system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 36007.042254 # average overall mshr miss latency |
| 504system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency |
|
| 470system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 471system.cpu.l2cache.replacements 0 # number of replacements 472system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use 473system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 474system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. 475system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. 476system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 477system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 515system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses 516system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 517system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 518system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses 519system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 520system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 521system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses 522system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses | 505system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 506system.cpu.l2cache.replacements 0 # number of replacements 507system.cpu.l2cache.tagsinuse 226.359524 # Cycle average of tags in use 508system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 509system.cpu.l2cache.sampled_refs 432 # Sample count of references to valid blocks. 510system.cpu.l2cache.avg_refs 0.006944 # Average number of references to valid blocks. 511system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 512system.cpu.l2cache.occ_blocks::cpu.inst 168.225322 # Average occupied blocks per requestor --- 37 unchanged lines hidden (view full) --- 550system.cpu.l2cache.demand_accesses::cpu.inst 344 # number of demand (read+write) accesses 551system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 552system.cpu.l2cache.demand_accesses::total 486 # number of demand (read+write) accesses 553system.cpu.l2cache.overall_accesses::cpu.inst 344 # number of overall (read+write) accesses 554system.cpu.l2cache.overall_accesses::cpu.data 142 # number of overall (read+write) accesses 555system.cpu.l2cache.overall_accesses::total 486 # number of overall (read+write) accesses 556system.cpu.l2cache.ReadReq_miss_rate::cpu.inst 0.991279 # miss rate for ReadReq accesses 557system.cpu.l2cache.ReadReq_miss_rate::cpu.data 1 # miss rate for ReadReq accesses |
| 558system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses |
|
| 523system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses | 559system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses |
| 560system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses |
|
| 524system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses 525system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses | 561system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991279 # miss rate for demand accesses 562system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses |
| 563system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses |
|
| 526system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses 527system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses | 564system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991279 # miss rate for overall accesses 565system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses |
| 566system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses |
|
| 528system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency 529system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency | 567system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 34284.457478 # average ReadReq miss latency 568system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 34527.472527 # average ReadReq miss latency |
| 569system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency |
|
| 530system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency | 570system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 34686.274510 # average ReadExReq miss latency |
| 571system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency |
|
| 531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency | 572system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 573system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency |
| 574system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency |
|
| 533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency | 575system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 576system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency |
| 577system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency |
|
| 535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 539system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 541system.cpu.l2cache.fast_writes 0 # number of fast writes performed 542system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 559system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles 560system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles 561system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles 562system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles 563system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles 564system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles 565system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses 566system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses | 578system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 579system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 580system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 581system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 582system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 583system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 584system.cpu.l2cache.fast_writes 0 # number of fast writes performed 585system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 16 unchanged lines hidden (view full) --- 602system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 10590500 # number of demand (read+write) MSHR miss cycles 603system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 4462000 # number of demand (read+write) MSHR miss cycles 604system.cpu.l2cache.demand_mshr_miss_latency::total 15052500 # number of demand (read+write) MSHR miss cycles 605system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 10590500 # number of overall MSHR miss cycles 606system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 4462000 # number of overall MSHR miss cycles 607system.cpu.l2cache.overall_mshr_miss_latency::total 15052500 # number of overall MSHR miss cycles 608system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for ReadReq accesses 609system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses |
| 610system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses |
|
| 567system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses | 611system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses |
| 612system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses |
|
| 568system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses 569system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses | 613system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for demand accesses 614system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses |
| 615system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses |
|
| 570system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses 571system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses | 616system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991279 # mshr miss rate for overall accesses 617system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses |
| 618system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses |
|
| 572system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency 573system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency | 619system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 31057.184751 # average ReadReq mshr miss latency 620system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 31406.593407 # average ReadReq mshr miss latency |
| 621system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency |
|
| 574system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency | 622system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 31450.980392 # average ReadExReq mshr miss latency |
| 623system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency |
|
| 575system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 576system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency | 624system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 625system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency |
| 626system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency |
|
| 577system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 578system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency | 627system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 31057.184751 # average overall mshr miss latency 628system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 31422.535211 # average overall mshr miss latency |
| 629system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency |
|
| 579system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 580 581---------- End Simulation Statistics ---------- | 630system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 631 632---------- End Simulation Statistics ---------- |