| stats.txt (8844:a451e4eda591) | stats.txt (8983:8800b05e1cb3) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 12671500 # Number of ticks simulated 5final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000013 # Number of seconds simulated 4sim_ticks 12671500 # Number of ticks simulated 5final_tick 12671500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 93816 # Simulator instruction rate (inst/s) 8host_op_rate 93786 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 229841550 # Simulator tick rate (ticks/s) 10host_mem_usage 211032 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host | 7host_inst_rate 56172 # Simulator instruction rate (inst/s) 8host_op_rate 56163 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 137660070 # Simulator tick rate (ticks/s) 10host_mem_usage 215596 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host |
| 12sim_insts 5169 # Number of instructions simulated 13sim_ops 5169 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30912 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 483 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 324 unchanged lines hidden (view full) --- 344system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses 345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency 346system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked | 12sim_insts 5169 # Number of instructions simulated 13sim_ops 5169 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read 30912 # Number of bytes read from this memory 15system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory 16system.physmem.bytes_written 0 # Number of bytes written to this memory 17system.physmem.num_reads 483 # Number of read requests responded to by this memory 18system.physmem.num_writes 0 # Number of write requests responded to by this memory 19system.physmem.num_other 0 # Number of other requests responded to by this memory --- 324 unchanged lines hidden (view full) --- 344system.cpu.icache.overall_miss_rate::cpu.inst 0.219225 # miss rate for overall accesses 345system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 35591.722595 # average ReadReq miss latency 346system.cpu.icache.demand_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 347system.cpu.icache.overall_avg_miss_latency::cpu.inst 35591.722595 # average overall miss latency 348system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 349system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 350system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 351system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked |
| 352system.cpu.icache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 352system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 353system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed 356system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits 357system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 358system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits 359system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits 360system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 426system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency 427system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency 428system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 429system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 430system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 431system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 433system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 354system.cpu.icache.fast_writes 0 # number of fast writes performed 355system.cpu.icache.cache_copies 0 # number of cache copies performed 356system.cpu.icache.ReadReq_mshr_hits::cpu.inst 103 # number of ReadReq MSHR hits 357system.cpu.icache.ReadReq_mshr_hits::total 103 # number of ReadReq MSHR hits 358system.cpu.icache.demand_mshr_hits::cpu.inst 103 # number of demand (read+write) MSHR hits 359system.cpu.icache.demand_mshr_hits::total 103 # number of demand (read+write) MSHR hits 360system.cpu.icache.overall_mshr_hits::cpu.inst 103 # number of overall MSHR hits 361system.cpu.icache.overall_mshr_hits::total 103 # number of overall MSHR hits --- 64 unchanged lines hidden (view full) --- 426system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 36289.473684 # average ReadReq miss latency 427system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 33609.144543 # average WriteReq miss latency 428system.cpu.dcache.demand_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 429system.cpu.dcache.overall_avg_miss_latency::cpu.data 34364.406780 # average overall miss latency 430system.cpu.dcache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 431system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 432system.cpu.dcache.blocked::no_mshrs 0 # number of cycles access was blocked 433system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 434system.cpu.dcache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 435system.cpu.dcache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 434system.cpu.dcache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 435system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 436system.cpu.dcache.fast_writes 0 # number of fast writes performed 437system.cpu.dcache.cache_copies 0 # number of cache copies performed 438system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits 439system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 440system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits 441system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits 442system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits 443system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked | 436system.cpu.dcache.fast_writes 0 # number of fast writes performed 437system.cpu.dcache.cache_copies 0 # number of cache copies performed 438system.cpu.dcache.ReadReq_mshr_hits::cpu.data 42 # number of ReadReq MSHR hits 439system.cpu.dcache.ReadReq_mshr_hits::total 42 # number of ReadReq MSHR hits 440system.cpu.dcache.WriteReq_mshr_hits::cpu.data 288 # number of WriteReq MSHR hits 441system.cpu.dcache.WriteReq_mshr_hits::total 288 # number of WriteReq MSHR hits 442system.cpu.dcache.demand_mshr_hits::cpu.data 330 # number of demand (read+write) MSHR hits 443system.cpu.dcache.demand_mshr_hits::total 330 # number of demand (read+write) MSHR hits --- 87 unchanged lines hidden (view full) --- 531system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 532system.cpu.l2cache.demand_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 533system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 34284.457478 # average overall miss latency 534system.cpu.l2cache.overall_avg_miss_latency::cpu.data 34584.507042 # average overall miss latency 535system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 536system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 537system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 538system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked |
| 539system.cpu.l2cache.avg_blocked_cycles::no_mshrs no_value # average number of cycles each access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_targets no_value # average number of cycles each access was blocked | 539system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 540system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 541system.cpu.l2cache.fast_writes 0 # number of fast writes performed 542system.cpu.l2cache.cache_copies 0 # number of cache copies performed 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- | 541system.cpu.l2cache.fast_writes 0 # number of fast writes performed 542system.cpu.l2cache.cache_copies 0 # number of cache copies performed 543system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 341 # number of ReadReq MSHR misses 544system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 545system.cpu.l2cache.ReadReq_mshr_misses::total 432 # number of ReadReq MSHR misses 546system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 547system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 548system.cpu.l2cache.demand_mshr_misses::cpu.inst 341 # number of demand (read+write) MSHR misses --- 33 unchanged lines hidden --- |