| stats.txt (11687:b3d5f0e9e258) | stats.txt (11731:c473ca7cc650) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24405000 # Number of ticks simulated 5final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24405000 # Number of ticks simulated 5final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 123007 # Simulator instruction rate (inst/s) 8host_op_rate 122970 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 600170719 # Simulator tick rate (ticks/s) 10host_mem_usage 251144 # Number of bytes of host memory used 11host_seconds 0.04 # Real time elapsed on the host | 7host_inst_rate 38911 # Simulator instruction rate (inst/s) 8host_op_rate 38904 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 189891987 # Simulator tick rate (ticks/s) 10host_mem_usage 234100 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host |
| 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30016 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation | 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 17system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30016 # Number of bytes read from this memory --- 176 unchanged lines hidden (view full) --- 196system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation |
| 204system.physmem.totQLat 7578250 # Total ticks spent queuing 205system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM | 204system.physmem.totQLat 7577250 # Total ticks spent queuing 205system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM |
| 206system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers |
| 207system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst | 209system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst |
| 210system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 9.61 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 6 unchanged lines hidden (view full) --- 224system.physmem.avgGap 51824.09 # Average gap between requests 225system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) | 210system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 212system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 215system.physmem.busUtil 9.61 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 6 unchanged lines hidden (view full) --- 224system.physmem.avgGap 51824.09 # Average gap between requests 225system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) |
| 232system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ) | 232system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ) |
| 233system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) | 233system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) |
| 234system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ) | 234system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ) |
| 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) 237system.physmem_0.averagePower 566.830977 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states | 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) 237system.physmem_0.averagePower 566.830977 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states |
| 242system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states | 242system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states |
| 243system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states | 243system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states |
| 244system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states | 244system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states |
| 245system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) --- 41 unchanged lines hidden (view full) --- 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 7 # Number of system calls 298system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 48811 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 245system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) --- 41 unchanged lines hidden (view full) --- 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 7 # Number of system calls 298system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 48811 # number of cpu cycles simulated 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 302system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss | 302system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss |
| 303system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing 308system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 309system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 310system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed | 303system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing 308system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 309system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 310system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed |
| 311system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total) |
| 314system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 314system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 315system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total) |
| 316system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 316system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) 324system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 327system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total) | 327system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total) |
| 328system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle 329system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle 330system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle | 328system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle 329system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle 330system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle |
| 331system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked | 331system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked |
| 332system.cpu.decode.RunCycles 2768 # Number of cycles decode is running 333system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking 334system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing 335system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 336system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction 337system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode 338system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode 339system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing 340system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle | 332system.cpu.decode.RunCycles 2768 # Number of cycles decode is running 333system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking 334system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing 335system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 336system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction 337system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode 338system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode 339system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing 340system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle |
| 341system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking | 341system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking |
| 342system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst 343system.cpu.rename.RunCycles 2740 # Number of cycles rename is running 344system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking 345system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename 346system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 347system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 348system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full 349system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full 350system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups 353system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 354system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed 355system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing 356system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 358system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer | 342system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst 343system.cpu.rename.RunCycles 2740 # Number of cycles rename is running 344system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking 345system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename 346system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 347system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full 348system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full 349system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full 350system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups 353system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 354system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed 355system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing 356system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed 358system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer |
| 359system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit. | 359system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. |
| 361system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. | 361system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. |
| 363system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec) | 363system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec) |
| 364system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ | 364system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ |
| 365system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued | 365system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued |
| 366system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued | 366system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued |
| 367system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph | 367system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph |
| 369system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed | 369system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| 370system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle | 370system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle |
| 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 374system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle |
| 378system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 378system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle 382system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 386system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle | 386system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle |
| 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available --- 23 unchanged lines hidden (view full) --- 418system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 419system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 423system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 388system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available --- 23 unchanged lines hidden (view full) --- 418system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 419system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available 420system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available 421system.cpu.iq.fu_full::FloatMemRead 0 0.00% 100.00% # attempts to use FU when none available 422system.cpu.iq.fu_full::FloatMemWrite 0 0.00% 100.00% # attempts to use FU when none available 423system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 424system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 425system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 426system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued 427system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued 428system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued 457system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued | 426system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued 427system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued 428system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued 431system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued 432system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued 433system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued 434system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued 435system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued 436system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued 451system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued 452system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued 453system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued 454system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued 455system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued 456system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued 457system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued |
| 458system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 458system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued 459system.cpu.iq.FU_type_0::FloatMemRead 0 0.00% 100.00% # Type of FU issued 460system.cpu.iq.FU_type_0::FloatMemWrite 0 0.00% 100.00% # Type of FU issued 461system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 462system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 463system.cpu.iq.FU_type_0::total 8119 # Type of FU issued 464system.cpu.iq.rate 0.166335 # Inst issue rate | 463system.cpu.iq.FU_type_0::total 8118 # Type of FU issued 464system.cpu.iq.rate 0.166315 # Inst issue rate |
| 465system.cpu.iq.fu_busy_cnt 180 # FU busy when requested | 465system.cpu.iq.fu_busy_cnt 180 # FU busy when requested |
| 466system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses | 466system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst) 467system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads 468system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes 469system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses |
| 470system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses | 470system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 471system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 472system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses |
| 473system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses | 473system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses |
| 474system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 474system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 475system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 476system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 477system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed | 477system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed |
| 478system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations | 478system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 479system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations |
| 480system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed | 480system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed |
| 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 483system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 486system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing | 481system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 482system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 483system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 484system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 485system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 486system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing |
| 487system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking | 487system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking |
| 488system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking | 488system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking |
| 489system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ | 489system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ |
| 490system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch | 490system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch |
| 491system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions | 491system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions 492system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions |
| 493system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute | 493system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 494system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall 495system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall 496system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 497system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 498system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly 499system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute |
| 500system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute | 500system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions 501system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed 502system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute |
| 503system.cpu.iew.exec_swp 0 # number of swp insts executed | 503system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 504system.cpu.iew.exec_nop 1599 # number of nop insts executed 505system.cpu.iew.exec_refs 3179 # number of memory reference insts executed 506system.cpu.iew.exec_branches 1364 # Number of branches executed | 504system.cpu.iew.exec_nop 1596 # number of nop insts executed 505system.cpu.iew.exec_refs 3178 # number of memory reference insts executed 506system.cpu.iew.exec_branches 1363 # Number of branches executed |
| 507system.cpu.iew.exec_stores 1049 # Number of stores executed | 507system.cpu.iew.exec_stores 1049 # Number of stores executed |
| 508system.cpu.iew.exec_rate 0.159636 # Inst execution rate 509system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 7340 # cumulative count of insts written-back | 508system.cpu.iew.exec_rate 0.159595 # Inst execution rate 509system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit 510system.cpu.iew.wb_count 7339 # cumulative count of insts written-back |
| 511system.cpu.iew.wb_producers 2867 # num instructions producing a value | 511system.cpu.iew.wb_producers 2867 # num instructions producing a value |
| 512system.cpu.iew.wb_consumers 4275 # num instructions consuming a value 513system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle 514system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back 515system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit | 512system.cpu.iew.wb_consumers 4274 # num instructions consuming a value 513system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle 514system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back 515system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit |
| 516system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 517system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted 518system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle --- 53 unchanged lines hidden (view full) --- 577system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 582system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::total 5640 # Class of committed instruction 584system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached | 516system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards 517system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted 518system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle 523system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle --- 53 unchanged lines hidden (view full) --- 577system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 578system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 579system.cpu.commit.op_class_0::FloatMemRead 0 0.00% 100.00% # Class of committed instruction 580system.cpu.commit.op_class_0::FloatMemWrite 0 0.00% 100.00% # Class of committed instruction 581system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 582system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 583system.cpu.commit.op_class_0::total 5640 # Class of committed instruction 584system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached |
| 585system.cpu.rob.rob_reads 24808 # The number of ROB reads 586system.cpu.rob.rob_writes 22150 # The number of ROB writes | 585system.cpu.rob.rob_reads 24800 # The number of ROB reads 586system.cpu.rob.rob_writes 22133 # The number of ROB writes |
| 587system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself | 587system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 588system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling | 588system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 589system.cpu.committedInsts 4999 # Number of Instructions Simulated 590system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated 591system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction 592system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads 593system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle 594system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads | 589system.cpu.committedInsts 4999 # Number of Instructions Simulated 590system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated 591system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction 592system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads 593system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle 594system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads |
| 595system.cpu.int_regfile_reads 10563 # number of integer regfile reads | 595system.cpu.int_regfile_reads 10560 # number of integer regfile reads |
| 596system.cpu.int_regfile_writes 5141 # number of integer regfile writes 597system.cpu.fp_regfile_reads 3 # number of floating regfile reads 598system.cpu.fp_regfile_writes 1 # number of floating regfile writes 599system.cpu.misc_regfile_reads 161 # number of misc regfile reads 600system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 601system.cpu.dcache.tags.replacements 0 # number of replacements | 596system.cpu.int_regfile_writes 5141 # number of integer regfile writes 597system.cpu.fp_regfile_reads 3 # number of floating regfile reads 598system.cpu.fp_regfile_writes 1 # number of floating regfile writes 599system.cpu.misc_regfile_reads 161 # number of misc regfile reads 600system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 601system.cpu.dcache.tags.replacements 0 # number of replacements |
| 602system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks. | 602system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use 603system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. |
| 604system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. | 604system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. |
| 605system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks. | 605system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. |
| 606system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 606system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 607system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor | 607system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor |
| 608system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id 613system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id | 608system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy 609system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy 610system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 611system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 612system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id 613system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id |
| 614system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses | 614system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 615system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses |
| 616system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states | 616system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 617system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits 618system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits | 617system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits 618system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits |
| 619system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits 620system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits | 619system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits 620system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits |
| 621system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits 622system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits 623system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits 624system.cpu.dcache.overall_hits::total 2396 # number of overall hits | 621system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 622system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 623system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 624system.cpu.dcache.overall_hits::total 2395 # number of overall hits |
| 625system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 626system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 627system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses 628system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses 629system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 630system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 631system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 632system.cpu.dcache.overall_misses::total 511 # number of overall misses | 625system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 626system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses 627system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses 628system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses 629system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 630system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 631system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 632system.cpu.dcache.overall_misses::total 511 # number of overall misses |
| 633system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles 634system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles | 633system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles 634system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles |
| 635system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles | 635system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles 636system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles |
| 637system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) | 637system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles 638system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles 639system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles 640system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles 641system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses) 642system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses) |
| 643system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) | 643system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 644system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) |
| 645system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses 646system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses 647system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses 648system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses 649system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses | 645system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses 646system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses 647system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses 648system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses 649system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses 650system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses |
| 651system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses | 651system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses 652system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses |
| 653system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses 654system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses 655system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses 656system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses 657system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency 658system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency | 653system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses 654system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses 655system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses 656system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses 657system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency 658system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency |
| 659system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency | 659system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency 660system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency |
| 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency | 661system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency 662system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency 663system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency 664system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency |
| 665system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked 666system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 671system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 672system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 683system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses | 665system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked 666system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 667system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 668system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 669system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked 670system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 671system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 672system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits --- 6 unchanged lines hidden (view full) --- 679system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 680system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 681system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 682system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 683system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 684system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 685system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 686system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses |
| 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles | 687system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles 688system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles |
| 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles | 689system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles 690system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles |
| 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses | 691system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles 692system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles 693system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles 694system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles 695system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses 696system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses |
| 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses | 697system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 698system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses |
| 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency | 699system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses 700system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses 701system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses 702system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses 703system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency 704system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency |
| 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency | 705system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency 706system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency |
| 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency | 707system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency 708system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency 709system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency 710system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency |
| 711system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 712system.cpu.icache.tags.replacements 17 # number of replacements 713system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use 714system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 715system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 716system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. 717system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 718system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor --- 57 unchanged lines hidden (view full) --- 776system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 777system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits 778system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 779system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 780system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 781system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 782system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 783system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses | 711system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 712system.cpu.icache.tags.replacements 17 # number of replacements 713system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use 714system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. 715system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 716system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. 717system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 718system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor --- 57 unchanged lines hidden (view full) --- 776system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 777system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits 778system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 779system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 780system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 781system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 782system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 783system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses |
| 784system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles 785system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles 786system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles 787system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles 788system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles 789system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles | 784system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles 785system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles 786system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles 787system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles 788system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles 789system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles |
| 790system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 791system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 792system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 793system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 794system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 795system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses | 790system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 791system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 792system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 793system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 794system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 795system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses |
| 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency 799system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency 801system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency | 796system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency 797system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency 798system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency 799system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency 800system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency 801system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency |
| 802system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 803system.cpu.l2cache.tags.replacements 0 # number of replacements | 802system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 803system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 804system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use | 804system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use |
| 805system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 806system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 807system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 808system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 809system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor | 805system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 806system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 807system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 808system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 809system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor |
| 810system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor | 810system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor |
| 811system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 817system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 818system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses --- 16 unchanged lines hidden (view full) --- 835system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 840system.cpu.l2cache.overall_misses::total 469 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles | 811system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy 812system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy 813system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy 814system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id 815system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 816system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id 817system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 818system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses --- 16 unchanged lines hidden (view full) --- 835system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 836system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 837system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 838system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 839system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 840system.cpu.l2cache.overall_misses::total 469 # number of overall misses 841system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles 842system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles |
| 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles | 843system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles 844system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles 845system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles 846system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles 847system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles 848system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles 849system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles 850system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles 851system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles 852system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles |
| 853system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 854system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 858system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 859system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 860system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 873system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 874system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 875system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 876system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 877system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 878system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 879system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency | 853system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 854system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 855system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 856system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 857system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 858system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 859system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 860system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) --- 12 unchanged lines hidden (view full) --- 873system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 874system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 875system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 876system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 877system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 878system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses 879system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency 880system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency |
| 881system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency 882system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency 883system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency 884system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency 885system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency 886system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency 887system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency | 881system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency 882system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency 883system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency 884system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency 885system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency 886system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency 887system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency 888system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency 889system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency 890system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency |
| 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 897system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 898system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 903system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 905system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 906system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 907system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 908system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 909system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles 910system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles | 891system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 892system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 893system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 894system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 895system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 896system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 897system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 898system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses --- 4 unchanged lines hidden (view full) --- 903system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 904system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 905system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 906system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 907system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 908system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses 909system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles 910system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles |
| 911system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles 912system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles 913system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles 914system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles 917system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles 919system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles 920system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles | 911system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles 912system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles 913system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles 914system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles 915system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles 916system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles 917system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles 918system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles 919system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles 920system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles |
| 921system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 922system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 923system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 924system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 925system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 926system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 927system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 928system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 929system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 930system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 931system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 932system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 933system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency 934system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency | 921system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 922system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 923system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 924system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 925system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 926system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 927system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 928system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 929system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 930system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 931system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 932system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses 933system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency 934system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency |
| 935system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency 936system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency 937system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency 938system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency 940system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency 941system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency 943system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency 944system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency | 935system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency 936system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency 937system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency 938system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency 939system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency 940system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency 941system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency 942system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency 943system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency 944system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency |
| 945system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 946system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 947system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 948system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 949system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 950system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 951system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 952system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1002system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1003system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1004system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 1005system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1006system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1007system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1008system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1009system.membus.snoop_fanout::total 469 # Request fanout histogram | 945system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 946system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 947system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 948system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 949system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 950system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 951system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 952system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution --- 49 unchanged lines hidden (view full) --- 1002system.membus.snoop_fanout::stdev 0 # Request fanout histogram 1003system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 1004system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 1005system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 1006system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 1007system.membus.snoop_fanout::min_value 0 # Request fanout histogram 1008system.membus.snoop_fanout::max_value 0 # Request fanout histogram 1009system.membus.snoop_fanout::total 469 # Request fanout histogram |
| 1010system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) | 1010system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks) |
| 1011system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 1012system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) 1013system.membus.respLayer1.utilization 10.2 # Layer utilization (%) 1014 1015---------- End Simulation Statistics ---------- | 1011system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 1012system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) 1013system.membus.respLayer1.utilization 10.2 # Layer utilization (%) 1014 1015---------- End Simulation Statistics ---------- |