| stats.txt (11606:6b749761c398) | stats.txt (11680:b4d943429dc6) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22838000 # Number of ticks simulated 5final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000024 # Number of seconds simulated 4sim_ticks 24405000 # Number of ticks simulated 5final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 76246 # Simulator instruction rate (inst/s) 8host_op_rate 76230 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 348191953 # Simulator tick rate (ticks/s) 10host_mem_usage 252304 # Number of bytes of host memory used 11host_seconds 0.07 # Real time elapsed on the host | 7host_inst_rate 101939 # Simulator instruction rate (inst/s) 8host_op_rate 101907 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 497362491 # Simulator tick rate (ticks/s) 10host_mem_usage 250452 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host |
| 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 16system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 17system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 469 # Number of read requests responded to by this memory | 17system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 469 # Number of read requests responded to by this memory |
| 25system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s) | 25system.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s) 30system.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s) 32system.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s) |
| 33system.physmem.readReqs 469 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 33system.physmem.readReqs 469 # Number of read requests accepted 34system.physmem.writeReqs 0 # Number of write requests accepted 35system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue 36system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 37system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM 38system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 39system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 40system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 71system.physmem.perBankWrBursts::10 0 # Per bank write bursts 72system.physmem.perBankWrBursts::11 0 # Per bank write bursts 73system.physmem.perBankWrBursts::12 0 # Per bank write bursts 74system.physmem.perBankWrBursts::13 0 # Per bank write bursts 75system.physmem.perBankWrBursts::14 0 # Per bank write bursts 76system.physmem.perBankWrBursts::15 0 # Per bank write bursts 77system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 78system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 79system.physmem.totGap 22751500 # Total gap between requests | 79system.physmem.totGap 24305500 # Total gap between requests |
| 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 469 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) | 80system.physmem.readPktSize::0 0 # Read request sizes (log2) 81system.physmem.readPktSize::1 0 # Read request sizes (log2) 82system.physmem.readPktSize::2 0 # Read request sizes (log2) 83system.physmem.readPktSize::3 0 # Read request sizes (log2) 84system.physmem.readPktSize::4 0 # Read request sizes (log2) 85system.physmem.readPktSize::5 0 # Read request sizes (log2) 86system.physmem.readPktSize::6 469 # Read request sizes (log2) 87system.physmem.writePktSize::0 0 # Write request sizes (log2) 88system.physmem.writePktSize::1 0 # Write request sizes (log2) 89system.physmem.writePktSize::2 0 # Write request sizes (log2) 90system.physmem.writePktSize::3 0 # Write request sizes (log2) 91system.physmem.writePktSize::4 0 # Write request sizes (log2) 92system.physmem.writePktSize::5 0 # Write request sizes (log2) 93system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 94system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see |
| 97system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see | 97system.physmem.rdQLenPdf::3 17 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 98system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see |
| 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 99system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 106system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 182system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 189system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 190system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 203system.physmem.totQLat 4619250 # Total ticks spent queuing 204system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM | 190system.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation 194system.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation 203system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation 204system.physmem.totQLat 7578250 # Total ticks spent queuing 205system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers | 206system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst | 207system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s | 209system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s | 212system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 10.27 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads | 215system.physmem.busUtil 9.61 # Data bus utilization in percentage 216system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing | 218system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing | 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing |
| 219system.physmem.readRowHits 353 # Number of row buffer hits during reads | 220system.physmem.readRowHits 352 # Number of row buffer hits during reads |
| 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes | 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes |
| 221system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads | 222system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads |
| 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 48510.66 # Average gap between requests 224system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined 225system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ) | 224system.physmem.avgGap 51824.09 # Average gap between requests 225system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined 226system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ) 227system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ) 228system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) | 229system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 230system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ) 233system.physmem_0.averagePower 783.164377 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states 237system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states 239system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ) | 230system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 231system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ) 232system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ) 233system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ) 234system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ) 235system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 236system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ) 237system.physmem_0.averagePower 566.830977 # Core power per rank (mW) 238system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank 239system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states 240system.physmem_0.memoryStateTime::REF 780000 # Time in different power states 241system.physmem_0.memoryStateTime::SREF 0 # Time in different power states 242system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states 243system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states 244system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states 245system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ) 246system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ) 247system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) | 248system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) |
| 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) 244system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ) 247system.physmem_1.averagePower 935.350071 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states 253system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 254system.cpu.branchPred.lookups 2189 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect | 249system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ) 250system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ) 251system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ) 252system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ) 253system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ) 254system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ) 255system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ) 256system.physmem_1.averagePower 675.693915 # Core power per rank (mW) 257system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank 258system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states 259system.physmem_1.memoryStateTime::REF 780000 # Time in different power states 260system.physmem_1.memoryStateTime::SREF 0 # Time in different power states 261system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states 262system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states 263system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states 264system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 265system.cpu.branchPred.lookups 2188 # Number of BP lookups 266system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted 267system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect |
| 257system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 587 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage | 268system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups 269system.cpu.branchPred.BTBHits 587 # Number of BTB hits 270system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 271system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage |
| 261system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target. | 272system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target. |
| 262system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 263system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. 264system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. 265system.cpu.branchPred.indirectMisses 268 # Number of indirect misses. | 273system.cpu.branchPred.RASInCorrect 70 # Number of incorrect RAS predictions. 274system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups. 275system.cpu.branchPred.indirectHits 2 # Number of indirect target hits. 276system.cpu.branchPred.indirectMisses 268 # Number of indirect misses. |
| 266system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches. | 277system.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches. |
| 267system.cpu_clk_domain.clock 500 # Clock period in ticks 268system.cpu.dtb.read_hits 0 # DTB read hits 269system.cpu.dtb.read_misses 0 # DTB read misses 270system.cpu.dtb.read_accesses 0 # DTB read accesses 271system.cpu.dtb.write_hits 0 # DTB write hits 272system.cpu.dtb.write_misses 0 # DTB write misses 273system.cpu.dtb.write_accesses 0 # DTB write accesses 274system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 279system.cpu.itb.read_accesses 0 # DTB read accesses 280system.cpu.itb.write_hits 0 # DTB write hits 281system.cpu.itb.write_misses 0 # DTB write misses 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 7 # Number of system calls | 278system.cpu_clk_domain.clock 500 # Clock period in ticks 279system.cpu.dtb.read_hits 0 # DTB read hits 280system.cpu.dtb.read_misses 0 # DTB read misses 281system.cpu.dtb.read_accesses 0 # DTB read accesses 282system.cpu.dtb.write_hits 0 # DTB write hits 283system.cpu.dtb.write_misses 0 # DTB write misses 284system.cpu.dtb.write_accesses 0 # DTB write accesses 285system.cpu.dtb.hits 0 # DTB hits --- 4 unchanged lines hidden (view full) --- 290system.cpu.itb.read_accesses 0 # DTB read accesses 291system.cpu.itb.write_hits 0 # DTB write hits 292system.cpu.itb.write_misses 0 # DTB write misses 293system.cpu.itb.write_accesses 0 # DTB write accesses 294system.cpu.itb.hits 0 # DTB hits 295system.cpu.itb.misses 0 # DTB misses 296system.cpu.itb.accesses 0 # DTB accesses 297system.cpu.workload.num_syscalls 7 # Number of system calls |
| 287system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states 288system.cpu.numCycles 45677 # number of cpu cycles simulated | 298system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states 299system.cpu.numCycles 48811 # number of cpu cycles simulated |
| 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 300system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 301system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 291system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss 292system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed 293system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered 294system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken 295system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked 296system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing | 302system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss 303system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed 304system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered 305system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken 306system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked 307system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing |
| 297system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 298system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 299system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed | 308system.cpu.fetch.PendingTrapStallCycles 205 # Number of stall cycles due to pending traps 309system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched 310system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed |
| 300system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total) | 311system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total) 313system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total) |
| 303system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 314system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 304system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total) 307system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total) 310system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total) 312system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total) | 315system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total) 316system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total) 318system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total) 319system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total) 320system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total) 321system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total) 322system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total) 323system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total) |
| 313system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 314system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 315system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 324system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 325system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 326system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 316system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total) 317system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle 318system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle 319system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle 320system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked 321system.cpu.decode.RunCycles 2777 # Number of cycles decode is running 322system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking 323system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing | 327system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total) 328system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle 329system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle 330system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle 331system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked 332system.cpu.decode.RunCycles 2768 # Number of cycles decode is running 333system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking 334system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing |
| 324system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 325system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction | 335system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch 336system.cpu.decode.BranchMispred 40 # Number of times decode detected a branch misprediction |
| 326system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode | 337system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode |
| 327system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode | 338system.cpu.decode.SquashedInsts 160 # Number of squashed instructions handled by decode |
| 328system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 329system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle 330system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking 331system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst 332system.cpu.rename.RunCycles 2748 # Number of cycles rename is running 333system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking 334system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename | 339system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing 340system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle 341system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking 342system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst 343system.cpu.rename.RunCycles 2740 # Number of cycles rename is running 344system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking 345system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename |
| 335system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 336system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full | 346system.cpu.rename.ROBFullEvents 5 # Number of times rename has blocked due to ROB full 347system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full |
| 337system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full 338system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full 339system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed 340system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made 341system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups | 348system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full 349system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full 350system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed 351system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made 352system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups |
| 342system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 343system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed | 353system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 354system.cpu.rename.CommittedMaps 3292 # Number of HB maps that are committed |
| 344system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing | 355system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing |
| 345system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 346system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed | 356system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 357system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed |
| 347system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer 348system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit. 349system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit. | 358system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer 359system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit. 360system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit. |
| 350system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 351system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. | 361system.cpu.memDep0.conflictingLoads 6 # Number of conflicting loads. 362system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. |
| 352system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec) 353system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ 354system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued | 363system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec) 364system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ 365system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued |
| 355system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued | 366system.cpu.iq.iqSquashedInstsIssued 19 # Number of squashed instructions issued |
| 356system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling 357system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph 358system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed 359system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle | 367system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling 368system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph 369system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed 370system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle 371system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle |
| 362system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 373system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 363system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle 366system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle 369system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle 370system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle | 374system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle 375system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle 376system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle 377system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle 378system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle 379system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle 380system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle 381system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle |
| 371system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 372system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 373system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 374system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 382system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle 383system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 384system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 385system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 375system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle | 386system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle |
| 376system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 387system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 377system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available 378system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available 379system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available 380system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available 381system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available 382system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available 383system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available 384system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available 385system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available 406system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available 407system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available | 388system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available 389system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available 390system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available 391system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available 392system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available 393system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available 394system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available 395system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available 396system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available 400system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available 401system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available 402system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available 403system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available 404system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available 405system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available 406system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available 407system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available 408system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available 409system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available 410system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available 411system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available 412system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available 413system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available 414system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available 415system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available 416system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available 417system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available 418system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available |
| 408system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 409system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 410system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 419system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 420system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 421system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 411system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued 412system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued 413system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued 414system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued 415system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued 416system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued 417system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued 418system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued 419system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued 440system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued 441system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued | 422system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued 423system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued 424system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued 425system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued 426system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued 427system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued 428system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued 429system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued 430system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued 434system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued 435system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued 436system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued 437system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued 438system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued 439system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued 440system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued 441system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued 442system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued 443system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued 444system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued 445system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued 446system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued 447system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued 448system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued 449system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued 450system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued 451system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued 452system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued |
| 442system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 443system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 453system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 454system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 444system.cpu.iq.FU_type_0::total 8125 # Type of FU issued 445system.cpu.iq.rate 0.177879 # Inst issue rate 446system.cpu.iq.fu_busy_cnt 181 # FU busy when requested 447system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst) 448system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads 449system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes 450system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses | 455system.cpu.iq.FU_type_0::total 8119 # Type of FU issued 456system.cpu.iq.rate 0.166335 # Inst issue rate 457system.cpu.iq.fu_busy_cnt 180 # FU busy when requested 458system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst) 459system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads 460system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes 461system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses |
| 451system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 452system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 453system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses | 462system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 463system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 464system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses |
| 454system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses | 465system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses |
| 455system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 456system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 457system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 466system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 467system.cpu.iew.lsq.thread0.forwLoads 78 # Number of loads that had data forwarded from stores 468system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 458system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed | 469system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed |
| 459system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 460system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations | 470system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed 471system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations |
| 461system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed | 472system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed |
| 462system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 463system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 464system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 465system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 466system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 473system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 474system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 475system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 476system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked 477system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 467system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing | 478system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing |
| 468system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking | 479system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking |
| 469system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking 470system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ 471system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch 472system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions 473system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions 474system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions | 480system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking 481system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ 482system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch 483system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions 484system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions 485system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions |
| 475system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall | 486system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall |
| 476system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall | 487system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall |
| 477system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 478system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly | 488system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations 489system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly |
| 479system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly 480system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute 481system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions | 490system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly 491system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute 492system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions |
| 482system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed | 493system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed |
| 483system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute | 494system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute |
| 484system.cpu.iew.exec_swp 0 # number of swp insts executed | 495system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 485system.cpu.iew.exec_nop 1602 # number of nop insts executed | 496system.cpu.iew.exec_nop 1599 # number of nop insts executed |
| 486system.cpu.iew.exec_refs 3179 # number of memory reference insts executed | 497system.cpu.iew.exec_refs 3179 # number of memory reference insts executed |
| 487system.cpu.iew.exec_branches 1368 # Number of branches executed | 498system.cpu.iew.exec_branches 1364 # Number of branches executed |
| 488system.cpu.iew.exec_stores 1049 # Number of stores executed | 499system.cpu.iew.exec_stores 1049 # Number of stores executed |
| 489system.cpu.iew.exec_rate 0.170742 # Inst execution rate 490system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit 491system.cpu.iew.wb_count 7349 # cumulative count of insts written-back 492system.cpu.iew.wb_producers 2873 # num instructions producing a value 493system.cpu.iew.wb_consumers 4285 # num instructions consuming a value 494system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle 495system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back 496system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit | 500system.cpu.iew.exec_rate 0.159636 # Inst execution rate 501system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit 502system.cpu.iew.wb_count 7340 # cumulative count of insts written-back 503system.cpu.iew.wb_producers 2867 # num instructions producing a value 504system.cpu.iew.wb_consumers 4275 # num instructions consuming a value 505system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle 506system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back 507system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit |
| 497system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards | 508system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards |
| 498system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted 499system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle | 509system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted 510system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle 512system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle |
| 502system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 513system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 503system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle 508system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle 511system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle | 514system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle 515system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle 516system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle 517system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle 518system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle 519system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle 520system.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle 521system.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle 522system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle |
| 512system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 513system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 514system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 523system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 524system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 525system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 515system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle | 526system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle |
| 516system.cpu.commit.committedInsts 5640 # Number of instructions committed 517system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed 518system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 519system.cpu.commit.refs 2036 # Number of memory references committed 520system.cpu.commit.loads 1135 # Number of loads committed 521system.cpu.commit.membars 0 # Number of memory barriers committed 522system.cpu.commit.branches 886 # Number of branches committed 523system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 553system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction 554system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction 555system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction 556system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 557system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 558system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 559system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 560system.cpu.commit.op_class_0::total 5640 # Class of committed instruction | 527system.cpu.commit.committedInsts 5640 # Number of instructions committed 528system.cpu.commit.committedOps 5640 # Number of ops (including micro ops) committed 529system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 530system.cpu.commit.refs 2036 # Number of memory references committed 531system.cpu.commit.loads 1135 # Number of loads committed 532system.cpu.commit.membars 0 # Number of memory barriers committed 533system.cpu.commit.branches 886 # Number of branches committed 534system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 564system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.90% # Class of committed instruction 565system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.90% # Class of committed instruction 566system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.90% # Class of committed instruction 567system.cpu.commit.op_class_0::MemRead 1135 20.12% 84.02% # Class of committed instruction 568system.cpu.commit.op_class_0::MemWrite 901 15.98% 100.00% # Class of committed instruction 569system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 570system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 571system.cpu.commit.op_class_0::total 5640 # Class of committed instruction |
| 561system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached 562system.cpu.rob.rob_reads 24134 # The number of ROB reads 563system.cpu.rob.rob_writes 22169 # The number of ROB writes | 572system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached 573system.cpu.rob.rob_reads 24808 # The number of ROB reads 574system.cpu.rob.rob_writes 22150 # The number of ROB writes |
| 564system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself | 575system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself |
| 565system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling | 576system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 566system.cpu.committedInsts 4999 # Number of Instructions Simulated 567system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated | 577system.cpu.committedInsts 4999 # Number of Instructions Simulated 578system.cpu.committedOps 4999 # Number of Ops (including micro ops) Simulated |
| 568system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction 569system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads 570system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle 571system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads 572system.cpu.int_regfile_reads 10569 # number of integer regfile reads 573system.cpu.int_regfile_writes 5149 # number of integer regfile writes | 579system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction 580system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads 581system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle 582system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads 583system.cpu.int_regfile_reads 10563 # number of integer regfile reads 584system.cpu.int_regfile_writes 5141 # number of integer regfile writes |
| 574system.cpu.fp_regfile_reads 3 # number of floating regfile reads 575system.cpu.fp_regfile_writes 1 # number of floating regfile writes | 585system.cpu.fp_regfile_reads 3 # number of floating regfile reads 586system.cpu.fp_regfile_writes 1 # number of floating regfile writes |
| 576system.cpu.misc_regfile_reads 160 # number of misc regfile reads 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 587system.cpu.misc_regfile_reads 161 # number of misc regfile reads 588system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 578system.cpu.dcache.tags.replacements 0 # number of replacements | 589system.cpu.dcache.tags.replacements 0 # number of replacements |
| 579system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. | 590system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use 591system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks. |
| 581system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. | 592system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. |
| 582system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks. | 593system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks. |
| 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 594system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 584system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy | 595system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor 596system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy 597system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy |
| 587system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id | 598system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id |
| 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id | 599system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id 600system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id |
| 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses | 601system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 602system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses 603system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses |
| 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 604system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 594system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits | 605system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits 606system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits |
| 596system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 598system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits 599system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits 600system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits 601system.cpu.dcache.overall_hits::total 2395 # number of overall hits | 607system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits 608system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits 609system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits 610system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits 611system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits 612system.cpu.dcache.overall_hits::total 2396 # number of overall hits |
| 602system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 603system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses | 613system.cpu.dcache.ReadReq_misses::cpu.data 167 # number of ReadReq misses 614system.cpu.dcache.ReadReq_misses::total 167 # number of ReadReq misses |
| 604system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses 605system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses 606system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses 607system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses 608system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses 609system.cpu.dcache.overall_misses::total 512 # number of overall misses 610system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles 611system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles 612system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles 613system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles 614system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles 615system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles 616system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles 617system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles | 615system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses 616system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses 617system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses 618system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses 619system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses 620system.cpu.dcache.overall_misses::total 511 # number of overall misses 621system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles 622system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles 623system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles 624system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles 625system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles 626system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles 627system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles 628system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles |
| 618system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) 619system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) 620system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 621system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 622system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses 623system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses 624system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses 625system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses 626system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses 627system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses | 629system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses) 630system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses) 631system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 632system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) 633system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses 634system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses 635system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses 636system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses 637system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses 638system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses |
| 628system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses 629system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses 630system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses 631system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses 632system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses 633system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses 634system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency 635system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency 636system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency 637system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency 638system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency 639system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency 640system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency 641system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency 642system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked | 639system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses 640system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses 641system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses 642system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses 643system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses 644system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses 645system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency 646system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency 647system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency 648system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency 649system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency 650system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency 651system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency 652system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency 653system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked |
| 643system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 644system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 645system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 654system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 655system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 656system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 646system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked | 657system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked |
| 647system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 648system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 649system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits | 658system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 659system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 660system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits |
| 650system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 651system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 652system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits 653system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits 654system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits 655system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits | 661system.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits 662system.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits 663system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits 664system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits 665system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits 666system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits |
| 656system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 657system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 658system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 659system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 660system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 661system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 662system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 663system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses | 667system.cpu.dcache.ReadReq_mshr_misses::cpu.data 90 # number of ReadReq MSHR misses 668system.cpu.dcache.ReadReq_mshr_misses::total 90 # number of ReadReq MSHR misses 669system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 670system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 671system.cpu.dcache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 672system.cpu.dcache.demand_mshr_misses::total 140 # number of demand (read+write) MSHR misses 673system.cpu.dcache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 674system.cpu.dcache.overall_mshr_misses::total 140 # number of overall MSHR misses |
| 664system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles 665system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles 666system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles 667system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles 668system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles 669system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles 670system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles 671system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles | 675system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles 676system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles 677system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles 678system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles 679system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles 680system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles 681system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles 682system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles |
| 672system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses 673system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses 674system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 675system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 676system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses 677system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses 678system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses 679system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses | 683system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses 684system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses 685system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 686system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses 687system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses 688system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses 689system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses 690system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses |
| 680system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency 682system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency 684system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency 685system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency 686system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency 687system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency 688system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 691system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency 692system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency 693system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency 694system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency 695system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency 696system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency 697system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency 698system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency 699system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 689system.cpu.icache.tags.replacements 17 # number of replacements | 700system.cpu.icache.tags.replacements 17 # number of replacements |
| 690system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use 691system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks. | 701system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use 702system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks. |
| 692system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. | 703system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. |
| 693system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks. | 704system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks. |
| 694system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 705system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 695system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor 696system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy 697system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy | 706system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor 707system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy 708system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy |
| 698system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id | 709system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id |
| 699system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id | 710system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id 711system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id |
| 701system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 702system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 4432 # Number of data accesses | 712system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 713system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses 714system.cpu.icache.tags.data_accesses 4432 # Number of data accesses |
| 704system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states 705system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits 710system.cpu.icache.overall_hits::total 1612 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses 713system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses 714system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses 715system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses 716system.cpu.icache.overall_misses::total 438 # number of overall misses 717system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles 718system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles 719system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles 720system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles 721system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles 722system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles | 715system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states 716system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits 717system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits 718system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits 719system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits 720system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits 721system.cpu.icache.overall_hits::total 1613 # number of overall hits 722system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 723system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses 724system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses 725system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses 726system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses 727system.cpu.icache.overall_misses::total 437 # number of overall misses 728system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles 729system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles 730system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles 731system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles 732system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles 733system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles |
| 723system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) 724system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) 725system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses 726system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses 727system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses 728system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses | 734system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses) 735system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses) 736system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses 737system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses 738system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses 739system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses |
| 729system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses 730system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses 731system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses 732system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses 733system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses 734system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses 735system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency 736system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency 737system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency 738system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency 739system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency 740system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency | 740system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses 741system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses 742system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses 743system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses 744system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses 745system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses 746system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency 747system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency 748system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency 749system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency 750system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency 751system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency |
| 741system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 742system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 743system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 744system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 745system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 746system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 747system.cpu.icache.writebacks::writebacks 17 # number of writebacks 748system.cpu.icache.writebacks::total 17 # number of writebacks | 752system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 753system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 754system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 755system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 756system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 757system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 758system.cpu.icache.writebacks::writebacks 17 # number of writebacks 759system.cpu.icache.writebacks::total 17 # number of writebacks |
| 749system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits 750system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits 751system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits 752system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits 753system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits 754system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits | 760system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits 761system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 762system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits 763system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits 764system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 765system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits |
| 755system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 756system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 757system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 758system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 759system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 760system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses | 766system.cpu.icache.ReadReq_mshr_misses::cpu.inst 332 # number of ReadReq MSHR misses 767system.cpu.icache.ReadReq_mshr_misses::total 332 # number of ReadReq MSHR misses 768system.cpu.icache.demand_mshr_misses::cpu.inst 332 # number of demand (read+write) MSHR misses 769system.cpu.icache.demand_mshr_misses::total 332 # number of demand (read+write) MSHR misses 770system.cpu.icache.overall_mshr_misses::cpu.inst 332 # number of overall MSHR misses 771system.cpu.icache.overall_mshr_misses::total 332 # number of overall MSHR misses |
| 761system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles 762system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles 763system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles 764system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles 765system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles 766system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles | 772system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles 773system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles 774system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles 775system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles 776system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles 777system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles |
| 767system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 768system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 769system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 770system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 771system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 772system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses | 778system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses 779system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses 780system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses 781system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses 782system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses 783system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses |
| 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency 774system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency 776system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency 778system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency 779system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 784system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency 785system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency 786system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency 787system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency 788system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency 789system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency 790system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 780system.cpu.l2cache.tags.replacements 0 # number of replacements | 791system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 781system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use | 792system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use |
| 782system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 783system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 784system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 785system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 793system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 794system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks. 795system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks. 796system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 786system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy | 797system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor 798system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor 799system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy 800system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy 801system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy |
| 791system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id | 802system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id |
| 792system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id 793system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id | 803system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id 804system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id |
| 794system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 795system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 796system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses | 805system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id 806system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 807system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses |
| 797system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 808system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 798system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 799system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 800system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 801system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 802system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 805system.cpu.l2cache.overall_hits::total 3 # number of overall hits --- 4 unchanged lines hidden (view full) --- 810system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses 811system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 812system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 813system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 814system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 815system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 816system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 817system.cpu.l2cache.overall_misses::total 469 # number of overall misses | 809system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 810system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 811system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 812system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 813system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 814system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 815system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 816system.cpu.l2cache.overall_hits::total 3 # number of overall hits --- 4 unchanged lines hidden (view full) --- 821system.cpu.l2cache.ReadSharedReq_misses::cpu.data 90 # number of ReadSharedReq misses 822system.cpu.l2cache.ReadSharedReq_misses::total 90 # number of ReadSharedReq misses 823system.cpu.l2cache.demand_misses::cpu.inst 329 # number of demand (read+write) misses 824system.cpu.l2cache.demand_misses::cpu.data 140 # number of demand (read+write) misses 825system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses 826system.cpu.l2cache.overall_misses::cpu.inst 329 # number of overall misses 827system.cpu.l2cache.overall_misses::cpu.data 140 # number of overall misses 828system.cpu.l2cache.overall_misses::total 469 # number of overall misses |
| 818system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles 819system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles 820system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles 821system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles 822system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles 823system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles 824system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles 825system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles 826system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles 827system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles 828system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles 829system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles | 829system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles 830system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles 831system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles 832system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles 833system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles 834system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles 835system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles 836system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles 837system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles 838system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles 839system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles 840system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles |
| 830system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 831system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 832system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 833system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 834system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 835system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 836system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 837system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 848system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 849system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 850system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 851system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 852system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 853system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 854system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 855system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses | 841system.cpu.l2cache.WritebackClean_accesses::writebacks 17 # number of WritebackClean accesses(hits+misses) 842system.cpu.l2cache.WritebackClean_accesses::total 17 # number of WritebackClean accesses(hits+misses) 843system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 844system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 845system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 332 # number of ReadCleanReq accesses(hits+misses) 846system.cpu.l2cache.ReadCleanReq_accesses::total 332 # number of ReadCleanReq accesses(hits+misses) 847system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 90 # number of ReadSharedReq accesses(hits+misses) 848system.cpu.l2cache.ReadSharedReq_accesses::total 90 # number of ReadSharedReq accesses(hits+misses) --- 10 unchanged lines hidden (view full) --- 859system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses 860system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses 861system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990964 # miss rate for demand accesses 862system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 863system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses 864system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990964 # miss rate for overall accesses 865system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 866system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses |
| 856system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency 857system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency 858system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency 859system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency 860system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency 861system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency 862system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency 863system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency 864system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency 865system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency 866system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency 867system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency | 867system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency 868system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency 869system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency 870system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency 871system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency 872system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency 873system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency 874system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency 875system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency 876system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency 877system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency 878system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency |
| 868system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 869system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 870system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 871system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 872system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 873system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 874system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 875system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 876system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 877system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 878system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 879system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 880system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 881system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 882system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 883system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 884system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 885system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses | 879system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 880system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 881system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 882system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 883system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 884system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 885system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 886system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 887system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 888system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 889system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 890system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 891system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 892system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses 893system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses 894system.cpu.l2cache.overall_mshr_misses::cpu.inst 329 # number of overall MSHR misses 895system.cpu.l2cache.overall_mshr_misses::cpu.data 140 # number of overall MSHR misses 896system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses |
| 886system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles 887system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles 888system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles 889system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles 890system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles 891system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles 892system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles 893system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles 894system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles 895system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles 896system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles 897system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles | 897system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles 898system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles 899system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles 900system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles 901system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles 902system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles 903system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles 904system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles 905system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles 906system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles 907system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles 908system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles |
| 898system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 899system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 900system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 901system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 902system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 903system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 904system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 905system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 906system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 907system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 908system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 909system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses | 909system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 910system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 911system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for ReadCleanReq accesses 912system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990964 # mshr miss rate for ReadCleanReq accesses 913system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses 914system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses 915system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for demand accesses 916system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 917system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses 918system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990964 # mshr miss rate for overall accesses 919system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 920system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses |
| 910system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency 911system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency 912system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency 913system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency 918system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency | 921system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency 922system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency 923system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency 924system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency 925system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency 926system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency 927system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency 928system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency 929system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency 930system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency 931system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency 932system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency |
| 922system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 923system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 924system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 925system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 926system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 927system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 933system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 934system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 935system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 936system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 937system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 938system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 928system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 939system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 929system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 935system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) --- 12 unchanged lines hidden (view full) --- 949system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 950system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 951system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 953system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 954system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 955system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 956system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) | 940system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 941system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 942system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 943system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 944system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 945system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 946system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 947system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) --- 12 unchanged lines hidden (view full) --- 960system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 961system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 962system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram 963system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 964system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 965system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 966system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 967system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) |
| 957system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) | 968system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%) |
| 958system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 959system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 960system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. 961system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 962system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 963system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 964system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 965system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 969system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 970system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) 971system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter. 972system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data. 973system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 974system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 975system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 976system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 966system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states | 977system.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states |
| 967system.membus.trans_dist::ReadResp 419 # Transaction distribution 968system.membus.trans_dist::ReadExReq 50 # Transaction distribution 969system.membus.trans_dist::ReadExResp 50 # Transaction distribution 970system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 971system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 972system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 973system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 974system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 980system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 981system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 982system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 983system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 984system.membus.snoop_fanout::min_value 0 # Request fanout histogram 985system.membus.snoop_fanout::max_value 0 # Request fanout histogram 986system.membus.snoop_fanout::total 469 # Request fanout histogram 987system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) | 978system.membus.trans_dist::ReadResp 419 # Transaction distribution 979system.membus.trans_dist::ReadExReq 50 # Transaction distribution 980system.membus.trans_dist::ReadExResp 50 # Transaction distribution 981system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 982system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 983system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 984system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 985system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) --- 5 unchanged lines hidden (view full) --- 991system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 992system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram 993system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 994system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 995system.membus.snoop_fanout::min_value 0 # Request fanout histogram 996system.membus.snoop_fanout::max_value 0 # Request fanout histogram 997system.membus.snoop_fanout::total 469 # Request fanout histogram 998system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks) |
| 988system.membus.reqLayer0.utilization 2.5 # Layer utilization (%) 989system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks) 990system.membus.respLayer1.utilization 10.9 # Layer utilization (%) | 999system.membus.reqLayer0.utilization 2.4 # Layer utilization (%) 1000system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks) 1001system.membus.respLayer1.utilization 10.2 # Layer utilization (%) |
| 991 992---------- End Simulation Statistics ---------- | 1002 1003---------- End Simulation Statistics ---------- |