| stats.txt (11502:e273e86a873d) | stats.txt (11530:6e143fd2cabf) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22532000 # Number of ticks simulated 5final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22532000 # Number of ticks simulated 5final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 96442 # Simulator instruction rate (inst/s) 8host_op_rate 96403 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 434426491 # Simulator tick rate (ticks/s) 10host_mem_usage 247240 # Number of bytes of host memory used | 7host_inst_rate 107418 # Simulator instruction rate (inst/s) 8host_op_rate 107396 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 483974405 # Simulator tick rate (ticks/s) 10host_mem_usage 292720 # Number of bytes of host memory used |
| 11host_seconds 0.05 # Real time elapsed on the host 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks | 11host_seconds 0.05 # Real time elapsed on the host 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks |
| 16system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 16system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 469 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 244system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) 245system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ) 246system.physmem_1.averagePower 936.587399 # Core power per rank (mW) 247system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states 248system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 249system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 250system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states 251system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 17system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 18system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 19system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 20system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory 21system.physmem.bytes_inst_read::total 21056 # Number of instructions bytes read from this memory 22system.physmem.num_reads::cpu.inst 329 # Number of read requests responded to by this memory 23system.physmem.num_reads::cpu.data 140 # Number of read requests responded to by this memory 24system.physmem.num_reads::total 469 # Number of read requests responded to by this memory --- 220 unchanged lines hidden (view full) --- 245system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ) 247system.physmem_1.averagePower 936.587399 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states 251system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 252system.cpu.branchPred.lookups 2183 # Number of BP lookups 253system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted 254system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect 255system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups 256system.cpu.branchPred.BTBHits 587 # Number of BTB hits 257system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 258system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage 259system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 277system.cpu.itb.read_accesses 0 # DTB read accesses 278system.cpu.itb.write_hits 0 # DTB write hits 279system.cpu.itb.write_misses 0 # DTB write misses 280system.cpu.itb.write_accesses 0 # DTB write accesses 281system.cpu.itb.hits 0 # DTB hits 282system.cpu.itb.misses 0 # DTB misses 283system.cpu.itb.accesses 0 # DTB accesses 284system.cpu.workload.num_syscalls 7 # Number of system calls | 254system.cpu.branchPred.lookups 2183 # Number of BP lookups 255system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted 256system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect 257system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups 258system.cpu.branchPred.BTBHits 587 # Number of BTB hits 259system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 260system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage 261system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target. --- 17 unchanged lines hidden (view full) --- 279system.cpu.itb.read_accesses 0 # DTB read accesses 280system.cpu.itb.write_hits 0 # DTB write hits 281system.cpu.itb.write_misses 0 # DTB write misses 282system.cpu.itb.write_accesses 0 # DTB write accesses 283system.cpu.itb.hits 0 # DTB hits 284system.cpu.itb.misses 0 # DTB misses 285system.cpu.itb.accesses 0 # DTB accesses 286system.cpu.workload.num_syscalls 7 # Number of system calls |
| 287system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states |
|
| 285system.cpu.numCycles 45065 # number of cpu cycles simulated 286system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 287system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 288system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss 289system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed 290system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered 291system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken 292system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 566system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads 567system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 10573 # number of integer regfile reads 570system.cpu.int_regfile_writes 5151 # number of integer regfile writes 571system.cpu.fp_regfile_reads 3 # number of floating regfile reads 572system.cpu.fp_regfile_writes 1 # number of floating regfile writes 573system.cpu.misc_regfile_reads 160 # number of misc regfile reads | 288system.cpu.numCycles 45065 # number of cpu cycles simulated 289system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 290system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 291system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss 292system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed 293system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered 294system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken 295system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked --- 273 unchanged lines hidden (view full) --- 569system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads 570system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle 571system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads 572system.cpu.int_regfile_reads 10573 # number of integer regfile reads 573system.cpu.int_regfile_writes 5151 # number of integer regfile writes 574system.cpu.fp_regfile_reads 3 # number of floating regfile reads 575system.cpu.fp_regfile_writes 1 # number of floating regfile writes 576system.cpu.misc_regfile_reads 160 # number of misc regfile reads |
| 577system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 574system.cpu.dcache.tags.replacements 0 # number of replacements 575system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use 576system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. 577system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. 578system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks. 579system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 580system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor 581system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy 583system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 584system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 586system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 587system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses 588system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses | 578system.cpu.dcache.tags.replacements 0 # number of replacements 579system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use 580system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks. 581system.cpu.dcache.tags.sampled_refs 140 # Sample count of references to valid blocks. 582system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks. 583system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 584system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor 585system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy 586system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy 587system.cpu.dcache.tags.occ_task_id_blocks::1024 140 # Occupied blocks per task id 588system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 589system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id 590system.cpu.dcache.tags.occ_task_id_percent::1024 0.034180 # Percentage of cache occupancy per task id 591system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses 592system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses |
| 593system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 589system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits 596system.cpu.dcache.overall_hits::total 2393 # number of overall hits --- 78 unchanged lines hidden (view full) --- 675system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency 677system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency 679system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 680system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 681system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency | 594system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits 595system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits 596system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 597system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 598system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits 599system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits 600system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits 601system.cpu.dcache.overall_hits::total 2393 # number of overall hits --- 78 unchanged lines hidden (view full) --- 680system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency 681system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency 682system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency 683system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency 684system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 685system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 686system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 687system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency |
| 688system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 683system.cpu.icache.tags.replacements 17 # number of replacements 684system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use 685system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 686system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 687system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. 688system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 689system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor 690system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy 691system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy 692system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id 693system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 694system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 695system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 696system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses 697system.cpu.icache.tags.data_accesses 4426 # Number of data accesses | 689system.cpu.icache.tags.replacements 17 # number of replacements 690system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use 691system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 692system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 693system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. 694system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 695system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor 696system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy 697system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy 698system.cpu.icache.tags.occ_task_id_blocks::1024 315 # Occupied blocks per task id 699system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 700system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 701system.cpu.icache.tags.occ_task_id_percent::1024 0.153809 # Percentage of cache occupancy per task id 702system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses 703system.cpu.icache.tags.data_accesses 4426 # Number of data accesses |
| 704system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 698system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits 699system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits 700system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits 701system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits 702system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits 703system.cpu.icache.overall_hits::total 1610 # number of overall hits 704system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 705system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 764system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses 765system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency 767system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 769system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 771system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency | 705system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits 706system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits 707system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits 708system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits 709system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits 710system.cpu.icache.overall_hits::total 1610 # number of overall hits 711system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses 712system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses --- 58 unchanged lines hidden (view full) --- 771system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses 772system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses 773system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency 774system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency 775system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 776system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 777system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 778system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency |
| 779system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 772system.cpu.l2cache.tags.replacements 0 # number of replacements 773system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use 774system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 775system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 776system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 777system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 778system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor 780system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy 781system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy 782system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy 783system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 784system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 785system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 786system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id 787system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 788system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses | 780system.cpu.l2cache.tags.replacements 0 # number of replacements 781system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use 782system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 783system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 784system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 785system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 786system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor 787system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor 788system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy 789system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy 790system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy 791system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id 792system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 793system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id 794system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id 795system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses 796system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses |
| 797system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
|
| 789system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 790system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 791system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 792system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 793system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 794system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 795system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 796system.cpu.l2cache.overall_hits::total 3 # number of overall hits --- 114 unchanged lines hidden (view full) --- 911system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 912system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 913system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 914system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. | 798system.cpu.l2cache.WritebackClean_hits::writebacks 17 # number of WritebackClean hits 799system.cpu.l2cache.WritebackClean_hits::total 17 # number of WritebackClean hits 800system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits 801system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits 802system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 803system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 804system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits 805system.cpu.l2cache.overall_hits::total 3 # number of overall hits --- 114 unchanged lines hidden (view full) --- 920system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 921system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 922system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 923system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 924system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 925system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 926system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 927system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. |
| 928system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
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| 919system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 921system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 922system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 923system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 924system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 925system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 926system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 941system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 942system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 943system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 944system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 945system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) 946system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 947system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 948system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) | 929system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 930system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution 931system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 932system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 933system.cpu.toL2Bus.trans_dist::ReadCleanReq 332 # Transaction distribution 934system.cpu.toL2Bus.trans_dist::ReadSharedReq 90 # Transaction distribution 935system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 681 # Packet count per connected master and slave (bytes) 936system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 280 # Packet count per connected master and slave (bytes) --- 14 unchanged lines hidden (view full) --- 951system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram 952system.cpu.toL2Bus.snoop_fanout::total 472 # Request fanout histogram 953system.cpu.toL2Bus.reqLayer0.occupancy 261500 # Layer occupancy (ticks) 954system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%) 955system.cpu.toL2Bus.respLayer0.occupancy 498000 # Layer occupancy (ticks) 956system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%) 957system.cpu.toL2Bus.respLayer1.occupancy 210000 # Layer occupancy (ticks) 958system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%) |
| 959system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states |
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| 949system.membus.trans_dist::ReadResp 419 # Transaction distribution 950system.membus.trans_dist::ReadExReq 50 # Transaction distribution 951system.membus.trans_dist::ReadExResp 50 # Transaction distribution 952system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 953system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 954system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 955system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 956system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- | 960system.membus.trans_dist::ReadResp 419 # Transaction distribution 961system.membus.trans_dist::ReadExReq 50 # Transaction distribution 962system.membus.trans_dist::ReadExResp 50 # Transaction distribution 963system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution 964system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes) 965system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes) 966system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes) 967system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes) --- 17 unchanged lines hidden --- |