| stats.txt (11441:0edcf757b6a2) | stats.txt (11456:c0fb4435b80f) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22532000 # Number of ticks simulated 5final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22532000 # Number of ticks simulated 5final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 106399 # Simulator instruction rate (inst/s) 8host_op_rate 106364 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 479269632 # Simulator tick rate (ticks/s) 10host_mem_usage 251364 # Number of bytes of host memory used 11host_seconds 0.05 # Real time elapsed on the host | 7host_inst_rate 65525 # Simulator instruction rate (inst/s) 8host_op_rate 65509 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 295199371 # Simulator tick rate (ticks/s) 10host_mem_usage 251356 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory --- 615 unchanged lines hidden (view full) --- 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 12sim_insts 4999 # Number of instructions simulated 13sim_ops 4999 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21056 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 8960 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30016 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21056 # Number of instructions bytes read from this memory --- 615 unchanged lines hidden (view full) --- 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 643system.cpu.dcache.fast_writes 0 # number of fast writes performed 644system.cpu.dcache.cache_copies 0 # number of cache copies performed | |
| 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency | 643system.cpu.dcache.ReadReq_mshr_hits::cpu.data 77 # number of ReadReq MSHR hits 644system.cpu.dcache.ReadReq_mshr_hits::total 77 # number of ReadReq MSHR hits 645system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 646system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 647system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits 648system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits 649system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits 650system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits --- 24 unchanged lines hidden (view full) --- 675system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency 676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency 677system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency 678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency 679system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 680system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency 681system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency 682system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency |
| 685system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 686system.cpu.icache.tags.replacements 17 # number of replacements 687system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 689system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 690system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 692system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency 737system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 683system.cpu.icache.tags.replacements 17 # number of replacements 684system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use 685system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks. 686system.cpu.icache.tags.sampled_refs 332 # Sample count of references to valid blocks. 687system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks. 688system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 689system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor 690system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy --- 41 unchanged lines hidden (view full) --- 732system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency 733system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency 734system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 735system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 736system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 737system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 738system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 739system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed | |
| 745system.cpu.icache.writebacks::writebacks 17 # number of writebacks 746system.cpu.icache.writebacks::total 17 # number of writebacks 747system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits 748system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 749system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits 750system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits 751system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 752system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 769system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses 770system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses 771system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency 772system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency 773system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 774system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 775system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 776system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency | 740system.cpu.icache.writebacks::writebacks 17 # number of writebacks 741system.cpu.icache.writebacks::total 17 # number of writebacks 742system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits 743system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits 744system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits 745system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits 746system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits 747system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits --- 16 unchanged lines hidden (view full) --- 764system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses 765system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses 766system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency 767system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency 768system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 769system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency 770system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency 771system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency |
| 777system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 778system.cpu.l2cache.tags.replacements 0 # number of replacements 779system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use 780system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 781system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 782system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 783system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 784system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor 785system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 863system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency 864system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency 865system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 866system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 867system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 868system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 869system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 870system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked | 772system.cpu.l2cache.tags.replacements 0 # number of replacements 773system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use 774system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks. 775system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks. 776system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks. 777system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. 778system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor 779system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor --- 77 unchanged lines hidden (view full) --- 857system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency 858system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency 859system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 860system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 861system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 862system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 863system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 864system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked |
| 871system.cpu.l2cache.fast_writes 0 # number of fast writes performed 872system.cpu.l2cache.cache_copies 0 # number of cache copies performed | |
| 873system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 874system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 875system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 876system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 877system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 878system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 879system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 880system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 913system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency 914system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency 915system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 916system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 917system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 918system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 919system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 920system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency | 865system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 867system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 329 # number of ReadCleanReq MSHR misses 868system.cpu.l2cache.ReadCleanReq_mshr_misses::total 329 # number of ReadCleanReq MSHR misses 869system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 90 # number of ReadSharedReq MSHR misses 870system.cpu.l2cache.ReadSharedReq_mshr_misses::total 90 # number of ReadSharedReq MSHR misses 871system.cpu.l2cache.demand_mshr_misses::cpu.inst 329 # number of demand (read+write) MSHR misses 872system.cpu.l2cache.demand_mshr_misses::cpu.data 140 # number of demand (read+write) MSHR misses --- 32 unchanged lines hidden (view full) --- 905system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency 906system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency 907system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 908system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 909system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency 910system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency 911system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency 912system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency |
| 921system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate | |
| 922system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 923system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 924system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 925system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 926system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 927system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 928system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 929system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution --- 53 unchanged lines hidden --- | 913system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter. 914system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data. 915system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data. 916system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter. 917system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data. 918system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data. 919system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution 920system.cpu.toL2Bus.trans_dist::WritebackClean 17 # Transaction distribution --- 53 unchanged lines hidden --- |