| stats.txt (10726:8a20e2a1562d) | stats.txt (10736:4433fb00fa7d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22762000 # Number of ticks simulated 5final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 85129 # Simulator instruction rate (inst/s) 8host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) --- 541 unchanged lines hidden (view full) --- 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction 557system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22762000 # Number of ticks simulated 5final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks 7host_inst_rate 85129 # Simulator instruction rate (inst/s) 8host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) --- 541 unchanged lines hidden (view full) --- 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction 557system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached |
| 558system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | |
| 559system.cpu.rob.rob_reads 23990 # The number of ROB reads 560system.cpu.rob.rob_writes 21831 # The number of ROB writes 561system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling 563system.cpu.committedInsts 4986 # Number of Instructions Simulated 564system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated 565system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads --- 393 unchanged lines hidden --- | 558system.cpu.rob.rob_reads 23990 # The number of ROB reads 559system.cpu.rob.rob_writes 21831 # The number of ROB writes 560system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself 561system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling 562system.cpu.committedInsts 4986 # Number of Instructions Simulated 563system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated 564system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction 565system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads --- 393 unchanged lines hidden --- |