| stats.txt (10628:c9b7e0c69f88) | stats.txt (10726:8a20e2a1562d) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- | 1 2---------- Begin Simulation Statistics ---------- |
| 3sim_seconds 0.000021 # Number of seconds simulated 4sim_ticks 21163500 # Number of ticks simulated 5final_tick 21163500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 3sim_seconds 0.000023 # Number of seconds simulated 4sim_ticks 22762000 # Number of ticks simulated 5final_tick 22762000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 81533 # Simulator instruction rate (inst/s) 8host_op_rate 81515 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 345921870 # Simulator tick rate (ticks/s) 10host_mem_usage 292088 # Number of bytes of host memory used | 7host_inst_rate 85129 # Simulator instruction rate (inst/s) 8host_op_rate 85110 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 388456550 # Simulator tick rate (ticks/s) 10host_mem_usage 291584 # Number of bytes of host memory used |
| 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4986 # Number of instructions simulated 13sim_ops 4986 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30144 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 471 # Number of read requests responded to by this memory | 11host_seconds 0.06 # Real time elapsed on the host 12sim_insts 4986 # Number of instructions simulated 13sim_ops 4986 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21120 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30144 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21120 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21120 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 330 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 471 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 997944574 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 426394500 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1424339074 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 997944574 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 997944574 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 997944574 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 426394500 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1424339074 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 927862227 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 396450224 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1324312451 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 927862227 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 927862227 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 927862227 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 396450224 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1324312451 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 471 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 471 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 471 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30144 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30144 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 21083000 # Total gap between requests | 78system.physmem.totGap 22674500 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 471 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 471 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) 93system.physmem.rdQLenPdf::0 277 # What read queue length does an incoming req see |
| 94system.physmem.rdQLenPdf::1 134 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 39 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see | 94system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::2 38 # What read queue length does an incoming req see 96system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 262.095238 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 179.705030 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 253.763121 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 34 32.38% 60.95% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 17 16.19% 77.14% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 10 9.52% 86.67% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 0.95% 91.43% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 1.90% 93.33% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 2 1.90% 95.24% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 4.76% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation 203system.physmem.totQLat 5392000 # Total ticks spent queuing 204system.physmem.totMemAccLat 14223250 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 181.184943 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 253.583818 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 28 26.92% 26.92% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 35 33.65% 60.58% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 18 17.31% 77.88% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 10 9.62% 87.50% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 2.88% 90.38% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation 203system.physmem.totQLat 5218000 # Total ticks spent queuing 204system.physmem.totMemAccLat 14049250 # Total ticks spent from burst creation until serviced by the DRAM |
| 205system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2355000 # Total ticks spent in databus transfers |
| 206system.physmem.avgQLat 11447.98 # Average queueing delay per DRAM burst | 206system.physmem.avgQLat 11078.56 # Average queueing delay per DRAM burst |
| 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 208system.physmem.avgMemAccLat 30197.98 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1424.34 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 29828.56 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1324.31 # Average DRAM read bandwidth in MiByte/s |
| 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 211system.physmem.avgRdBWSys 1424.34 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1324.31 # Average system read bandwidth in MiByte/s |
| 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 214system.physmem.busUtil 11.13 # Data bus utilization in percentage 215system.physmem.busUtilRead 11.13 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 10.35 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.35 # Data bus utilization in percentage for reads |
| 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes |
| 217system.physmem.avgRdQLen 1.75 # Average read queue length when enqueuing | 217system.physmem.avgRdQLen 1.74 # Average read queue length when enqueuing |
| 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 356 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 356 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 75.58 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 223system.physmem.avgGap 44762.21 # Average gap between requests | 223system.physmem.avgGap 48141.19 # Average gap between requests |
| 224system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined | 224system.physmem.pageHitRate 75.58 # Row buffer hit rate, read and write combined |
| 225system.physmem_0.actEnergy 136080 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 74250 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 569400 # Energy for read commands per rank (pJ) | 225system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ) 226system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ) 227system.physmem_0.readEnergy 491400 # Energy for read commands per rank (pJ) |
| 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ) 229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 230system.physmem_0.actBackEnergy 9948780 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 772500 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 12518130 # Total energy per rank (pJ) 233system.physmem_0.averagePower 790.660351 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 2505250 # Time in different power states | 230system.physmem_0.actBackEnergy 9465705 # Energy for active background per rank (pJ) 231system.physmem_0.preBackEnergy 1196250 # Energy for precharge background per rank (pJ) 232system.physmem_0.totalEnergy 12369120 # Total energy per rank (pJ) 233system.physmem_0.averagePower 781.248697 # Core power per rank (mW) 234system.physmem_0.memoryStateTime::IDLE 1950500 # Time in different power states |
| 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states | 235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states 236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 237system.physmem_0.memoryStateTime::ACT 14081250 # Time in different power states | 237system.physmem_0.memoryStateTime::ACT 13375750 # Time in different power states |
| 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states | 238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 239system.physmem_1.actEnergy 536760 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 292875 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 2285400 # Energy for read commands per rank (pJ) | 239system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ) 240system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ) 241system.physmem_1.readEnergy 2184000 # Energy for read commands per rank (pJ) |
| 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) | 242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ) 243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ) |
| 244system.physmem_1.actBackEnergy 10734525 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 83250 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 14949930 # Total energy per rank (pJ) 247system.physmem_1.averagePower 944.255803 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 97000 # Time in different power states | 244system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ) 245system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ) 246system.physmem_1.totalEnergy 14812845 # Total energy per rank (pJ) 247system.physmem_1.averagePower 935.597347 # Core power per rank (mW) 248system.physmem_1.memoryStateTime::IDLE 284750 # Time in different power states |
| 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states | 249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states 250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states |
| 251system.physmem_1.memoryStateTime::ACT 15229250 # Time in different power states | 251system.physmem_1.memoryStateTime::ACT 15222250 # Time in different power states |
| 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states | 252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 253system.cpu.branchPred.lookups 2146 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1406 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 427 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1636 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 528 # Number of BTB hits | 253system.cpu.branchPred.lookups 2110 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1371 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 423 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1629 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 525 # Number of BTB hits |
| 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. | 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. |
| 259system.cpu.branchPred.BTBHitPct 32.273839 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 284 # Number of times the RAS was used to get a target. | 259system.cpu.branchPred.BTBHitPct 32.228361 # BTB Hit Percentage 260system.cpu.branchPred.usedRAS 280 # Number of times the RAS was used to get a target. |
| 261system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses 268system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 7 # Number of system calls | 261system.cpu.branchPred.RASInCorrect 68 # Number of incorrect RAS predictions. 262system.cpu_clk_domain.clock 500 # Clock period in ticks 263system.cpu.dtb.read_hits 0 # DTB read hits 264system.cpu.dtb.read_misses 0 # DTB read misses 265system.cpu.dtb.read_accesses 0 # DTB read accesses 266system.cpu.dtb.write_hits 0 # DTB write hits 267system.cpu.dtb.write_misses 0 # DTB write misses 268system.cpu.dtb.write_accesses 0 # DTB write accesses --- 5 unchanged lines hidden (view full) --- 274system.cpu.itb.read_accesses 0 # DTB read accesses 275system.cpu.itb.write_hits 0 # DTB write hits 276system.cpu.itb.write_misses 0 # DTB write misses 277system.cpu.itb.write_accesses 0 # DTB write accesses 278system.cpu.itb.hits 0 # DTB hits 279system.cpu.itb.misses 0 # DTB misses 280system.cpu.itb.accesses 0 # DTB accesses 281system.cpu.workload.num_syscalls 7 # Number of system calls |
| 282system.cpu.numCycles 42328 # number of cpu cycles simulated | 282system.cpu.numCycles 45525 # number of cpu cycles simulated |
| 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed | 283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed |
| 285system.cpu.fetch.icacheStallCycles 8967 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 13064 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2146 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 812 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 4771 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 872 # Number of cycles fetch has spent squashing 291system.cpu.fetch.PendingTrapStallCycles 202 # Number of stall cycles due to pending traps 292system.cpu.fetch.CacheLines 2037 # Number of cache lines fetched 293system.cpu.fetch.IcacheSquashes 262 # Number of outstanding Icache misses that were squashed 294system.cpu.fetch.rateDist::samples 14376 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::mean 0.908737 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::stdev 2.207470 # Number of instructions fetched each cycle (Total) | 285system.cpu.fetch.icacheStallCycles 8934 # Number of cycles fetch is stalled on an Icache miss 286system.cpu.fetch.Insts 12895 # Number of instructions fetch has processed 287system.cpu.fetch.Branches 2110 # Number of branches that fetch encountered 288system.cpu.fetch.predictedBranches 805 # Number of branches that fetch has predicted taken 289system.cpu.fetch.Cycles 4920 # Number of cycles fetch has run and was not squashing or blocked 290system.cpu.fetch.SquashCycles 864 # Number of cycles fetch has spent squashing 291system.cpu.fetch.PendingTrapStallCycles 192 # Number of stall cycles due to pending traps 292system.cpu.fetch.CacheLines 2026 # Number of cache lines fetched 293system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed 294system.cpu.fetch.rateDist::samples 14478 # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::mean 0.890662 # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::stdev 2.186824 # Number of instructions fetched each cycle (Total) |
| 297system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 297system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 298system.cpu.fetch.rateDist::0 11035 76.76% 76.76% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::1 1473 10.25% 87.01% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::2 126 0.88% 87.88% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::3 160 1.11% 89.00% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::4 283 1.97% 90.96% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::5 90 0.63% 91.59% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::6 137 0.95% 92.54% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::7 121 0.84% 93.38% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::8 951 6.62% 100.00% # Number of instructions fetched each cycle (Total) | 298system.cpu.fetch.rateDist::0 11164 77.11% 77.11% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::1 1470 10.15% 87.26% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::2 124 0.86% 88.12% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::3 160 1.11% 89.23% # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::4 283 1.95% 91.18% # Number of instructions fetched each cycle (Total) 303system.cpu.fetch.rateDist::5 94 0.65% 91.83% # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.rateDist::6 128 0.88% 92.71% # Number of instructions fetched each cycle (Total) 305system.cpu.fetch.rateDist::7 113 0.78% 93.49% # Number of instructions fetched each cycle (Total) 306system.cpu.fetch.rateDist::8 942 6.51% 100.00% # Number of instructions fetched each cycle (Total) |
| 307system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 307system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 308system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 309system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 310system.cpu.fetch.rateDist::total 14376 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.branchRate 0.050699 # Number of branch fetches per cycle 312system.cpu.fetch.rate 0.308637 # Number of inst fetches per cycle 313system.cpu.decode.IdleCycles 8549 # Number of cycles decode is idle 314system.cpu.decode.BlockedCycles 2515 # Number of cycles decode is blocked 315system.cpu.decode.RunCycles 2791 # Number of cycles decode is running 316system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking 317system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing | 310system.cpu.fetch.rateDist::total 14478 # Number of instructions fetched each cycle (Total) 311system.cpu.fetch.branchRate 0.046348 # Number of branch fetches per cycle 312system.cpu.fetch.rate 0.283251 # Number of inst fetches per cycle 313system.cpu.decode.IdleCycles 8487 # Number of cycles decode is idle 314system.cpu.decode.BlockedCycles 2706 # Number of cycles decode is blocked 315system.cpu.decode.RunCycles 2773 # Number of cycles decode is running 316system.cpu.decode.UnblockCycles 121 # Number of cycles decode is unblocking 317system.cpu.decode.SquashCycles 391 # Number of cycles decode is squashing |
| 318system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch 319system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction | 318system.cpu.decode.BranchResolved 174 # Number of times decode resolved a branch 319system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction |
| 320system.cpu.decode.DecodedInsts 12032 # Number of instructions handled by decode | 320system.cpu.decode.DecodedInsts 11880 # Number of instructions handled by decode |
| 321system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode | 321system.cpu.decode.SquashedInsts 172 # Number of squashed instructions handled by decode |
| 322system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 8711 # Number of cycles rename is idle | 322system.cpu.rename.SquashCycles 391 # Number of cycles rename is squashing 323system.cpu.rename.IdleCycles 8645 # Number of cycles rename is idle |
| 324system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking | 324system.cpu.rename.BlockCycles 502 # Number of cycles rename is blocking |
| 325system.cpu.rename.serializeStallCycles 944 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 2743 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 1081 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 11544 # Number of instructions processed by rename | 325system.cpu.rename.serializeStallCycles 1002 # count of cycles rename stalled for serializing inst 326system.cpu.rename.RunCycles 2724 # Number of cycles rename is running 327system.cpu.rename.UnblockCycles 1214 # Number of cycles rename is unblocking 328system.cpu.rename.RenamedInsts 11398 # Number of instructions processed by rename |
| 329system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 330system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full | 329system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full 330system.cpu.rename.IQFullEvents 2 # Number of times rename has blocked due to IQ full |
| 331system.cpu.rename.LQFullEvents 196 # Number of times rename has blocked due to LQ full 332system.cpu.rename.SQFullEvents 868 # Number of times rename has blocked due to SQ full 333system.cpu.rename.RenamedOperands 6963 # Number of destination operands rename has renamed 334system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made 335system.cpu.rename.int_rename_lookups 13345 # Number of integer rename lookups | 331system.cpu.rename.LQFullEvents 231 # Number of times rename has blocked due to LQ full 332system.cpu.rename.SQFullEvents 967 # Number of times rename has blocked due to SQ full 333system.cpu.rename.RenamedOperands 6879 # Number of destination operands rename has renamed 334system.cpu.rename.RenameLookups 13412 # Number of register rename lookups that rename has made 335system.cpu.rename.int_rename_lookups 13162 # Number of integer rename lookups |
| 336system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 337system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed | 336system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 337system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed |
| 338system.cpu.rename.UndoneMaps 3681 # Number of HB maps that are undone due to squashing | 338system.cpu.rename.UndoneMaps 3597 # Number of HB maps that are undone due to squashing |
| 339system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 340system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed | 339system.cpu.rename.serializingInsts 13 # count of serializing insts renamed 340system.cpu.rename.tempSerializingInsts 9 # count of temporary serializing insts renamed |
| 341system.cpu.rename.skidInsts 298 # count of insts added to the skid buffer 342system.cpu.memDep0.insertedLoads 2503 # Number of loads inserted to the mem dependence unit. 343system.cpu.memDep0.insertedStores 1169 # Number of stores inserted to the mem dependence unit. | 341system.cpu.rename.skidInsts 290 # count of insts added to the skid buffer 342system.cpu.memDep0.insertedLoads 2474 # Number of loads inserted to the mem dependence unit. 343system.cpu.memDep0.insertedStores 1168 # Number of stores inserted to the mem dependence unit. |
| 344system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 345system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. | 344system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 345system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores. |
| 346system.cpu.iq.iqInstsAdded 9029 # Number of instructions added to the IQ (excludes non-spec) | 346system.cpu.iq.iqInstsAdded 8940 # Number of instructions added to the IQ (excludes non-spec) |
| 347system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ | 347system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ |
| 348system.cpu.iq.iqInstsIssued 8280 # Number of instructions issued 349system.cpu.iq.iqSquashedInstsIssued 31 # Number of squashed instructions issued 350system.cpu.iq.iqSquashedInstsExamined 3419 # Number of squashed instructions iterated over during squash; mainly for profiling 351system.cpu.iq.iqSquashedOperandsExamined 1838 # Number of squashed operands that are examined and possibly removed from graph | 348system.cpu.iq.iqInstsIssued 8204 # Number of instructions issued 349system.cpu.iq.iqSquashedInstsIssued 35 # Number of squashed instructions issued 350system.cpu.iq.iqSquashedInstsExamined 3309 # Number of squashed instructions iterated over during squash; mainly for profiling 351system.cpu.iq.iqSquashedOperandsExamined 1790 # Number of squashed operands that are examined and possibly removed from graph |
| 352system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed | 352system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| 353system.cpu.iq.issued_per_cycle::samples 14376 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::mean 0.575960 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::stdev 1.325471 # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::samples 14478 # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::mean 0.566653 # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::stdev 1.310295 # Number of insts issued each cycle |
| 356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 357system.cpu.iq.issued_per_cycle::0 11054 76.89% 76.89% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::1 1314 9.14% 86.03% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::2 739 5.14% 91.17% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::3 413 2.87% 94.05% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::4 345 2.40% 96.45% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::5 315 2.19% 98.64% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::6 104 0.72% 99.36% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::7 66 0.46% 99.82% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::8 26 0.18% 100.00% # Number of insts issued each cycle | 357system.cpu.iq.issued_per_cycle::0 11167 77.13% 77.13% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::1 1314 9.08% 86.21% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::2 734 5.07% 91.28% # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::3 423 2.92% 94.20% # Number of insts issued each cycle 361system.cpu.iq.issued_per_cycle::4 344 2.38% 96.57% # Number of insts issued each cycle 362system.cpu.iq.issued_per_cycle::5 310 2.14% 98.72% # Number of insts issued each cycle 363system.cpu.iq.issued_per_cycle::6 102 0.70% 99.42% # Number of insts issued each cycle 364system.cpu.iq.issued_per_cycle::7 57 0.39% 99.81% # Number of insts issued each cycle 365system.cpu.iq.issued_per_cycle::8 27 0.19% 100.00% # Number of insts issued each cycle |
| 366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 369system.cpu.iq.issued_per_cycle::total 14376 # Number of insts issued each cycle | 369system.cpu.iq.issued_per_cycle::total 14478 # Number of insts issued each cycle |
| 370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available | 370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available |
| 371system.cpu.iq.fu_full::IntAlu 8 4.06% 4.06% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntMult 0 0.00% 4.06% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntDiv 0 0.00% 4.06% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.06% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.06% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.06% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatMult 0 0.00% 4.06% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.06% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.06% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.06% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.06% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.06% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.06% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.06% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMult 0 0.00% 4.06% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.06% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShift 0 0.00% 4.06% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.06% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.06% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.06% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.06% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.06% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.06% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.06% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.06% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.06% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.06% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.06% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemRead 131 66.50% 70.56% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemWrite 58 29.44% 100.00% # attempts to use FU when none available | 371system.cpu.iq.fu_full::IntAlu 9 4.59% 4.59% # attempts to use FU when none available 372system.cpu.iq.fu_full::IntMult 0 0.00% 4.59% # attempts to use FU when none available 373system.cpu.iq.fu_full::IntDiv 0 0.00% 4.59% # attempts to use FU when none available 374system.cpu.iq.fu_full::FloatAdd 0 0.00% 4.59% # attempts to use FU when none available 375system.cpu.iq.fu_full::FloatCmp 0 0.00% 4.59% # attempts to use FU when none available 376system.cpu.iq.fu_full::FloatCvt 0 0.00% 4.59% # attempts to use FU when none available 377system.cpu.iq.fu_full::FloatMult 0 0.00% 4.59% # attempts to use FU when none available 378system.cpu.iq.fu_full::FloatDiv 0 0.00% 4.59% # attempts to use FU when none available 379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 380system.cpu.iq.fu_full::SimdAdd 0 0.00% 4.59% # attempts to use FU when none available 381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 4.59% # attempts to use FU when none available 382system.cpu.iq.fu_full::SimdAlu 0 0.00% 4.59% # attempts to use FU when none available 383system.cpu.iq.fu_full::SimdCmp 0 0.00% 4.59% # attempts to use FU when none available 384system.cpu.iq.fu_full::SimdCvt 0 0.00% 4.59% # attempts to use FU when none available 385system.cpu.iq.fu_full::SimdMisc 0 0.00% 4.59% # attempts to use FU when none available 386system.cpu.iq.fu_full::SimdMult 0 0.00% 4.59% # attempts to use FU when none available 387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 4.59% # attempts to use FU when none available 388system.cpu.iq.fu_full::SimdShift 0 0.00% 4.59% # attempts to use FU when none available 389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 4.59% # attempts to use FU when none available 390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 4.59% # attempts to use FU when none available 391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 4.59% # attempts to use FU when none available 392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 4.59% # attempts to use FU when none available 393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 4.59% # attempts to use FU when none available 394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 4.59% # attempts to use FU when none available 395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 4.59% # attempts to use FU when none available 396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 4.59% # attempts to use FU when none available 397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 4.59% # attempts to use FU when none available 398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 4.59% # attempts to use FU when none available 399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 4.59% # attempts to use FU when none available 400system.cpu.iq.fu_full::MemRead 129 65.82% 70.41% # attempts to use FU when none available 401system.cpu.iq.fu_full::MemWrite 58 29.59% 100.00% # attempts to use FU when none available |
| 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued | 402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available 403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available 404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued |
| 405system.cpu.iq.FU_type_0::IntAlu 4865 58.76% 58.76% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.80% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.82% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.84% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.84% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.84% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.84% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.84% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.84% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.84% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.84% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.84% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.84% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.84% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.84% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.84% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.84% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.84% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.84% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.84% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.84% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.84% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.84% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.84% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.84% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.84% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.84% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.84% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.84% # Type of FU issued 434system.cpu.iq.FU_type_0::MemRead 2336 28.21% 87.05% # Type of FU issued 435system.cpu.iq.FU_type_0::MemWrite 1072 12.95% 100.00% # Type of FU issued | 405system.cpu.iq.FU_type_0::IntAlu 4822 58.78% 58.78% # Type of FU issued 406system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.82% # Type of FU issued 407system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.84% # Type of FU issued 408system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.86% # Type of FU issued 409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.86% # Type of FU issued 410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.86% # Type of FU issued 411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.86% # Type of FU issued 412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.86% # Type of FU issued 413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.86% # Type of FU issued 414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.86% # Type of FU issued 415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.86% # Type of FU issued 416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.86% # Type of FU issued 417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.86% # Type of FU issued 418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.86% # Type of FU issued 419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.86% # Type of FU issued 420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.86% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.86% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.86% # Type of FU issued 423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.86% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.86% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.86% # Type of FU issued 426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.86% # Type of FU issued 427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.86% # Type of FU issued 428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.86% # Type of FU issued 429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.86% # Type of FU issued 430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.86% # Type of FU issued 431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.86% # Type of FU issued 432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.86% # Type of FU issued 433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.86% # Type of FU issued 434system.cpu.iq.FU_type_0::MemRead 2303 28.07% 86.93% # Type of FU issued 435system.cpu.iq.FU_type_0::MemWrite 1072 13.07% 100.00% # Type of FU issued |
| 436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued | 436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued |
| 438system.cpu.iq.FU_type_0::total 8280 # Type of FU issued 439system.cpu.iq.rate 0.195615 # Inst issue rate 440system.cpu.iq.fu_busy_cnt 197 # FU busy when requested 441system.cpu.iq.fu_busy_rate 0.023792 # FU busy rate (busy events/executed inst) 442system.cpu.iq.int_inst_queue_reads 31160 # Number of integer instruction queue reads 443system.cpu.iq.int_inst_queue_writes 12466 # Number of integer instruction queue writes 444system.cpu.iq.int_inst_queue_wakeup_accesses 7466 # Number of integer instruction queue wakeup accesses | 438system.cpu.iq.FU_type_0::total 8204 # Type of FU issued 439system.cpu.iq.rate 0.180209 # Inst issue rate 440system.cpu.iq.fu_busy_cnt 196 # FU busy when requested 441system.cpu.iq.fu_busy_rate 0.023891 # FU busy rate (busy events/executed inst) 442system.cpu.iq.int_inst_queue_reads 31113 # Number of integer instruction queue reads 443system.cpu.iq.int_inst_queue_writes 12267 # Number of integer instruction queue writes 444system.cpu.iq.int_inst_queue_wakeup_accesses 7408 # Number of integer instruction queue wakeup accesses |
| 445system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 446system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 447system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses | 445system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 446system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 447system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses |
| 448system.cpu.iq.int_alu_accesses 8475 # Number of integer alu accesses | 448system.cpu.iq.int_alu_accesses 8398 # Number of integer alu accesses |
| 449system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 450system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores 451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address | 449system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 450system.cpu.iew.lsq.thread0.forwLoads 82 # Number of loads that had data forwarded from stores 451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address |
| 452system.cpu.iew.lsq.thread0.squashedLoads 1371 # Number of loads squashed | 452system.cpu.iew.lsq.thread0.squashedLoads 1342 # Number of loads squashed |
| 453system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed 454system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations | 453system.cpu.iew.lsq.thread0.ignoredResponses 7 # Number of memory responses ignored because the instruction is squashed 454system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations |
| 455system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed | 455system.cpu.iew.lsq.thread0.squashedStores 267 # Number of stores squashed |
| 456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 458system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled | 456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address 457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 458system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled |
| 459system.cpu.iew.lsq.thread0.cacheBlocked 25 # Number of times an access to memory failed due to the cache being blocked | 459system.cpu.iew.lsq.thread0.cacheBlocked 23 # Number of times an access to memory failed due to the cache being blocked |
| 460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle | 460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle |
| 461system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing 462system.cpu.iew.iewBlockCycles 475 # Number of cycles IEW is blocking 463system.cpu.iew.iewUnblockCycles 11 # Number of cycles IEW is unblocking 464system.cpu.iew.iewDispatchedInsts 10593 # Number of instructions dispatched to IQ 465system.cpu.iew.iewDispSquashedInsts 153 # Number of squashed instructions skipped by dispatch 466system.cpu.iew.iewDispLoadInsts 2503 # Number of dispatched load instructions 467system.cpu.iew.iewDispStoreInsts 1169 # Number of dispatched store instructions | 461system.cpu.iew.iewSquashCycles 391 # Number of cycles IEW is squashing 462system.cpu.iew.iewBlockCycles 464 # Number of cycles IEW is blocking 463system.cpu.iew.iewUnblockCycles 10 # Number of cycles IEW is unblocking 464system.cpu.iew.iewDispatchedInsts 10483 # Number of instructions dispatched to IQ 465system.cpu.iew.iewDispSquashedInsts 162 # Number of squashed instructions skipped by dispatch 466system.cpu.iew.iewDispLoadInsts 2474 # Number of dispatched load instructions 467system.cpu.iew.iewDispStoreInsts 1168 # Number of dispatched store instructions |
| 468system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 469system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall | 468system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions 469system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall |
| 470system.cpu.iew.iewLSQFullEvents 13 # Number of times the LSQ has become full, causing a stall | 470system.cpu.iew.iewLSQFullEvents 12 # Number of times the LSQ has become full, causing a stall |
| 471system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations | 471system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations |
| 472system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly 473system.cpu.iew.predictedNotTakenIncorrect 354 # Number of branches that were predicted not taken incorrectly 474system.cpu.iew.branchMispredicts 452 # Number of branch mispredicts detected at execute 475system.cpu.iew.iewExecutedInsts 7957 # Number of executed instructions 476system.cpu.iew.iewExecLoadInsts 2194 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 323 # Number of squashed instructions skipped in execute | 472system.cpu.iew.predictedTakenIncorrect 96 # Number of branches that were predicted taken incorrectly 473system.cpu.iew.predictedNotTakenIncorrect 348 # Number of branches that were predicted not taken incorrectly 474system.cpu.iew.branchMispredicts 444 # Number of branch mispredicts detected at execute 475system.cpu.iew.iewExecutedInsts 7875 # Number of executed instructions 476system.cpu.iew.iewExecLoadInsts 2160 # Number of load instructions executed 477system.cpu.iew.iewExecSquashedInsts 329 # Number of squashed instructions skipped in execute |
| 478system.cpu.iew.exec_swp 0 # number of swp insts executed | 478system.cpu.iew.exec_swp 0 # number of swp insts executed |
| 479system.cpu.iew.exec_nop 1553 # number of nop insts executed 480system.cpu.iew.exec_refs 3252 # number of memory reference insts executed 481system.cpu.iew.exec_branches 1379 # Number of branches executed 482system.cpu.iew.exec_stores 1058 # Number of stores executed 483system.cpu.iew.exec_rate 0.187984 # Inst execution rate 484system.cpu.iew.wb_sent 7571 # cumulative count of insts sent to commit 485system.cpu.iew.wb_count 7468 # cumulative count of insts written-back 486system.cpu.iew.wb_producers 2915 # num instructions producing a value 487system.cpu.iew.wb_consumers 4399 # num instructions consuming a value | 479system.cpu.iew.exec_nop 1532 # number of nop insts executed 480system.cpu.iew.exec_refs 3217 # number of memory reference insts executed 481system.cpu.iew.exec_branches 1365 # Number of branches executed 482system.cpu.iew.exec_stores 1057 # Number of stores executed 483system.cpu.iew.exec_rate 0.172982 # Inst execution rate 484system.cpu.iew.wb_sent 7509 # cumulative count of insts sent to commit 485system.cpu.iew.wb_count 7410 # cumulative count of insts written-back 486system.cpu.iew.wb_producers 2869 # num instructions producing a value 487system.cpu.iew.wb_consumers 4254 # num instructions consuming a value |
| 488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 489system.cpu.iew.wb_rate 0.176432 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.662651 # average fanout of values written-back | 489system.cpu.iew.wb_rate 0.162768 # insts written-back per cycle 490system.cpu.iew.wb_fanout 0.674424 # average fanout of values written-back |
| 491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ | 491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ |
| 492system.cpu.commit.commitSquashedInsts 4969 # The number of squashed insts skipped by commit | 492system.cpu.commit.commitSquashedInsts 4860 # The number of squashed insts skipped by commit |
| 493system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards | 493system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards |
| 494system.cpu.commit.branchMispredicts 386 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 13506 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 0.416333 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 1.231872 # Number of insts commited each cycle | 494system.cpu.commit.branchMispredicts 382 # The number of times a branch was mispredicted 495system.cpu.commit.committed_per_cycle::samples 13623 # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::mean 0.412758 # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::stdev 1.228786 # Number of insts commited each cycle |
| 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 499system.cpu.commit.committed_per_cycle::0 11333 83.91% 83.91% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 875 6.48% 90.39% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 515 3.81% 94.20% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 250 1.85% 96.05% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 149 1.10% 97.16% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 177 1.31% 98.47% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 64 0.47% 98.94% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 102 0.76% 100.00% # Number of insts commited each cycle | 499system.cpu.commit.committed_per_cycle::0 11456 84.09% 84.09% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::1 871 6.39% 90.49% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::2 510 3.74% 94.23% # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::3 252 1.85% 96.08% # Number of insts commited each cycle 503system.cpu.commit.committed_per_cycle::4 148 1.09% 97.17% # Number of insts commited each cycle 504system.cpu.commit.committed_per_cycle::5 178 1.31% 98.47% # Number of insts commited each cycle 505system.cpu.commit.committed_per_cycle::6 65 0.48% 98.95% # Number of insts commited each cycle 506system.cpu.commit.committed_per_cycle::7 40 0.29% 99.24% # Number of insts commited each cycle 507system.cpu.commit.committed_per_cycle::8 103 0.76% 100.00% # Number of insts commited each cycle |
| 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 511system.cpu.commit.committed_per_cycle::total 13506 # Number of insts commited each cycle | 511system.cpu.commit.committed_per_cycle::total 13623 # Number of insts commited each cycle |
| 512system.cpu.commit.committedInsts 5623 # Number of instructions committed 513system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 2033 # Number of memory references committed 516system.cpu.commit.loads 1132 # Number of loads committed 517system.cpu.commit.membars 0 # Number of memory barriers committed 518system.cpu.commit.branches 883 # Number of branches committed 519system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction | 512system.cpu.commit.committedInsts 5623 # Number of instructions committed 513system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed 514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 515system.cpu.commit.refs 2033 # Number of memory references committed 516system.cpu.commit.loads 1132 # Number of loads committed 517system.cpu.commit.membars 0 # Number of memory barriers committed 518system.cpu.commit.branches 883 # Number of branches committed 519system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. --- 29 unchanged lines hidden (view full) --- 549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction 550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction 551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction 552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction 553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction 554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction |
| 557system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached | 557system.cpu.commit.bw_lim_events 103 # number cycles where commit BW limit reached |
| 558system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 558system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 559system.cpu.rob.rob_reads 23983 # The number of ROB reads 560system.cpu.rob.rob_writes 22065 # The number of ROB writes 561system.cpu.timesIdled 275 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 27952 # Total number of cycles that the CPU has spent unscheduled due to idling | 559system.cpu.rob.rob_reads 23990 # The number of ROB reads 560system.cpu.rob.rob_writes 21831 # The number of ROB writes 561system.cpu.timesIdled 267 # Number of times that the entire CPU went into an idle state and unscheduled itself 562system.cpu.idleCycles 31047 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 563system.cpu.committedInsts 4986 # Number of Instructions Simulated 564system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated | 563system.cpu.committedInsts 4986 # Number of Instructions Simulated 564system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated |
| 565system.cpu.cpi 8.489370 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 8.489370 # CPI: Total CPI of All Threads 567system.cpu.ipc 0.117794 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 0.117794 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 10767 # number of integer regfile reads 570system.cpu.int_regfile_writes 5247 # number of integer regfile writes | 565system.cpu.cpi 9.130566 # CPI: Cycles Per Instruction 566system.cpu.cpi_total 9.130566 # CPI: Total CPI of All Threads 567system.cpu.ipc 0.109522 # IPC: Instructions Per Cycle 568system.cpu.ipc_total 0.109522 # IPC: Total IPC of All Threads 569system.cpu.int_regfile_reads 10639 # number of integer regfile reads 570system.cpu.int_regfile_writes 5201 # number of integer regfile writes |
| 571system.cpu.fp_regfile_reads 3 # number of floating regfile reads 572system.cpu.fp_regfile_writes 1 # number of floating regfile writes | 571system.cpu.fp_regfile_reads 3 # number of floating regfile reads 572system.cpu.fp_regfile_writes 1 # number of floating regfile writes |
| 573system.cpu.misc_regfile_reads 164 # number of misc regfile reads | 573system.cpu.misc_regfile_reads 165 # number of misc regfile reads |
| 574system.cpu.dcache.tags.replacements 0 # number of replacements | 574system.cpu.dcache.tags.replacements 0 # number of replacements |
| 575system.cpu.dcache.tags.tagsinuse 91.168146 # Cycle average of tags in use 576system.cpu.dcache.tags.total_refs 2445 # Total number of references to valid blocks. | 575system.cpu.dcache.tags.tagsinuse 91.212769 # Cycle average of tags in use 576system.cpu.dcache.tags.total_refs 2418 # Total number of references to valid blocks. |
| 577system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. | 577system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks. |
| 578system.cpu.dcache.tags.avg_refs 17.340426 # Average number of references to valid blocks. | 578system.cpu.dcache.tags.avg_refs 17.148936 # Average number of references to valid blocks. |
| 579system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 579system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 580system.cpu.dcache.tags.occ_blocks::cpu.data 91.168146 # Average occupied blocks per requestor 581system.cpu.dcache.tags.occ_percent::cpu.data 0.022258 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_percent::total 0.022258 # Average percentage of cache occupancy | 580system.cpu.dcache.tags.occ_blocks::cpu.data 91.212769 # Average occupied blocks per requestor 581system.cpu.dcache.tags.occ_percent::cpu.data 0.022269 # Average percentage of cache occupancy 582system.cpu.dcache.tags.occ_percent::total 0.022269 # Average percentage of cache occupancy |
| 583system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id | 583system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id |
| 584system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::1 102 # Occupied blocks per task id | 584system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id 585system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id |
| 586system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id | 586system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id |
| 587system.cpu.dcache.tags.tag_accesses 6061 # Number of tag accesses 588system.cpu.dcache.tags.data_accesses 6061 # Number of data accesses 589system.cpu.dcache.ReadReq_hits::cpu.data 1893 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 1893 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 552 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 552 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 2445 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 2445 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 2445 # number of overall hits 596system.cpu.dcache.overall_hits::total 2445 # number of overall hits 597system.cpu.dcache.ReadReq_misses::cpu.data 166 # number of ReadReq misses 598system.cpu.dcache.ReadReq_misses::total 166 # number of ReadReq misses 599system.cpu.dcache.WriteReq_misses::cpu.data 349 # number of WriteReq misses 600system.cpu.dcache.WriteReq_misses::total 349 # number of WriteReq misses 601system.cpu.dcache.demand_misses::cpu.data 515 # number of demand (read+write) misses 602system.cpu.dcache.demand_misses::total 515 # number of demand (read+write) misses 603system.cpu.dcache.overall_misses::cpu.data 515 # number of overall misses 604system.cpu.dcache.overall_misses::total 515 # number of overall misses 605system.cpu.dcache.ReadReq_miss_latency::cpu.data 11320500 # number of ReadReq miss cycles 606system.cpu.dcache.ReadReq_miss_latency::total 11320500 # number of ReadReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::cpu.data 22383749 # number of WriteReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::total 22383749 # number of WriteReq miss cycles 609system.cpu.dcache.demand_miss_latency::cpu.data 33704249 # number of demand (read+write) miss cycles 610system.cpu.dcache.demand_miss_latency::total 33704249 # number of demand (read+write) miss cycles 611system.cpu.dcache.overall_miss_latency::cpu.data 33704249 # number of overall miss cycles 612system.cpu.dcache.overall_miss_latency::total 33704249 # number of overall miss cycles 613system.cpu.dcache.ReadReq_accesses::cpu.data 2059 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.ReadReq_accesses::total 2059 # number of ReadReq accesses(hits+misses) | 587system.cpu.dcache.tags.tag_accesses 5997 # Number of tag accesses 588system.cpu.dcache.tags.data_accesses 5997 # Number of data accesses 589system.cpu.dcache.ReadReq_hits::cpu.data 1862 # number of ReadReq hits 590system.cpu.dcache.ReadReq_hits::total 1862 # number of ReadReq hits 591system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits 592system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits 593system.cpu.dcache.demand_hits::cpu.data 2418 # number of demand (read+write) hits 594system.cpu.dcache.demand_hits::total 2418 # number of demand (read+write) hits 595system.cpu.dcache.overall_hits::cpu.data 2418 # number of overall hits 596system.cpu.dcache.overall_hits::total 2418 # number of overall hits 597system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses 598system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses 599system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses 600system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses 601system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 602system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 603system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 604system.cpu.dcache.overall_misses::total 510 # number of overall misses 605system.cpu.dcache.ReadReq_miss_latency::cpu.data 12038750 # number of ReadReq miss cycles 606system.cpu.dcache.ReadReq_miss_latency::total 12038750 # number of ReadReq miss cycles 607system.cpu.dcache.WriteReq_miss_latency::cpu.data 24387249 # number of WriteReq miss cycles 608system.cpu.dcache.WriteReq_miss_latency::total 24387249 # number of WriteReq miss cycles 609system.cpu.dcache.demand_miss_latency::cpu.data 36425999 # number of demand (read+write) miss cycles 610system.cpu.dcache.demand_miss_latency::total 36425999 # number of demand (read+write) miss cycles 611system.cpu.dcache.overall_miss_latency::cpu.data 36425999 # number of overall miss cycles 612system.cpu.dcache.overall_miss_latency::total 36425999 # number of overall miss cycles 613system.cpu.dcache.ReadReq_accesses::cpu.data 2027 # number of ReadReq accesses(hits+misses) 614system.cpu.dcache.ReadReq_accesses::total 2027 # number of ReadReq accesses(hits+misses) |
| 615system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) | 615system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses) 616system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses) |
| 617system.cpu.dcache.demand_accesses::cpu.data 2960 # number of demand (read+write) accesses 618system.cpu.dcache.demand_accesses::total 2960 # number of demand (read+write) accesses 619system.cpu.dcache.overall_accesses::cpu.data 2960 # number of overall (read+write) accesses 620system.cpu.dcache.overall_accesses::total 2960 # number of overall (read+write) accesses 621system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.080622 # miss rate for ReadReq accesses 622system.cpu.dcache.ReadReq_miss_rate::total 0.080622 # miss rate for ReadReq accesses 623system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.387347 # miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_miss_rate::total 0.387347 # miss rate for WriteReq accesses 625system.cpu.dcache.demand_miss_rate::cpu.data 0.173986 # miss rate for demand accesses 626system.cpu.dcache.demand_miss_rate::total 0.173986 # miss rate for demand accesses 627system.cpu.dcache.overall_miss_rate::cpu.data 0.173986 # miss rate for overall accesses 628system.cpu.dcache.overall_miss_rate::total 0.173986 # miss rate for overall accesses 629system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68195.783133 # average ReadReq miss latency 630system.cpu.dcache.ReadReq_avg_miss_latency::total 68195.783133 # average ReadReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64136.816619 # average WriteReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::total 64136.816619 # average WriteReq miss latency 633system.cpu.dcache.demand_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 634system.cpu.dcache.demand_avg_miss_latency::total 65445.143689 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 65445.143689 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 65445.143689 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked | 617system.cpu.dcache.demand_accesses::cpu.data 2928 # number of demand (read+write) accesses 618system.cpu.dcache.demand_accesses::total 2928 # number of demand (read+write) accesses 619system.cpu.dcache.overall_accesses::cpu.data 2928 # number of overall (read+write) accesses 620system.cpu.dcache.overall_accesses::total 2928 # number of overall (read+write) accesses 621system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.081401 # miss rate for ReadReq accesses 622system.cpu.dcache.ReadReq_miss_rate::total 0.081401 # miss rate for ReadReq accesses 623system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses 624system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses 625system.cpu.dcache.demand_miss_rate::cpu.data 0.174180 # miss rate for demand accesses 626system.cpu.dcache.demand_miss_rate::total 0.174180 # miss rate for demand accesses 627system.cpu.dcache.overall_miss_rate::cpu.data 0.174180 # miss rate for overall accesses 628system.cpu.dcache.overall_miss_rate::total 0.174180 # miss rate for overall accesses 629system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 72962.121212 # average ReadReq miss latency 630system.cpu.dcache.ReadReq_avg_miss_latency::total 72962.121212 # average ReadReq miss latency 631system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70687.678261 # average WriteReq miss latency 632system.cpu.dcache.WriteReq_avg_miss_latency::total 70687.678261 # average WriteReq miss latency 633system.cpu.dcache.demand_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency 634system.cpu.dcache.demand_avg_miss_latency::total 71423.527451 # average overall miss latency 635system.cpu.dcache.overall_avg_miss_latency::cpu.data 71423.527451 # average overall miss latency 636system.cpu.dcache.overall_avg_miss_latency::total 71423.527451 # average overall miss latency 637system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked |
| 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 638system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 640system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked | 641system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked |
| 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.dcache.fast_writes 0 # number of fast writes performed 644system.cpu.dcache.cache_copies 0 # number of cache copies performed | 642system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.dcache.fast_writes 0 # number of fast writes performed 644system.cpu.dcache.cache_copies 0 # number of cache copies performed |
| 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 75 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 75 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 299 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 299 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 374 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 374 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 374 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 374 # number of overall MSHR hits | 645system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits 646system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits 647system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits 648system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits 649system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits 650system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits 651system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits 652system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits |
| 653system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 654system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 656system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 657system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 658system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 659system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 660system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses | 653system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 654system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 655system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses 656system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses 657system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 658system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses 659system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 660system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses |
| 661system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7311000 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_latency::total 7311000 # number of ReadReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4032499 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteReq_mshr_miss_latency::total 4032499 # number of WriteReq MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11343499 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.demand_mshr_miss_latency::total 11343499 # number of demand (read+write) MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11343499 # number of overall MSHR miss cycles 668system.cpu.dcache.overall_mshr_miss_latency::total 11343499 # number of overall MSHR miss cycles 669system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044196 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044196 # mshr miss rate for ReadReq accesses | 661system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7833500 # number of ReadReq MSHR miss cycles 662system.cpu.dcache.ReadReq_mshr_miss_latency::total 7833500 # number of ReadReq MSHR miss cycles 663system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4084749 # number of WriteReq MSHR miss cycles 664system.cpu.dcache.WriteReq_mshr_miss_latency::total 4084749 # number of WriteReq MSHR miss cycles 665system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11918249 # number of demand (read+write) MSHR miss cycles 666system.cpu.dcache.demand_mshr_miss_latency::total 11918249 # number of demand (read+write) MSHR miss cycles 667system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11918249 # number of overall MSHR miss cycles 668system.cpu.dcache.overall_mshr_miss_latency::total 11918249 # number of overall MSHR miss cycles 669system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044894 # mshr miss rate for ReadReq accesses 670system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044894 # mshr miss rate for ReadReq accesses |
| 671system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses | 671system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses 672system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses |
| 673system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for demand accesses 674system.cpu.dcache.demand_mshr_miss_rate::total 0.047635 # mshr miss rate for demand accesses 675system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.047635 # mshr miss rate for overall accesses 676system.cpu.dcache.overall_mshr_miss_rate::total 0.047635 # mshr miss rate for overall accesses 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 80340.659341 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 80340.659341 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80649.980000 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80649.980000 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80450.347518 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 80450.347518 # average overall mshr miss latency | 673system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for demand accesses 674system.cpu.dcache.demand_mshr_miss_rate::total 0.048156 # mshr miss rate for demand accesses 675system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048156 # mshr miss rate for overall accesses 676system.cpu.dcache.overall_mshr_miss_rate::total 0.048156 # mshr miss rate for overall accesses 677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 86082.417582 # average ReadReq mshr miss latency 678system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 86082.417582 # average ReadReq mshr miss latency 679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81694.980000 # average WriteReq mshr miss latency 680system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81694.980000 # average WriteReq mshr miss latency 681system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency 682system.cpu.dcache.demand_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency 683system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 84526.588652 # average overall mshr miss latency 684system.cpu.dcache.overall_avg_mshr_miss_latency::total 84526.588652 # average overall mshr miss latency |
| 685system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 686system.cpu.icache.tags.replacements 17 # number of replacements | 685system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 686system.cpu.icache.tags.replacements 17 # number of replacements |
| 687system.cpu.icache.tags.tagsinuse 158.344728 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 1593 # Total number of references to valid blocks. | 687system.cpu.icache.tags.tagsinuse 158.205778 # Cycle average of tags in use 688system.cpu.icache.tags.total_refs 1577 # Total number of references to valid blocks. |
| 689system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. | 689system.cpu.icache.tags.sampled_refs 333 # Sample count of references to valid blocks. |
| 690system.cpu.icache.tags.avg_refs 4.783784 # Average number of references to valid blocks. | 690system.cpu.icache.tags.avg_refs 4.735736 # Average number of references to valid blocks. |
| 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 691system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 692system.cpu.icache.tags.occ_blocks::cpu.inst 158.344728 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.077317 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.077317 # Average percentage of cache occupancy | 692system.cpu.icache.tags.occ_blocks::cpu.inst 158.205778 # Average occupied blocks per requestor 693system.cpu.icache.tags.occ_percent::cpu.inst 0.077249 # Average percentage of cache occupancy 694system.cpu.icache.tags.occ_percent::total 0.077249 # Average percentage of cache occupancy |
| 695system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id | 695system.cpu.icache.tags.occ_task_id_blocks::1024 316 # Occupied blocks per task id |
| 696system.cpu.icache.tags.age_task_id_blocks_1024::0 151 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 165 # Occupied blocks per task id | 696system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id 697system.cpu.icache.tags.age_task_id_blocks_1024::1 173 # Occupied blocks per task id |
| 698system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id | 698system.cpu.icache.tags.occ_task_id_percent::1024 0.154297 # Percentage of cache occupancy per task id |
| 699system.cpu.icache.tags.tag_accesses 4407 # Number of tag accesses 700system.cpu.icache.tags.data_accesses 4407 # Number of data accesses 701system.cpu.icache.ReadReq_hits::cpu.inst 1593 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 1593 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 1593 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 1593 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 1593 # number of overall hits 706system.cpu.icache.overall_hits::total 1593 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 444 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 444 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 444 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 444 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 444 # number of overall misses 712system.cpu.icache.overall_misses::total 444 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 30764750 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 30764750 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 30764750 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 30764750 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 30764750 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 30764750 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 2037 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 2037 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 2037 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 2037 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 2037 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 2037 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.217968 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.217968 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.217968 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.217968 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.217968 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.217968 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69289.977477 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 69289.977477 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 69289.977477 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 69289.977477 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 69289.977477 # average overall miss latency | 699system.cpu.icache.tags.tag_accesses 4385 # Number of tag accesses 700system.cpu.icache.tags.data_accesses 4385 # Number of data accesses 701system.cpu.icache.ReadReq_hits::cpu.inst 1577 # number of ReadReq hits 702system.cpu.icache.ReadReq_hits::total 1577 # number of ReadReq hits 703system.cpu.icache.demand_hits::cpu.inst 1577 # number of demand (read+write) hits 704system.cpu.icache.demand_hits::total 1577 # number of demand (read+write) hits 705system.cpu.icache.overall_hits::cpu.inst 1577 # number of overall hits 706system.cpu.icache.overall_hits::total 1577 # number of overall hits 707system.cpu.icache.ReadReq_misses::cpu.inst 449 # number of ReadReq misses 708system.cpu.icache.ReadReq_misses::total 449 # number of ReadReq misses 709system.cpu.icache.demand_misses::cpu.inst 449 # number of demand (read+write) misses 710system.cpu.icache.demand_misses::total 449 # number of demand (read+write) misses 711system.cpu.icache.overall_misses::cpu.inst 449 # number of overall misses 712system.cpu.icache.overall_misses::total 449 # number of overall misses 713system.cpu.icache.ReadReq_miss_latency::cpu.inst 34003000 # number of ReadReq miss cycles 714system.cpu.icache.ReadReq_miss_latency::total 34003000 # number of ReadReq miss cycles 715system.cpu.icache.demand_miss_latency::cpu.inst 34003000 # number of demand (read+write) miss cycles 716system.cpu.icache.demand_miss_latency::total 34003000 # number of demand (read+write) miss cycles 717system.cpu.icache.overall_miss_latency::cpu.inst 34003000 # number of overall miss cycles 718system.cpu.icache.overall_miss_latency::total 34003000 # number of overall miss cycles 719system.cpu.icache.ReadReq_accesses::cpu.inst 2026 # number of ReadReq accesses(hits+misses) 720system.cpu.icache.ReadReq_accesses::total 2026 # number of ReadReq accesses(hits+misses) 721system.cpu.icache.demand_accesses::cpu.inst 2026 # number of demand (read+write) accesses 722system.cpu.icache.demand_accesses::total 2026 # number of demand (read+write) accesses 723system.cpu.icache.overall_accesses::cpu.inst 2026 # number of overall (read+write) accesses 724system.cpu.icache.overall_accesses::total 2026 # number of overall (read+write) accesses 725system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.221619 # miss rate for ReadReq accesses 726system.cpu.icache.ReadReq_miss_rate::total 0.221619 # miss rate for ReadReq accesses 727system.cpu.icache.demand_miss_rate::cpu.inst 0.221619 # miss rate for demand accesses 728system.cpu.icache.demand_miss_rate::total 0.221619 # miss rate for demand accesses 729system.cpu.icache.overall_miss_rate::cpu.inst 0.221619 # miss rate for overall accesses 730system.cpu.icache.overall_miss_rate::total 0.221619 # miss rate for overall accesses 731system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75730.512249 # average ReadReq miss latency 732system.cpu.icache.ReadReq_avg_miss_latency::total 75730.512249 # average ReadReq miss latency 733system.cpu.icache.demand_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency 734system.cpu.icache.demand_avg_miss_latency::total 75730.512249 # average overall miss latency 735system.cpu.icache.overall_avg_miss_latency::cpu.inst 75730.512249 # average overall miss latency 736system.cpu.icache.overall_avg_miss_latency::total 75730.512249 # average overall miss latency |
| 737system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed | 737system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 738system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 739system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked 740system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 741system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 742system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 743system.cpu.icache.fast_writes 0 # number of fast writes performed 744system.cpu.icache.cache_copies 0 # number of cache copies performed |
| 745system.cpu.icache.ReadReq_mshr_hits::cpu.inst 111 # number of ReadReq MSHR hits 746system.cpu.icache.ReadReq_mshr_hits::total 111 # number of ReadReq MSHR hits 747system.cpu.icache.demand_mshr_hits::cpu.inst 111 # number of demand (read+write) MSHR hits 748system.cpu.icache.demand_mshr_hits::total 111 # number of demand (read+write) MSHR hits 749system.cpu.icache.overall_mshr_hits::cpu.inst 111 # number of overall MSHR hits 750system.cpu.icache.overall_mshr_hits::total 111 # number of overall MSHR hits | 745system.cpu.icache.ReadReq_mshr_hits::cpu.inst 116 # number of ReadReq MSHR hits 746system.cpu.icache.ReadReq_mshr_hits::total 116 # number of ReadReq MSHR hits 747system.cpu.icache.demand_mshr_hits::cpu.inst 116 # number of demand (read+write) MSHR hits 748system.cpu.icache.demand_mshr_hits::total 116 # number of demand (read+write) MSHR hits 749system.cpu.icache.overall_mshr_hits::cpu.inst 116 # number of overall MSHR hits 750system.cpu.icache.overall_mshr_hits::total 116 # number of overall MSHR hits |
| 751system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses 752system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses 753system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses 754system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses 755system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses 756system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses | 751system.cpu.icache.ReadReq_mshr_misses::cpu.inst 333 # number of ReadReq MSHR misses 752system.cpu.icache.ReadReq_mshr_misses::total 333 # number of ReadReq MSHR misses 753system.cpu.icache.demand_mshr_misses::cpu.inst 333 # number of demand (read+write) MSHR misses 754system.cpu.icache.demand_mshr_misses::total 333 # number of demand (read+write) MSHR misses 755system.cpu.icache.overall_mshr_misses::cpu.inst 333 # number of overall MSHR misses 756system.cpu.icache.overall_mshr_misses::total 333 # number of overall MSHR misses |
| 757system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24043500 # number of ReadReq MSHR miss cycles 758system.cpu.icache.ReadReq_mshr_miss_latency::total 24043500 # number of ReadReq MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24043500 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.demand_mshr_miss_latency::total 24043500 # number of demand (read+write) MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24043500 # number of overall MSHR miss cycles 762system.cpu.icache.overall_mshr_miss_latency::total 24043500 # number of overall MSHR miss cycles 763system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for ReadReq accesses 764system.cpu.icache.ReadReq_mshr_miss_rate::total 0.163476 # mshr miss rate for ReadReq accesses 765system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for demand accesses 766system.cpu.icache.demand_mshr_miss_rate::total 0.163476 # mshr miss rate for demand accesses 767system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.163476 # mshr miss rate for overall accesses 768system.cpu.icache.overall_mshr_miss_rate::total 0.163476 # mshr miss rate for overall accesses 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72202.702703 # average ReadReq mshr miss latency 770system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72202.702703 # average ReadReq mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 772system.cpu.icache.demand_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72202.702703 # average overall mshr miss latency 774system.cpu.icache.overall_avg_mshr_miss_latency::total 72202.702703 # average overall mshr miss latency | 757system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26389500 # number of ReadReq MSHR miss cycles 758system.cpu.icache.ReadReq_mshr_miss_latency::total 26389500 # number of ReadReq MSHR miss cycles 759system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26389500 # number of demand (read+write) MSHR miss cycles 760system.cpu.icache.demand_mshr_miss_latency::total 26389500 # number of demand (read+write) MSHR miss cycles 761system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26389500 # number of overall MSHR miss cycles 762system.cpu.icache.overall_mshr_miss_latency::total 26389500 # number of overall MSHR miss cycles 763system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for ReadReq accesses 764system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164363 # mshr miss rate for ReadReq accesses 765system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for demand accesses 766system.cpu.icache.demand_mshr_miss_rate::total 0.164363 # mshr miss rate for demand accesses 767system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164363 # mshr miss rate for overall accesses 768system.cpu.icache.overall_mshr_miss_rate::total 0.164363 # mshr miss rate for overall accesses 769system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 79247.747748 # average ReadReq mshr miss latency 770system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 79247.747748 # average ReadReq mshr miss latency 771system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency 772system.cpu.icache.demand_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency 773system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 79247.747748 # average overall mshr miss latency 774system.cpu.icache.overall_avg_mshr_miss_latency::total 79247.747748 # average overall mshr miss latency |
| 775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.cpu.l2cache.tags.replacements 0 # number of replacements | 775system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 776system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 777system.cpu.l2cache.tags.tagsinuse 218.292920 # Cycle average of tags in use | 777system.cpu.l2cache.tags.tagsinuse 218.150435 # Cycle average of tags in use |
| 778system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 778system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 779system.cpu.l2cache.tags.sampled_refs 421 # Sample count of references to valid blocks. 780system.cpu.l2cache.tags.avg_refs 0.007126 # Average number of references to valid blocks. 781system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.335208 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 57.957712 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004893 # Average percentage of cache occupancy | 782system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.168468 # Average occupied blocks per requestor 783system.cpu.l2cache.tags.occ_blocks::cpu.data 57.981967 # Average occupied blocks per requestor 784system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004888 # Average percentage of cache occupancy |
| 785system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy | 785system.cpu.l2cache.tags.occ_percent::cpu.data 0.001769 # Average percentage of cache occupancy |
| 786system.cpu.l2cache.tags.occ_percent::total 0.006662 # Average percentage of cache occupancy | 786system.cpu.l2cache.tags.occ_percent::total 0.006657 # Average percentage of cache occupancy |
| 787system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id | 787system.cpu.l2cache.tags.occ_task_id_blocks::1024 421 # Occupied blocks per task id |
| 788system.cpu.l2cache.tags.age_task_id_blocks_1024::0 192 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::1 229 # Occupied blocks per task id | 788system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id 789system.cpu.l2cache.tags.age_task_id_blocks_1024::1 240 # Occupied blocks per task id |
| 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 795system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 796system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 797system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits --- 4 unchanged lines hidden (view full) --- 802system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 803system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 804system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses 805system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 806system.cpu.l2cache.demand_misses::total 471 # number of demand (read+write) misses 807system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses 808system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 809system.cpu.l2cache.overall_misses::total 471 # number of overall misses | 790system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012848 # Percentage of cache occupancy per task id 791system.cpu.l2cache.tags.tag_accesses 4263 # Number of tag accesses 792system.cpu.l2cache.tags.data_accesses 4263 # Number of data accesses 793system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 794system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 795system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 796system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 797system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits --- 4 unchanged lines hidden (view full) --- 802system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses 803system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses 804system.cpu.l2cache.demand_misses::cpu.inst 330 # number of demand (read+write) misses 805system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses 806system.cpu.l2cache.demand_misses::total 471 # number of demand (read+write) misses 807system.cpu.l2cache.overall_misses::cpu.inst 330 # number of overall misses 808system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses 809system.cpu.l2cache.overall_misses::total 471 # number of overall misses |
| 810system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23680500 # number of ReadReq miss cycles 811system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7216500 # number of ReadReq miss cycles 812system.cpu.l2cache.ReadReq_miss_latency::total 30897000 # number of ReadReq miss cycles 813system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3981500 # number of ReadExReq miss cycles 814system.cpu.l2cache.ReadExReq_miss_latency::total 3981500 # number of ReadExReq miss cycles 815system.cpu.l2cache.demand_miss_latency::cpu.inst 23680500 # number of demand (read+write) miss cycles 816system.cpu.l2cache.demand_miss_latency::cpu.data 11198000 # number of demand (read+write) miss cycles 817system.cpu.l2cache.demand_miss_latency::total 34878500 # number of demand (read+write) miss cycles 818system.cpu.l2cache.overall_miss_latency::cpu.inst 23680500 # number of overall miss cycles 819system.cpu.l2cache.overall_miss_latency::cpu.data 11198000 # number of overall miss cycles 820system.cpu.l2cache.overall_miss_latency::total 34878500 # number of overall miss cycles | 810system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 26025000 # number of ReadReq miss cycles 811system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7738500 # number of ReadReq miss cycles 812system.cpu.l2cache.ReadReq_miss_latency::total 33763500 # number of ReadReq miss cycles 813system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4034000 # number of ReadExReq miss cycles 814system.cpu.l2cache.ReadExReq_miss_latency::total 4034000 # number of ReadExReq miss cycles 815system.cpu.l2cache.demand_miss_latency::cpu.inst 26025000 # number of demand (read+write) miss cycles 816system.cpu.l2cache.demand_miss_latency::cpu.data 11772500 # number of demand (read+write) miss cycles 817system.cpu.l2cache.demand_miss_latency::total 37797500 # number of demand (read+write) miss cycles 818system.cpu.l2cache.overall_miss_latency::cpu.inst 26025000 # number of overall miss cycles 819system.cpu.l2cache.overall_miss_latency::cpu.data 11772500 # number of overall miss cycles 820system.cpu.l2cache.overall_miss_latency::total 37797500 # number of overall miss cycles |
| 821system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) 822system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 823system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 824system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 825system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 826system.cpu.l2cache.demand_accesses::cpu.inst 333 # number of demand (read+write) accesses 827system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 828system.cpu.l2cache.demand_accesses::total 474 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 835system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 836system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 837system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses 838system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 839system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses 840system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses 841system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 842system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses | 821system.cpu.l2cache.ReadReq_accesses::cpu.inst 333 # number of ReadReq accesses(hits+misses) 822system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 823system.cpu.l2cache.ReadReq_accesses::total 424 # number of ReadReq accesses(hits+misses) 824system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses) 825system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses) 826system.cpu.l2cache.demand_accesses::cpu.inst 333 # number of demand (read+write) accesses 827system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses 828system.cpu.l2cache.demand_accesses::total 474 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 835system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 836system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 837system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990991 # miss rate for demand accesses 838system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 839system.cpu.l2cache.demand_miss_rate::total 0.993671 # miss rate for demand accesses 840system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990991 # miss rate for overall accesses 841system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 842system.cpu.l2cache.overall_miss_rate::total 0.993671 # miss rate for overall accesses |
| 843system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71759.090909 # average ReadReq miss latency 844system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 79302.197802 # average ReadReq miss latency 845system.cpu.l2cache.ReadReq_avg_miss_latency::total 73389.548694 # average ReadReq miss latency 846system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79630 # average ReadExReq miss latency 847system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79630 # average ReadExReq miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::total 74052.016985 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71759.090909 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79418.439716 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::total 74052.016985 # average overall miss latency | 843system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 78863.636364 # average ReadReq miss latency 844system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 85038.461538 # average ReadReq miss latency 845system.cpu.l2cache.ReadReq_avg_miss_latency::total 80198.337292 # average ReadReq miss latency 846system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80680 # average ReadExReq miss latency 847system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80680 # average ReadExReq miss latency 848system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency 849system.cpu.l2cache.demand_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency 850system.cpu.l2cache.demand_avg_miss_latency::total 80249.469214 # average overall miss latency 851system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 78863.636364 # average overall miss latency 852system.cpu.l2cache.overall_avg_miss_latency::cpu.data 83492.907801 # average overall miss latency 853system.cpu.l2cache.overall_avg_miss_latency::total 80249.469214 # average overall miss latency |
| 854system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 857system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 858system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 859system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 860system.cpu.l2cache.fast_writes 0 # number of fast writes performed 861system.cpu.l2cache.cache_copies 0 # number of cache copies performed 862system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses 863system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 864system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 867system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 869system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses 870system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses 871system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 872system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses | 854system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 855system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 856system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 857system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 858system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 859system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 860system.cpu.l2cache.fast_writes 0 # number of fast writes performed 861system.cpu.l2cache.cache_copies 0 # number of cache copies performed 862system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 330 # number of ReadReq MSHR misses 863system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 864system.cpu.l2cache.ReadReq_mshr_misses::total 421 # number of ReadReq MSHR misses 865system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses 866system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses 867system.cpu.l2cache.demand_mshr_misses::cpu.inst 330 # number of demand (read+write) MSHR misses 868system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses 869system.cpu.l2cache.demand_mshr_misses::total 471 # number of demand (read+write) MSHR misses 870system.cpu.l2cache.overall_mshr_misses::cpu.inst 330 # number of overall MSHR misses 871system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses 872system.cpu.l2cache.overall_mshr_misses::total 471 # number of overall MSHR misses |
| 873system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19517000 # number of ReadReq MSHR miss cycles 874system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6096000 # number of ReadReq MSHR miss cycles 875system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25613000 # number of ReadReq MSHR miss cycles 876system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3359000 # number of ReadExReq MSHR miss cycles 877system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3359000 # number of ReadExReq MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19517000 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9455000 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::total 28972000 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19517000 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9455000 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::total 28972000 # number of overall MSHR miss cycles | 873system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 21894000 # number of ReadReq MSHR miss cycles 874system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6598000 # number of ReadReq MSHR miss cycles 875system.cpu.l2cache.ReadReq_mshr_miss_latency::total 28492000 # number of ReadReq MSHR miss cycles 876system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3411000 # number of ReadExReq MSHR miss cycles 877system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3411000 # number of ReadExReq MSHR miss cycles 878system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 21894000 # number of demand (read+write) MSHR miss cycles 879system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10009000 # number of demand (read+write) MSHR miss cycles 880system.cpu.l2cache.demand_mshr_miss_latency::total 31903000 # number of demand (read+write) MSHR miss cycles 881system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 21894000 # number of overall MSHR miss cycles 882system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10009000 # number of overall MSHR miss cycles 883system.cpu.l2cache.overall_mshr_miss_latency::total 31903000 # number of overall MSHR miss cycles |
| 884system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses 885system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 886system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses 887system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 888system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 889system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses 890system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 891system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses 892system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses 893system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 894system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses | 884system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for ReadReq accesses 885system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 886system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.992925 # mshr miss rate for ReadReq accesses 887system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 888system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 889system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for demand accesses 890system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 891system.cpu.l2cache.demand_mshr_miss_rate::total 0.993671 # mshr miss rate for demand accesses 892system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990991 # mshr miss rate for overall accesses 893system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 894system.cpu.l2cache.overall_mshr_miss_rate::total 0.993671 # mshr miss rate for overall accesses |
| 895system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59142.424242 # average ReadReq mshr miss latency 896system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 66989.010989 # average ReadReq mshr miss latency 897system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60838.479810 # average ReadReq mshr miss latency 898system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67180 # average ReadExReq mshr miss latency 899system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67180 # average ReadExReq mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 901system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59142.424242 # average overall mshr miss latency 904system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67056.737589 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61511.677282 # average overall mshr miss latency | 895system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 66345.454545 # average ReadReq mshr miss latency 896system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 72505.494505 # average ReadReq mshr miss latency 897system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 67676.959620 # average ReadReq mshr miss latency 898system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 68220 # average ReadExReq mshr miss latency 899system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 68220 # average ReadExReq mshr miss latency 900system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency 901system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency 902system.cpu.l2cache.demand_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency 903system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 66345.454545 # average overall mshr miss latency 904system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 70985.815603 # average overall mshr miss latency 905system.cpu.l2cache.overall_avg_mshr_miss_latency::total 67734.607219 # average overall mshr miss latency |
| 906system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 907system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 911system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) 912system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 913system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 922system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 925system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram 929system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) | 906system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 907system.cpu.toL2Bus.trans_dist::ReadReq 424 # Transaction distribution 908system.cpu.toL2Bus.trans_dist::ReadResp 424 # Transaction distribution 909system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution 910system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution 911system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 666 # Packet count per connected master and slave (bytes) 912system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes) 913system.cpu.toL2Bus.pkt_count::total 948 # Packet count per connected master and slave (bytes) --- 8 unchanged lines hidden (view full) --- 922system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 923system.cpu.toL2Bus.snoop_fanout::1 474 100.00% 100.00% # Request fanout histogram 924system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 925system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 926system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 927system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 928system.cpu.toL2Bus.snoop_fanout::total 474 # Request fanout histogram 929system.cpu.toL2Bus.reqLayer0.occupancy 237000 # Layer occupancy (ticks) |
| 930system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 931system.cpu.toL2Bus.respLayer0.occupancy 562000 # Layer occupancy (ticks) 932system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 933system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) 934system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) | 930system.cpu.toL2Bus.reqLayer0.utilization 1.0 # Layer utilization (%) 931system.cpu.toL2Bus.respLayer0.occupancy 569000 # Layer occupancy (ticks) 932system.cpu.toL2Bus.respLayer0.utilization 2.5 # Layer utilization (%) 933system.cpu.toL2Bus.respLayer1.occupancy 233500 # Layer occupancy (ticks) 934system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) |
| 935system.membus.trans_dist::ReadReq 421 # Transaction distribution 936system.membus.trans_dist::ReadResp 421 # Transaction distribution 937system.membus.trans_dist::ReadExReq 50 # Transaction distribution 938system.membus.trans_dist::ReadExResp 50 # Transaction distribution 939system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) 940system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) 941system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) 942system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) 943system.membus.snoops 0 # Total snoops (count) 944system.membus.snoop_fanout::samples 471 # Request fanout histogram 945system.membus.snoop_fanout::mean 0 # Request fanout histogram 946system.membus.snoop_fanout::stdev 0 # Request fanout histogram 947system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 948system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram 949system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 950system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 951system.membus.snoop_fanout::min_value 0 # Request fanout histogram 952system.membus.snoop_fanout::max_value 0 # Request fanout histogram 953system.membus.snoop_fanout::total 471 # Request fanout histogram | 935system.membus.trans_dist::ReadReq 421 # Transaction distribution 936system.membus.trans_dist::ReadResp 421 # Transaction distribution 937system.membus.trans_dist::ReadExReq 50 # Transaction distribution 938system.membus.trans_dist::ReadExResp 50 # Transaction distribution 939system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 942 # Packet count per connected master and slave (bytes) 940system.membus.pkt_count::total 942 # Packet count per connected master and slave (bytes) 941system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30144 # Cumulative packet size per connected master and slave (bytes) 942system.membus.pkt_size::total 30144 # Cumulative packet size per connected master and slave (bytes) 943system.membus.snoops 0 # Total snoops (count) 944system.membus.snoop_fanout::samples 471 # Request fanout histogram 945system.membus.snoop_fanout::mean 0 # Request fanout histogram 946system.membus.snoop_fanout::stdev 0 # Request fanout histogram 947system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 948system.membus.snoop_fanout::0 471 100.00% 100.00% # Request fanout histogram 949system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 950system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 951system.membus.snoop_fanout::min_value 0 # Request fanout histogram 952system.membus.snoop_fanout::max_value 0 # Request fanout histogram 953system.membus.snoop_fanout::total 471 # Request fanout histogram |
| 954system.membus.reqLayer0.occupancy 594000 # Layer occupancy (ticks) 955system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) 956system.membus.respLayer1.occupancy 4415500 # Layer occupancy (ticks) 957system.membus.respLayer1.utilization 20.9 # Layer utilization (%) | 954system.membus.reqLayer0.occupancy 598000 # Layer occupancy (ticks) 955system.membus.reqLayer0.utilization 2.6 # Layer utilization (%) 956system.membus.respLayer1.occupancy 2506000 # Layer occupancy (ticks) 957system.membus.respLayer1.utilization 11.0 # Layer utilization (%) |
| 958 959---------- End Simulation Statistics ---------- | 958 959---------- End Simulation Statistics ---------- |