| stats.txt (10352:5f1f92bf76ee) | stats.txt (10409:8c80b91944c5) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21611500 # Number of ticks simulated 5final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21611500 # Number of ticks simulated 5final_tick 21611500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 39362 # Simulator instruction rate (inst/s) 8host_op_rate 39354 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 164927772 # Simulator tick rate (ticks/s) 10host_mem_usage 235848 # Number of bytes of host memory used 11host_seconds 0.13 # Real time elapsed on the host | 7host_inst_rate 87050 # Simulator instruction rate (inst/s) 8host_op_rate 87030 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 364707967 # Simulator tick rate (ticks/s) 10host_mem_usage 288672 # Number of bytes of host memory used 11host_seconds 0.06 # Real time elapsed on the host |
| 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30656 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory --- 174 unchanged lines hidden (view full) --- 194system.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation | 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21568 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30656 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21568 # Number of instructions bytes read from this memory --- 174 unchanged lines hidden (view full) --- 194system.physmem.bytesPerActivate::128-255 38 34.86% 64.22% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 15 13.76% 77.98% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 11 10.09% 88.07% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 3 2.75% 90.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::768-895 3 2.75% 93.58% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::896-1023 2 1.83% 95.41% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation |
| 202system.physmem.totQLat 5548500 # Total ticks spent queuing 203system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM | 202system.physmem.totQLat 5601000 # Total ticks spent queuing 203system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers | 204system.physmem.totBusLat 2395000 # Total ticks spent in databus transfers |
| 205system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst | 205system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst |
| 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 206system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 207system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst | 207system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst |
| 208system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 11.08 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 44965.55 # Average gap between requests 223system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states | 208system.physmem.avgRdBW 1418.50 # Average DRAM read bandwidth in MiByte/s 209system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s 210system.physmem.avgRdBWSys 1418.50 # Average system read bandwidth in MiByte/s 211system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 212system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s 213system.physmem.busUtil 11.08 # Data bus utilization in percentage 214system.physmem.busUtilRead 11.08 # Data bus utilization in percentage for reads 215system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes --- 5 unchanged lines hidden (view full) --- 221system.physmem.writeRowHitRate nan # Row buffer hit rate for writes 222system.physmem.avgGap 44965.55 # Average gap between requests 223system.physmem.pageHitRate 75.16 # Row buffer hit rate, read and write combined 224system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 225system.physmem.memoryStateTime::REF 520000 # Time in different power states 226system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 227system.physmem.memoryStateTime::ACT 15315250 # Time in different power states 228system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states |
| 229system.membus.throughput 1418504037 # Throughput (bytes/s) | |
| 230system.membus.trans_dist::ReadReq 428 # Transaction distribution 231system.membus.trans_dist::ReadResp 428 # Transaction distribution 232system.membus.trans_dist::ReadExReq 51 # Transaction distribution 233system.membus.trans_dist::ReadExResp 51 # Transaction distribution 234system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) 235system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) | 229system.membus.trans_dist::ReadReq 428 # Transaction distribution 230system.membus.trans_dist::ReadResp 428 # Transaction distribution 231system.membus.trans_dist::ReadExReq 51 # Transaction distribution 232system.membus.trans_dist::ReadExResp 51 # Transaction distribution 233system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 958 # Packet count per connected master and slave (bytes) 234system.membus.pkt_count::total 958 # Packet count per connected master and slave (bytes) |
| 236system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) 237system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) 238system.membus.data_through_bus 30656 # Total data (bytes) 239system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 235system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes) 236system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes) 237system.membus.snoops 0 # Total snoops (count) 238system.membus.snoop_fanout::samples 479 # Request fanout histogram 239system.membus.snoop_fanout::mean 0 # Request fanout histogram 240system.membus.snoop_fanout::stdev 0 # Request fanout histogram 241system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 242system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram 243system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram 244system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 245system.membus.snoop_fanout::min_value 0 # Request fanout histogram 246system.membus.snoop_fanout::max_value 0 # Request fanout histogram 247system.membus.snoop_fanout::total 479 # Request fanout histogram |
| 240system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 241system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) | 248system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks) 249system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) |
| 242system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks) | 250system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks) |
| 243system.membus.respLayer1.utilization 20.8 # Layer utilization (%) 244system.cpu_clk_domain.clock 500 # Clock period in ticks 245system.cpu.branchPred.lookups 2196 # Number of BP lookups 246system.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted 247system.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect 248system.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups 249system.cpu.branchPred.BTBHits 564 # Number of BTB hits 250system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 306 unchanged lines hidden (view full) --- 557system.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads 558system.cpu.ipc 0.119286 # IPC: Instructions Per Cycle 559system.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads 560system.cpu.int_regfile_reads 11114 # number of integer regfile reads 561system.cpu.int_regfile_writes 5412 # number of integer regfile writes 562system.cpu.fp_regfile_reads 3 # number of floating regfile reads 563system.cpu.fp_regfile_writes 1 # number of floating regfile writes 564system.cpu.misc_regfile_reads 164 # number of misc regfile reads | 251system.membus.respLayer1.utilization 20.8 # Layer utilization (%) 252system.cpu_clk_domain.clock 500 # Clock period in ticks 253system.cpu.branchPred.lookups 2196 # Number of BP lookups 254system.cpu.branchPred.condPredicted 1454 # Number of conditional branches predicted 255system.cpu.branchPred.condIncorrect 435 # Number of conditional branches incorrect 256system.cpu.branchPred.BTBLookups 1700 # Number of BTB lookups 257system.cpu.branchPred.BTBHits 564 # Number of BTB hits 258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. --- 306 unchanged lines hidden (view full) --- 565system.cpu.cpi_total 8.383243 # CPI: Total CPI of All Threads 566system.cpu.ipc 0.119286 # IPC: Instructions Per Cycle 567system.cpu.ipc_total 0.119286 # IPC: Total IPC of All Threads 568system.cpu.int_regfile_reads 11114 # number of integer regfile reads 569system.cpu.int_regfile_writes 5412 # number of integer regfile writes 570system.cpu.fp_regfile_reads 3 # number of floating regfile reads 571system.cpu.fp_regfile_writes 1 # number of floating regfile writes 572system.cpu.misc_regfile_reads 164 # number of misc regfile reads |
| 565system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s) | |
| 566system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution 567system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution 568system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 570system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) 571system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 572system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) | 573system.cpu.toL2Bus.trans_dist::ReadReq 431 # Transaction distribution 574system.cpu.toL2Bus.trans_dist::ReadResp 431 # Transaction distribution 575system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 576system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 577system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 680 # Packet count per connected master and slave (bytes) 578system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 579system.cpu.toL2Bus.pkt_count::total 964 # Packet count per connected master and slave (bytes) |
| 573system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) 574system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes) 577system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) | 580system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes) 581system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 582system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes) 583system.cpu.toL2Bus.snoops 0 # Total snoops (count) 584system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram 585system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram 586system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram 587system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram 588system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram 589system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram 590system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram 591system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram 592system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram 593system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram 594system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram |
| 578system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 579system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 580system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) 581system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 582system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 583system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 584system.cpu.icache.tags.replacements 17 # number of replacements | 595system.cpu.toL2Bus.reqLayer0.occupancy 241000 # Layer occupancy (ticks) 596system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) 597system.cpu.toL2Bus.respLayer0.occupancy 575000 # Layer occupancy (ticks) 598system.cpu.toL2Bus.respLayer0.utilization 2.7 # Layer utilization (%) 599system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) 600system.cpu.toL2Bus.respLayer1.utilization 1.1 # Layer utilization (%) 601system.cpu.icache.tags.replacements 17 # number of replacements |
| 585system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use | 602system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use |
| 586system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. 587system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. 588system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. 589system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 603system.cpu.icache.tags.total_refs 1615 # Total number of references to valid blocks. 604system.cpu.icache.tags.sampled_refs 340 # Sample count of references to valid blocks. 605system.cpu.icache.tags.avg_refs 4.750000 # Average number of references to valid blocks. 606system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 590system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor 591system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy 592system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy | 607system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor 608system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy 609system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy |
| 593system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id 594system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 595system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 596system.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id 597system.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses 598system.cpu.icache.tags.data_accesses 4476 # Number of data accesses 599system.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits 600system.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits 601system.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits 602system.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits 603system.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits 604system.cpu.icache.overall_hits::total 1615 # number of overall hits 605system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses 606system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses 607system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses 608system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses 609system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses 610system.cpu.icache.overall_misses::total 453 # number of overall misses | 610system.cpu.icache.tags.occ_task_id_blocks::1024 323 # Occupied blocks per task id 611system.cpu.icache.tags.age_task_id_blocks_1024::0 154 # Occupied blocks per task id 612system.cpu.icache.tags.age_task_id_blocks_1024::1 169 # Occupied blocks per task id 613system.cpu.icache.tags.occ_task_id_percent::1024 0.157715 # Percentage of cache occupancy per task id 614system.cpu.icache.tags.tag_accesses 4476 # Number of tag accesses 615system.cpu.icache.tags.data_accesses 4476 # Number of data accesses 616system.cpu.icache.ReadReq_hits::cpu.inst 1615 # number of ReadReq hits 617system.cpu.icache.ReadReq_hits::total 1615 # number of ReadReq hits 618system.cpu.icache.demand_hits::cpu.inst 1615 # number of demand (read+write) hits 619system.cpu.icache.demand_hits::total 1615 # number of demand (read+write) hits 620system.cpu.icache.overall_hits::cpu.inst 1615 # number of overall hits 621system.cpu.icache.overall_hits::total 1615 # number of overall hits 622system.cpu.icache.ReadReq_misses::cpu.inst 453 # number of ReadReq misses 623system.cpu.icache.ReadReq_misses::total 453 # number of ReadReq misses 624system.cpu.icache.demand_misses::cpu.inst 453 # number of demand (read+write) misses 625system.cpu.icache.demand_misses::total 453 # number of demand (read+write) misses 626system.cpu.icache.overall_misses::cpu.inst 453 # number of overall misses 627system.cpu.icache.overall_misses::total 453 # number of overall misses |
| 611system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles 612system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles 613system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles 614system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles 615system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles 616system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles | 628system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles 629system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles 630system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles 631system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles 632system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles 633system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles |
| 617system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 618system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 619system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 620system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 621system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 622system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 623system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses 624system.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses 625system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses 626system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses 627system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses 628system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses | 634system.cpu.icache.ReadReq_accesses::cpu.inst 2068 # number of ReadReq accesses(hits+misses) 635system.cpu.icache.ReadReq_accesses::total 2068 # number of ReadReq accesses(hits+misses) 636system.cpu.icache.demand_accesses::cpu.inst 2068 # number of demand (read+write) accesses 637system.cpu.icache.demand_accesses::total 2068 # number of demand (read+write) accesses 638system.cpu.icache.overall_accesses::cpu.inst 2068 # number of overall (read+write) accesses 639system.cpu.icache.overall_accesses::total 2068 # number of overall (read+write) accesses 640system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.219052 # miss rate for ReadReq accesses 641system.cpu.icache.ReadReq_miss_rate::total 0.219052 # miss rate for ReadReq accesses 642system.cpu.icache.demand_miss_rate::cpu.inst 0.219052 # miss rate for demand accesses 643system.cpu.icache.demand_miss_rate::total 0.219052 # miss rate for demand accesses 644system.cpu.icache.overall_miss_rate::cpu.inst 0.219052 # miss rate for overall accesses 645system.cpu.icache.overall_miss_rate::total 0.219052 # miss rate for overall accesses |
| 629system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency 630system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency 631system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency 632system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency 633system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency 634system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency | 646system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency 647system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency 648system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 649system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency 650system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency 651system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency |
| 635system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 636system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 637system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 638system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 639system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked 640system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 641system.cpu.icache.fast_writes 0 # number of fast writes performed 642system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 647system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 648system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 649system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses 650system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses 651system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses 652system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses 653system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses 654system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses | 652system.cpu.icache.blocked_cycles::no_mshrs 48 # number of cycles access was blocked 653system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 654system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 655system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 656system.cpu.icache.avg_blocked_cycles::no_mshrs 48 # average number of cycles each access was blocked 657system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 658system.cpu.icache.fast_writes 0 # number of fast writes performed 659system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 664system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 665system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 666system.cpu.icache.ReadReq_mshr_misses::cpu.inst 340 # number of ReadReq MSHR misses 667system.cpu.icache.ReadReq_mshr_misses::total 340 # number of ReadReq MSHR misses 668system.cpu.icache.demand_mshr_misses::cpu.inst 340 # number of demand (read+write) MSHR misses 669system.cpu.icache.demand_mshr_misses::total 340 # number of demand (read+write) MSHR misses 670system.cpu.icache.overall_mshr_misses::cpu.inst 340 # number of overall MSHR misses 671system.cpu.icache.overall_mshr_misses::total 340 # number of overall MSHR misses |
| 655system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles 656system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles 657system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles 658system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles 659system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles 660system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles | 672system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles 673system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles 674system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles 675system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles 676system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles 677system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles |
| 661system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses 662system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses 663system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses 664system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses 665system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses 666system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses | 678system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for ReadReq accesses 679system.cpu.icache.ReadReq_mshr_miss_rate::total 0.164410 # mshr miss rate for ReadReq accesses 680system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for demand accesses 681system.cpu.icache.demand_mshr_miss_rate::total 0.164410 # mshr miss rate for demand accesses 682system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.164410 # mshr miss rate for overall accesses 683system.cpu.icache.overall_mshr_miss_rate::total 0.164410 # mshr miss rate for overall accesses |
| 667system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency 668system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency 669system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency 670system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency 671system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency 672system.cpu.icache.overall_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency | 684system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency 685system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency 686system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 687system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency 688system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency 689system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency |
| 673system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 674system.cpu.l2cache.tags.replacements 0 # number of replacements | 690system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 691system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 675system.cpu.l2cache.tags.tagsinuse 222.300532 # Cycle average of tags in use | 692system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use |
| 676system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 677system.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. 678system.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. 679system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 693system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 694system.cpu.l2cache.tags.sampled_refs 428 # Sample count of references to valid blocks. 695system.cpu.l2cache.tags.avg_refs 0.007009 # Average number of references to valid blocks. 696system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 680system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor 681system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685875 # Average occupied blocks per requestor | 697system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor 698system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor |
| 682system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy 683system.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy 684system.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_task_id_blocks::1024 428 # Occupied blocks per task id 686system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 687system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 688system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013062 # Percentage of cache occupancy per task id 689system.cpu.l2cache.tags.tag_accesses 4335 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 700system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 701system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 702system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses 703system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 704system.cpu.l2cache.demand_misses::total 479 # number of demand (read+write) misses 705system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses 706system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 707system.cpu.l2cache.overall_misses::total 479 # number of overall misses | 699system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004993 # Average percentage of cache occupancy 700system.cpu.l2cache.tags.occ_percent::cpu.data 0.001791 # Average percentage of cache occupancy 701system.cpu.l2cache.tags.occ_percent::total 0.006784 # Average percentage of cache occupancy 702system.cpu.l2cache.tags.occ_task_id_blocks::1024 428 # Occupied blocks per task id 703system.cpu.l2cache.tags.age_task_id_blocks_1024::0 193 # Occupied blocks per task id 704system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id 705system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013062 # Percentage of cache occupancy per task id 706system.cpu.l2cache.tags.tag_accesses 4335 # Number of tag accesses --- 10 unchanged lines hidden (view full) --- 717system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 718system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 719system.cpu.l2cache.demand_misses::cpu.inst 337 # number of demand (read+write) misses 720system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 721system.cpu.l2cache.demand_misses::total 479 # number of demand (read+write) misses 722system.cpu.l2cache.overall_misses::cpu.inst 337 # number of overall misses 723system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 724system.cpu.l2cache.overall_misses::total 479 # number of overall misses |
| 708system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24254500 # number of ReadReq miss cycles 709system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7288250 # number of ReadReq miss cycles 710system.cpu.l2cache.ReadReq_miss_latency::total 31542750 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4058000 # number of ReadExReq miss cycles 712system.cpu.l2cache.ReadExReq_miss_latency::total 4058000 # number of ReadExReq miss cycles 713system.cpu.l2cache.demand_miss_latency::cpu.inst 24254500 # number of demand (read+write) miss cycles 714system.cpu.l2cache.demand_miss_latency::cpu.data 11346250 # number of demand (read+write) miss cycles 715system.cpu.l2cache.demand_miss_latency::total 35600750 # number of demand (read+write) miss cycles 716system.cpu.l2cache.overall_miss_latency::cpu.inst 24254500 # number of overall miss cycles 717system.cpu.l2cache.overall_miss_latency::cpu.data 11346250 # number of overall miss cycles 718system.cpu.l2cache.overall_miss_latency::total 35600750 # number of overall miss cycles | 725system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles 726system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles 727system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles 728system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles 729system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles 730system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles 731system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles 732system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles 733system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles 734system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles 735system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles |
| 719system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) 720system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 721system.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 723system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 724system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses 725system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 726system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 733system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 734system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 735system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991176 # miss rate for demand accesses 736system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 737system.cpu.l2cache.demand_miss_rate::total 0.993776 # miss rate for demand accesses 738system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses 739system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 740system.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses | 736system.cpu.l2cache.ReadReq_accesses::cpu.inst 340 # number of ReadReq accesses(hits+misses) 737system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 738system.cpu.l2cache.ReadReq_accesses::total 431 # number of ReadReq accesses(hits+misses) 739system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 740system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 741system.cpu.l2cache.demand_accesses::cpu.inst 340 # number of demand (read+write) accesses 742system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 743system.cpu.l2cache.demand_accesses::total 482 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 750system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 751system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 752system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991176 # miss rate for demand accesses 753system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 754system.cpu.l2cache.demand_miss_rate::total 0.993776 # miss rate for demand accesses 755system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991176 # miss rate for overall accesses 756system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 757system.cpu.l2cache.overall_miss_rate::total 0.993776 # miss rate for overall accesses |
| 741system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71971.810089 # average ReadReq miss latency 742system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80090.659341 # average ReadReq miss latency 743system.cpu.l2cache.ReadReq_avg_miss_latency::total 73698.014019 # average ReadReq miss latency 744system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79568.627451 # average ReadExReq miss latency 745system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79568.627451 # average ReadExReq miss latency 746system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency 747system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency 748system.cpu.l2cache.demand_avg_miss_latency::total 74323.068894 # average overall miss latency 749system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency 750system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894 # average overall miss latency | 758system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency 759system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency 760system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency 761system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency 762system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency 763system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 764system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency 765system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency 766system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency 767system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency 768system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency |
| 752system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 753system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 754system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 755system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 756system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 757system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 758system.cpu.l2cache.fast_writes 0 # number of fast writes performed 759system.cpu.l2cache.cache_copies 0 # number of cache copies performed 760system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 761system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 762system.cpu.l2cache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 763system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 764system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 765system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 766system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 767system.cpu.l2cache.demand_mshr_misses::total 479 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 769system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 770system.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses | 769system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 770system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 771system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 772system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 773system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 774system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 775system.cpu.l2cache.fast_writes 0 # number of fast writes performed 776system.cpu.l2cache.cache_copies 0 # number of cache copies performed 777system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 337 # number of ReadReq MSHR misses 778system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 779system.cpu.l2cache.ReadReq_mshr_misses::total 428 # number of ReadReq MSHR misses 780system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 781system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 782system.cpu.l2cache.demand_mshr_misses::cpu.inst 337 # number of demand (read+write) MSHR misses 783system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 784system.cpu.l2cache.demand_mshr_misses::total 479 # number of demand (read+write) MSHR misses 785system.cpu.l2cache.overall_mshr_misses::cpu.inst 337 # number of overall MSHR misses 786system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 787system.cpu.l2cache.overall_mshr_misses::total 479 # number of overall MSHR misses |
| 771system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19999000 # number of ReadReq MSHR miss cycles 772system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6168250 # number of ReadReq MSHR miss cycles 773system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26167250 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3423500 # number of ReadExReq MSHR miss cycles 775system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3423500 # number of ReadExReq MSHR miss cycles 776system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19999000 # number of demand (read+write) MSHR miss cycles 777system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9591750 # number of demand (read+write) MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::total 29590750 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19999000 # number of overall MSHR miss cycles 780system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9591750 # number of overall MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::total 29590750 # number of overall MSHR miss cycles | 788system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles 789system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles 790system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles 791system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles 792system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles 793system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles 794system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles 795system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles 796system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles 797system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles 798system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles |
| 782system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses 783system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 784system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 786system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 787system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for demand accesses 788system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 789system.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 # mshr miss rate for demand accesses 790system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses 791system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 792system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses | 799system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for ReadReq accesses 800system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 801system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993039 # mshr miss rate for ReadReq accesses 802system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 803system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 804system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for demand accesses 805system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 806system.cpu.l2cache.demand_mshr_miss_rate::total 0.993776 # mshr miss rate for demand accesses 807system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991176 # mshr miss rate for overall accesses 808system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 809system.cpu.l2cache.overall_mshr_miss_rate::total 0.993776 # mshr miss rate for overall accesses |
| 793system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency 794system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency 797system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency 798system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency 799system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency 801system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency 802system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency | 810system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency 811system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency 812system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency 813system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency 814system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency 815system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 816system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 817system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency 818system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency 819system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency 820system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency |
| 804system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 805system.cpu.dcache.tags.replacements 0 # number of replacements | 821system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 822system.cpu.dcache.tags.replacements 0 # number of replacements |
| 806system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use | 823system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use |
| 807system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. 808system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 809system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. 810system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 824system.cpu.dcache.tags.total_refs 2508 # Total number of references to valid blocks. 825system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 826system.cpu.dcache.tags.avg_refs 17.661972 # Average number of references to valid blocks. 827system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 811system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor | 828system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor |
| 812system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy 813system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy 814system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 815system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 816system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 817system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 818system.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses 819system.cpu.dcache.tags.data_accesses 6220 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 828system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 829system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 830system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 831system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 832system.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses 833system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses 834system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses 835system.cpu.dcache.overall_misses::total 531 # number of overall misses | 829system.cpu.dcache.tags.occ_percent::cpu.data 0.022566 # Average percentage of cache occupancy 830system.cpu.dcache.tags.occ_percent::total 0.022566 # Average percentage of cache occupancy 831system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 832system.cpu.dcache.tags.age_task_id_blocks_1024::0 38 # Occupied blocks per task id 833system.cpu.dcache.tags.age_task_id_blocks_1024::1 104 # Occupied blocks per task id 834system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 835system.cpu.dcache.tags.tag_accesses 6220 # Number of tag accesses 836system.cpu.dcache.tags.data_accesses 6220 # Number of data accesses --- 8 unchanged lines hidden (view full) --- 845system.cpu.dcache.ReadReq_misses::cpu.data 169 # number of ReadReq misses 846system.cpu.dcache.ReadReq_misses::total 169 # number of ReadReq misses 847system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 848system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 849system.cpu.dcache.demand_misses::cpu.data 531 # number of demand (read+write) misses 850system.cpu.dcache.demand_misses::total 531 # number of demand (read+write) misses 851system.cpu.dcache.overall_misses::cpu.data 531 # number of overall misses 852system.cpu.dcache.overall_misses::total 531 # number of overall misses |
| 836system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles 837system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles 838system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles 839system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles 840system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles 841system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles 842system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles 843system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles | 853system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles 854system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles 855system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles 856system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles 857system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles 858system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles 859system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles 860system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles |
| 844system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) 845system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) 846system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 847system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 848system.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses 849system.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses 850system.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses 851system.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses 852system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses 853system.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses 854system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 855system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 856system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses 857system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses 858system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses 859system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses | 861system.cpu.dcache.ReadReq_accesses::cpu.data 2114 # number of ReadReq accesses(hits+misses) 862system.cpu.dcache.ReadReq_accesses::total 2114 # number of ReadReq accesses(hits+misses) 863system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 864system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 865system.cpu.dcache.demand_accesses::cpu.data 3039 # number of demand (read+write) accesses 866system.cpu.dcache.demand_accesses::total 3039 # number of demand (read+write) accesses 867system.cpu.dcache.overall_accesses::cpu.data 3039 # number of overall (read+write) accesses 868system.cpu.dcache.overall_accesses::total 3039 # number of overall (read+write) accesses 869system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.079943 # miss rate for ReadReq accesses 870system.cpu.dcache.ReadReq_miss_rate::total 0.079943 # miss rate for ReadReq accesses 871system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 872system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 873system.cpu.dcache.demand_miss_rate::cpu.data 0.174729 # miss rate for demand accesses 874system.cpu.dcache.demand_miss_rate::total 0.174729 # miss rate for demand accesses 875system.cpu.dcache.overall_miss_rate::cpu.data 0.174729 # miss rate for overall accesses 876system.cpu.dcache.overall_miss_rate::total 0.174729 # miss rate for overall accesses |
| 860system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency 861system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency 862system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency 863system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency 864system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency 865system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency 866system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency 867system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency | 877system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency 878system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency 879system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency 880system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency 881system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 882system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency 883system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency 884system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency |
| 868system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 869system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 870system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 871system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 872system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 873system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 874system.cpu.dcache.fast_writes 0 # number of fast writes performed 875system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 884system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 885system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 886system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 887system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 888system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 889system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 890system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 891system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 885system.cpu.dcache.blocked_cycles::no_mshrs 573 # number of cycles access was blocked 886system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 887system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 888system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked 889system.cpu.dcache.avg_blocked_cycles::no_mshrs 52.090909 # average number of cycles each access was blocked 890system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 891system.cpu.dcache.fast_writes 0 # number of fast writes performed 892system.cpu.dcache.cache_copies 0 # number of cache copies performed --- 8 unchanged lines hidden (view full) --- 901system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 902system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 903system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 904system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 905system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 906system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 907system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 908system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 892system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles 893system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles 894system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles 895system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles 896system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles 897system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles 898system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles 899system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles | 909system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles 910system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles 911system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles 912system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles 913system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles 914system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles 915system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles 916system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles |
| 900system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses 901system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 902system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 903system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 904system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses 905system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses 906system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses 907system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses | 917system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.043046 # mshr miss rate for ReadReq accesses 918system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.043046 # mshr miss rate for ReadReq accesses 919system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 920system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 921system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for demand accesses 922system.cpu.dcache.demand_mshr_miss_rate::total 0.046726 # mshr miss rate for demand accesses 923system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.046726 # mshr miss rate for overall accesses 924system.cpu.dcache.overall_mshr_miss_rate::total 0.046726 # mshr miss rate for overall accesses |
| 908system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency 909system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency 910system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency 911system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency 912system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency 913system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency 914system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency 915system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency | 925system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency 926system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency 927system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency 928system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency 929system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 930system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency 931system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency 932system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency |
| 916system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 917 918---------- End Simulation Statistics ---------- | 933system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 934 935---------- End Simulation Statistics ---------- |