| stats.txt (10148:4574d5882066) | stats.txt (10220:9eab5efc02e8) |
|---|---|
| 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated | 1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated |
| 4sim_ticks 21918500 # Number of ticks simulated 5final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) | 4sim_ticks 21843500 # Number of ticks simulated 5final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) |
| 6sim_freq 1000000000000 # Frequency of simulated ticks | 6sim_freq 1000000000000 # Frequency of simulated ticks |
| 7host_inst_rate 56826 # Simulator instruction rate (inst/s) 8host_op_rate 56817 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 241494238 # Simulator tick rate (ticks/s) 10host_mem_usage 266500 # Number of bytes of host memory used 11host_seconds 0.09 # Real time elapsed on the host | 7host_inst_rate 63396 # Simulator instruction rate (inst/s) 8host_op_rate 63384 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 268482897 # Simulator tick rate (ticks/s) 10host_mem_usage 267540 # Number of bytes of host memory used 11host_seconds 0.08 # Real time elapsed on the host |
| 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 477 # Number of read requests responded to by this memory | 12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.voltage_domain.voltage 1 # Voltage in Volts 15system.clk_domain.clock 1000 # Clock period in ticks 16system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 17system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 18system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 19system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 20system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 21system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory 22system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory 23system.physmem.num_reads::total 477 # Number of read requests responded to by this memory |
| 24system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s) | 24system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s) 25system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s) 26system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s) 27system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s) 28system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s) 29system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s) 30system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s) 31system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s) |
| 32system.physmem.readReqs 477 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry | 32system.physmem.readReqs 477 # Number of read requests accepted 33system.physmem.writeReqs 0 # Number of write requests accepted 34system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue 35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue 36system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM 37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue 38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM 39system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side --- 30 unchanged lines hidden (view full) --- 70system.physmem.perBankWrBursts::10 0 # Per bank write bursts 71system.physmem.perBankWrBursts::11 0 # Per bank write bursts 72system.physmem.perBankWrBursts::12 0 # Per bank write bursts 73system.physmem.perBankWrBursts::13 0 # Per bank write bursts 74system.physmem.perBankWrBursts::14 0 # Per bank write bursts 75system.physmem.perBankWrBursts::15 0 # Per bank write bursts 76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry 77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry |
| 78system.physmem.totGap 21839000 # Total gap between requests | 78system.physmem.totGap 21764000 # Total gap between requests |
| 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 477 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) | 79system.physmem.readPktSize::0 0 # Read request sizes (log2) 80system.physmem.readPktSize::1 0 # Read request sizes (log2) 81system.physmem.readPktSize::2 0 # Read request sizes (log2) 82system.physmem.readPktSize::3 0 # Read request sizes (log2) 83system.physmem.readPktSize::4 0 # Read request sizes (log2) 84system.physmem.readPktSize::5 0 # Read request sizes (log2) 85system.physmem.readPktSize::6 477 # Read request sizes (log2) 86system.physmem.writePktSize::0 0 # Write request sizes (log2) 87system.physmem.writePktSize::1 0 # Write request sizes (log2) 88system.physmem.writePktSize::2 0 # Write request sizes (log2) 89system.physmem.writePktSize::3 0 # Write request sizes (log2) 90system.physmem.writePktSize::4 0 # Write request sizes (log2) 91system.physmem.writePktSize::5 0 # Write request sizes (log2) 92system.physmem.writePktSize::6 0 # Write request sizes (log2) |
| 93system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see | 93system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see |
| 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see | 95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see |
| 96system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see | 96system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see 97system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see |
| 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see | 98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see 101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see 102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see 103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see 104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see 105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see --- 75 unchanged lines hidden (view full) --- 181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see 182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see 183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see 184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see 185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see 186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see 187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see 188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see |
| 189system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation 202system.physmem.totQLat 2715000 # Total ticks spent queuing 203system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM | 189system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation 190system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation 191system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation 192system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation 193system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation 194system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation 195system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation 196system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation 197system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation 198system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation 199system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation 200system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation 201system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation 202system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation 203system.physmem.totQLat 4715500 # Total ticks spent queuing 204system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM |
| 204system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers | 205system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers |
| 205system.physmem.totBankLat 8676250 # Total ticks spent accessing banks 206system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst 207system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst | 206system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst |
| 208system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst | 207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst |
| 209system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst 210system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s | 208system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst 209system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s |
| 211system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s | 210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s |
| 212system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s | 211system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s |
| 213system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 214system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s | 212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s 213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s |
| 215system.physmem.busUtil 10.88 # Data bus utilization in percentage 216system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads | 214system.physmem.busUtil 10.92 # Data bus utilization in percentage 215system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads |
| 217system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 218system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 219system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 220system.physmem.readRowHits 357 # Number of row buffer hits during reads 221system.physmem.writeRowHits 0 # Number of row buffer hits during writes 222system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads 223system.physmem.writeRowHitRate nan # Row buffer hit rate for writes | 216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes 217system.physmem.avgRdQLen 1.70 # Average read queue length when enqueuing 218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing 219system.physmem.readRowHits 357 # Number of row buffer hits during reads 220system.physmem.writeRowHits 0 # Number of row buffer hits during writes 221system.physmem.readRowHitRate 74.84 # Row buffer hit rate for reads 222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes |
| 224system.physmem.avgGap 45784.07 # Average gap between requests | 223system.physmem.avgGap 45626.83 # Average gap between requests |
| 225system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined | 224system.physmem.pageHitRate 74.84 # Row buffer hit rate, read and write combined |
| 226system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state 227system.membus.throughput 1392796040 # Throughput (bytes/s) | 225system.physmem.memoryStateTime::IDLE 11000 # Time in different power states 226system.physmem.memoryStateTime::REF 520000 # Time in different power states 227system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states 228system.physmem.memoryStateTime::ACT 15319000 # Time in different power states 229system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states 230system.membus.throughput 1397578227 # Throughput (bytes/s) |
| 228system.membus.trans_dist::ReadReq 426 # Transaction distribution 229system.membus.trans_dist::ReadResp 426 # Transaction distribution 230system.membus.trans_dist::ReadExReq 51 # Transaction distribution 231system.membus.trans_dist::ReadExResp 51 # Transaction distribution 232system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 233system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 234system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 235system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 236system.membus.data_through_bus 30528 # Total data (bytes) 237system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) | 231system.membus.trans_dist::ReadReq 426 # Transaction distribution 232system.membus.trans_dist::ReadResp 426 # Transaction distribution 233system.membus.trans_dist::ReadExReq 51 # Transaction distribution 234system.membus.trans_dist::ReadExResp 51 # Transaction distribution 235system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 236system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 237system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 238system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 239system.membus.data_through_bus 30528 # Total data (bytes) 240system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
| 238system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) | 241system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks) |
| 239system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) | 242system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) |
| 240system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks) 241system.membus.respLayer1.utilization 20.4 # Layer utilization (%) | 243system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks) 244system.membus.respLayer1.utilization 20.5 # Layer utilization (%) |
| 242system.cpu_clk_domain.clock 500 # Clock period in ticks 243system.cpu.branchPred.lookups 2174 # Number of BP lookups 244system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 245system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 246system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 247system.cpu.branchPred.BTBHits 492 # Number of BTB hits 248system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 249system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage --- 13 unchanged lines hidden (view full) --- 263system.cpu.itb.read_accesses 0 # DTB read accesses 264system.cpu.itb.write_hits 0 # DTB write hits 265system.cpu.itb.write_misses 0 # DTB write misses 266system.cpu.itb.write_accesses 0 # DTB write accesses 267system.cpu.itb.hits 0 # DTB hits 268system.cpu.itb.misses 0 # DTB misses 269system.cpu.itb.accesses 0 # DTB accesses 270system.cpu.workload.num_syscalls 8 # Number of system calls | 245system.cpu_clk_domain.clock 500 # Clock period in ticks 246system.cpu.branchPred.lookups 2174 # Number of BP lookups 247system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 248system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 249system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 250system.cpu.branchPred.BTBHits 492 # Number of BTB hits 251system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 252system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage --- 13 unchanged lines hidden (view full) --- 266system.cpu.itb.read_accesses 0 # DTB read accesses 267system.cpu.itb.write_hits 0 # DTB write hits 268system.cpu.itb.write_misses 0 # DTB write misses 269system.cpu.itb.write_accesses 0 # DTB write accesses 270system.cpu.itb.hits 0 # DTB hits 271system.cpu.itb.misses 0 # DTB misses 272system.cpu.itb.accesses 0 # DTB accesses 273system.cpu.workload.num_syscalls 8 # Number of system calls |
| 271system.cpu.numCycles 43838 # number of cpu cycles simulated | 274system.cpu.numCycles 43688 # number of cpu cycles simulated |
| 272system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 273system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 274system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss 275system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed 276system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 277system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken 278system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked 279system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing | 275system.cpu.numWorkItemsStarted 0 # number of work items this cpu started 276system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed 277system.cpu.fetch.icacheStallCycles 8831 # Number of cycles fetch is stalled on an Icache miss 278system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed 279system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered 280system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken 281system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked 282system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing |
| 280system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked | 283system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked |
| 281system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 282system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 283system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed | 284system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps 285system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched 286system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed |
| 284system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total) 285system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total) 286system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total) | 287system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total) 288system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total) |
| 287system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) | 290system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total) |
| 288system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total) 289system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total) 290system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total) 291system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total) | 291system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total) 292system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total) |
| 292system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) 293system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) 294system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) 295system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) | 295system.cpu.fetch.rateDist::4 305 2.10% 90.65% # Number of instructions fetched each cycle (Total) 296system.cpu.fetch.rateDist::5 115 0.79% 91.44% # Number of instructions fetched each cycle (Total) 297system.cpu.fetch.rateDist::6 150 1.03% 92.48% # Number of instructions fetched each cycle (Total) 298system.cpu.fetch.rateDist::7 158 1.09% 93.57% # Number of instructions fetched each cycle (Total) 299system.cpu.fetch.rateDist::8 933 6.43% 100.00% # Number of instructions fetched each cycle (Total) 300system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 302system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) |
| 300system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total) 301system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle 302system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle | 303system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total) 304system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle 305system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle |
| 303system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle | 306system.cpu.decode.IdleCycles 8899 # Number of cycles decode is idle |
| 304system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked | 307system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked |
| 305system.cpu.decode.RunCycles 3025 # Number of cycles decode is running 306system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 307system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 308system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 309system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 310system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode 311system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 312system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing 313system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle | 308system.cpu.decode.RunCycles 3025 # Number of cycles decode is running 309system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 310system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 311system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 312system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction 313system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode 314system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 315system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing 316system.cpu.rename.IdleCycles 9081 # Number of cycles rename is idle |
| 314system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking 315system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst | 317system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking 318system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst |
| 316system.cpu.rename.RunCycles 2898 # Number of cycles rename is running 317system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 318system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename 319system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 320system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 321system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 322system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 323system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made --- 10 unchanged lines hidden (view full) --- 334system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 335system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) 336system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 337system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued 338system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 339system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling 340system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph 341system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed | 319system.cpu.rename.RunCycles 2898 # Number of cycles rename is running 320system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking 321system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename 322system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 323system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 324system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full 325system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 326system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made --- 10 unchanged lines hidden (view full) --- 337system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 338system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) 339system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ 340system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued 341system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued 342system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling 343system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph 344system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed |
| 342system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle 343system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle 344system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle | 345system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle 346system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle |
| 345system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle | 348system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle |
| 346system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle 347system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle 348system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle 349system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle | 349system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle 350system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle |
| 350system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle 351system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle 352system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle 353system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle | 353system.cpu.iq.issued_per_cycle::4 355 2.45% 97.50% # Number of insts issued each cycle 354system.cpu.iq.issued_per_cycle::5 226 1.56% 99.06% # Number of insts issued each cycle 355system.cpu.iq.issued_per_cycle::6 89 0.61% 99.68% # Number of insts issued each cycle 356system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle 357system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle 358system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle 359system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle 360system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle |
| 358system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle | 361system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle |
| 359system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 360system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 361system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 362system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 363system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 364system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 365system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 420system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued 421system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued 422system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued 423system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued 424system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued 425system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 426system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 427system.cpu.iq.FU_type_0::total 8293 # Type of FU issued | 362system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available 363system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available 364system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available 365system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available 366system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available 367system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available 368system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available 369system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available --- 53 unchanged lines hidden (view full) --- 423system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued 424system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued 425system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued 426system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued 427system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued 428system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued 429system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued 430system.cpu.iq.FU_type_0::total 8293 # Type of FU issued |
| 428system.cpu.iq.rate 0.189174 # Inst issue rate | 431system.cpu.iq.rate 0.189823 # Inst issue rate |
| 429system.cpu.iq.fu_busy_cnt 160 # FU busy when requested 430system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) | 432system.cpu.iq.fu_busy_cnt 160 # FU busy when requested 433system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst) |
| 431system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads | 434system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads |
| 432system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes 433system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses 434system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 435system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 436system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 437system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses 438system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 439system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 464system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions 465system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed 466system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 467system.cpu.iew.exec_swp 0 # number of swp insts executed 468system.cpu.iew.exec_nop 1512 # number of nop insts executed 469system.cpu.iew.exec_refs 3186 # number of memory reference insts executed 470system.cpu.iew.exec_branches 1344 # Number of branches executed 471system.cpu.iew.exec_stores 1079 # Number of stores executed | 435system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes 436system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses 437system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads 438system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes 439system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses 440system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses 441system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses 442system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores --- 24 unchanged lines hidden (view full) --- 467system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions 468system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed 469system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute 470system.cpu.iew.exec_swp 0 # number of swp insts executed 471system.cpu.iew.exec_nop 1512 # number of nop insts executed 472system.cpu.iew.exec_refs 3186 # number of memory reference insts executed 473system.cpu.iew.exec_branches 1344 # Number of branches executed 474system.cpu.iew.exec_stores 1079 # Number of stores executed |
| 472system.cpu.iew.exec_rate 0.180483 # Inst execution rate | 475system.cpu.iew.exec_rate 0.181102 # Inst execution rate |
| 473system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit 474system.cpu.iew.wb_count 7455 # cumulative count of insts written-back 475system.cpu.iew.wb_producers 2921 # num instructions producing a value 476system.cpu.iew.wb_consumers 4197 # num instructions consuming a value 477system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ | 476system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit 477system.cpu.iew.wb_count 7455 # cumulative count of insts written-back 478system.cpu.iew.wb_producers 2921 # num instructions producing a value 479system.cpu.iew.wb_consumers 4197 # num instructions consuming a value 480system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ |
| 478system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle | 481system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle |
| 479system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 480system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 481system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit 482system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 483system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted | 482system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back 483system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ 484system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit 485system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards 486system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted |
| 484system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle 485system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle 486system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle | 487system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle 488system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle 489system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle |
| 487system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle | 490system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle |
| 488system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle | 491system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle |
| 489system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle 490system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle 491system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle 492system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle | 492system.cpu.commit.committed_per_cycle::1 999 7.33% 89.71% # Number of insts commited each cycle 493system.cpu.commit.committed_per_cycle::2 630 4.62% 94.33% # Number of insts commited each cycle 494system.cpu.commit.committed_per_cycle::3 315 2.31% 96.64% # Number of insts commited each cycle 495system.cpu.commit.committed_per_cycle::4 149 1.09% 97.73% # Number of insts commited each cycle 496system.cpu.commit.committed_per_cycle::5 94 0.69% 98.42% # Number of insts commited each cycle 497system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle 498system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle 499system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle 500system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle 501system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle 502system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle |
| 500system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle | 503system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle |
| 501system.cpu.commit.committedInsts 5813 # Number of instructions committed 502system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 503system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 504system.cpu.commit.refs 2088 # Number of memory references committed 505system.cpu.commit.loads 1163 # Number of loads committed 506system.cpu.commit.membars 0 # Number of memory barriers committed 507system.cpu.commit.branches 915 # Number of branches committed 508system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 509system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 510system.cpu.commit.function_calls 87 # Number of function calls committed. | 504system.cpu.commit.committedInsts 5813 # Number of instructions committed 505system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed 506system.cpu.commit.swp_count 0 # Number of s/w prefetches committed 507system.cpu.commit.refs 2088 # Number of memory references committed 508system.cpu.commit.loads 1163 # Number of loads committed 509system.cpu.commit.membars 0 # Number of memory barriers committed 510system.cpu.commit.branches 915 # Number of branches committed 511system.cpu.commit.fp_insts 2 # Number of committed floating point instructions. 512system.cpu.commit.int_insts 5111 # Number of committed integer instructions. 513system.cpu.commit.function_calls 87 # Number of function calls committed. |
| 514system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction 515system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction 516system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction 517system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction 518system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction 519system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction 520system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction 521system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction 522system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction 523system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction 524system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction 525system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction 526system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction 527system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction 528system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction 529system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction 530system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction 531system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction 532system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction 533system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction 534system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction 535system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction 536system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction 537system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction 538system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction 539system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction 540system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction 541system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction 542system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction 543system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction 544system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction 545system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction 546system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction 547system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction 548system.cpu.commit.op_class_0::total 5813 # Class of committed instruction |
|
| 511system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 512system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits | 549system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached 550system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits |
| 513system.cpu.rob.rob_reads 24245 # The number of ROB reads | 551system.cpu.rob.rob_reads 24239 # The number of ROB reads |
| 514system.cpu.rob.rob_writes 22333 # The number of ROB writes | 552system.cpu.rob.rob_writes 22333 # The number of ROB writes |
| 515system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself 516system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling | 553system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself 554system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling |
| 517system.cpu.committedInsts 5156 # Number of Instructions Simulated 518system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 519system.cpu.committedInsts_total 5156 # Number of Instructions Simulated | 555system.cpu.committedInsts 5156 # Number of Instructions Simulated 556system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated 557system.cpu.committedInsts_total 5156 # Number of Instructions Simulated |
| 520system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction 521system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads 522system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle 523system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads | 558system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction 559system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads 560system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle 561system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads |
| 524system.cpu.int_regfile_reads 10743 # number of integer regfile reads 525system.cpu.int_regfile_writes 5234 # number of integer regfile writes 526system.cpu.fp_regfile_reads 3 # number of floating regfile reads 527system.cpu.fp_regfile_writes 1 # number of floating regfile writes 528system.cpu.misc_regfile_reads 148 # number of misc regfile reads | 562system.cpu.int_regfile_reads 10743 # number of integer regfile reads 563system.cpu.int_regfile_writes 5234 # number of integer regfile writes 564system.cpu.fp_regfile_reads 3 # number of floating regfile reads 565system.cpu.fp_regfile_writes 1 # number of floating regfile writes 566system.cpu.misc_regfile_reads 148 # number of misc regfile reads |
| 529system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s) | 567system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s) |
| 530system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 531system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 532system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 533system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 534system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 535system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 536system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 537system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 538system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 539system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 540system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 541system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 542system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 543system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) | 568system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution 569system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution 570system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution 571system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution 572system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes) 573system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes) 574system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes) 575system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes) 576system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes) 577system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes) 578system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes) 579system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes) 580system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks) 581system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%) |
| 544system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks) | 582system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks) |
| 545system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) | 583system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%) |
| 546system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks) | 584system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks) |
| 547system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 548system.cpu.icache.tags.replacements 17 # number of replacements | 585system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%) 586system.cpu.icache.tags.replacements 17 # number of replacements |
| 549system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use | 587system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use |
| 550system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. 551system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 552system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. 553system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 588system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks. 589system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks. 590system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks. 591system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 554system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor 555system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy 556system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy | 592system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor 593system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy 594system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy |
| 557system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 558system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 559system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 560system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id 561system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses 562system.cpu.icache.tags.data_accesses 4268 # Number of data accesses 563system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits 564system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits 565system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits 566system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits 567system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 568system.cpu.icache.overall_hits::total 1514 # number of overall hits 569system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 570system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 571system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 572system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 573system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 574system.cpu.icache.overall_misses::total 451 # number of overall misses | 595system.cpu.icache.tags.occ_task_id_blocks::1024 321 # Occupied blocks per task id 596system.cpu.icache.tags.age_task_id_blocks_1024::0 149 # Occupied blocks per task id 597system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id 598system.cpu.icache.tags.occ_task_id_percent::1024 0.156738 # Percentage of cache occupancy per task id 599system.cpu.icache.tags.tag_accesses 4268 # Number of tag accesses 600system.cpu.icache.tags.data_accesses 4268 # Number of data accesses 601system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits 602system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits 603system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits 604system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits 605system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 606system.cpu.icache.overall_hits::total 1514 # number of overall hits 607system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 608system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 609system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 610system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 611system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 612system.cpu.icache.overall_misses::total 451 # number of overall misses |
| 575system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles 576system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles 577system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles 578system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles 579system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles 580system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles | 613system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles 614system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles 615system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles 616system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles 617system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles 618system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles |
| 581system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 582system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 583system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 584system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 585system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 586system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 587system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 588system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 589system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 590system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 591system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 592system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses | 619system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 620system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 621system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 622system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 623system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 624system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 625system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 627system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 628system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 629system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 630system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses |
| 593system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency 594system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency 595system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency 596system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency 597system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency 598system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency | 631system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency 632system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency 633system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 634system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency 635system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency 636system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency |
| 599system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 600system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 601system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 602system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 603system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 604system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 605system.cpu.icache.fast_writes 0 # number of fast writes performed 606system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 611system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 612system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 613system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 614system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 615system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 616system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 617system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 618system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses | 637system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 638system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 639system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 640system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 641system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 642system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 643system.cpu.icache.fast_writes 0 # number of fast writes performed 644system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 649system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 650system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 651system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 652system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 653system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 654system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 655system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 656system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses |
| 619system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles 620system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles 621system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles 622system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles 623system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles 624system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles | 657system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles 658system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles 659system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles 660system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles 661system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles 662system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles |
| 625system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 626system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 627system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 628system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 629system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 630system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses | 663system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 664system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 665system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 666system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 667system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 668system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses |
| 631system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency 632system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency 633system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency 634system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency 635system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency 636system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency | 669system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency 670system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency 671system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 672system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency 673system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency 674system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency |
| 637system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 638system.cpu.l2cache.tags.replacements 0 # number of replacements | 675system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 676system.cpu.l2cache.tags.replacements 0 # number of replacements |
| 639system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use | 677system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use |
| 640system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 641system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 642system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 643system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 678system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 679system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 680system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 681system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 644system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor 645system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor | 682system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor 683system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor |
| 646system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy 647system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy | 684system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004995 # Average percentage of cache occupancy 685system.cpu.l2cache.tags.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy |
| 648system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy | 686system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy |
| 649system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 650system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 651system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 652system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 653system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses 654system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses 655system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 656system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 664system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 665system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 666system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 667system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 668system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 669system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 670system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 671system.cpu.l2cache.overall_misses::total 477 # number of overall misses | 687system.cpu.l2cache.tags.occ_task_id_blocks::1024 426 # Occupied blocks per task id 688system.cpu.l2cache.tags.age_task_id_blocks_1024::0 189 # Occupied blocks per task id 689system.cpu.l2cache.tags.age_task_id_blocks_1024::1 237 # Occupied blocks per task id 690system.cpu.l2cache.tags.occ_task_id_percent::1024 0.013000 # Percentage of cache occupancy per task id 691system.cpu.l2cache.tags.tag_accesses 4317 # Number of tag accesses 692system.cpu.l2cache.tags.data_accesses 4317 # Number of data accesses 693system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 694system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits --- 7 unchanged lines hidden (view full) --- 702system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 703system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 704system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 705system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 706system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 707system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 708system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 709system.cpu.l2cache.overall_misses::total 477 # number of overall misses |
| 672system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles 673system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles 674system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles 675system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles 676system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles 677system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles 678system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles 679system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles 680system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles 681system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles 682system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles | 710system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles 711system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles 712system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles 713system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles 714system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles 715system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles 716system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles 717system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles 718system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles 719system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles 720system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles |
| 683system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 684system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 685system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 686system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 687system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 688system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 689system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 690system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 697system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 698system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 699system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 700system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 701system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 702system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 703system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 704system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses | 721system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 722system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 723system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 724system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 725system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 726system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 727system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 728system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 735system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 736system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 737system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 738system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 739system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 740system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 741system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 742system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses |
| 705system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency 706system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency 707system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency 708system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency 709system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency 710system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency 711system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency 712system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency 713system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency 714system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency 715system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency | 743system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency 744system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency 745system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency 746system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency 747system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency 748system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 749system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 750system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency 751system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency 752system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency 753system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency |
| 716system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 717system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 718system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 719system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 720system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 721system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 722system.cpu.l2cache.fast_writes 0 # number of fast writes performed 723system.cpu.l2cache.cache_copies 0 # number of cache copies performed 724system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 725system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 726system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 727system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 728system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 729system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 730system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 731system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 732system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 733system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 734system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses | 754system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 755system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 756system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 757system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 758system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 759system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 760system.cpu.l2cache.fast_writes 0 # number of fast writes performed 761system.cpu.l2cache.cache_copies 0 # number of cache copies performed 762system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses 763system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 764system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses 765system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 766system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 767system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses 768system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 769system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses 770system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses 771system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 772system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses |
| 735system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles 736system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles 737system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles 738system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles 739system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles 740system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles 741system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles 742system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles 743system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles 744system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles 745system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles | 773system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles 774system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles 775system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles 776system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles 777system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles 778system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles 779system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles 780system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles 781system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles 782system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles 783system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles |
| 746system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 747system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 748system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 749system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 750system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 751system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 752system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 753system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 754system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 755system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 756system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses | 784system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses 785system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 786system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses 787system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 788system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 789system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses 790system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 791system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses 792system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses 793system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 794system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses |
| 757system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency 758system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency 759system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency 760system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency 761system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency 762system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency 763system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency 764system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency 765system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency 766system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency 767system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency | 795system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency 796system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency 797system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency 798system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency 799system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency 800system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 801system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 802system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency 803system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency 804system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency 805system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency |
| 768system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 769system.cpu.dcache.tags.replacements 0 # number of replacements | 806system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 807system.cpu.dcache.tags.replacements 0 # number of replacements |
| 770system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use | 808system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use |
| 771system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 772system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 773system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 774system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. | 809system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks. 810system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks. 811system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks. 812system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
| 775system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor 776system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy 777system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy | 813system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor 814system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy 815system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy |
| 778system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 779system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 780system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 781system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 782system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 783system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 784system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 785system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 792system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 793system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 794system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 795system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 796system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 797system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 798system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 799system.cpu.dcache.overall_misses::total 510 # number of overall misses | 816system.cpu.dcache.tags.occ_task_id_blocks::1024 142 # Occupied blocks per task id 817system.cpu.dcache.tags.age_task_id_blocks_1024::0 39 # Occupied blocks per task id 818system.cpu.dcache.tags.age_task_id_blocks_1024::1 103 # Occupied blocks per task id 819system.cpu.dcache.tags.occ_task_id_percent::1024 0.034668 # Percentage of cache occupancy per task id 820system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses 821system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses 822system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits 823system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits --- 6 unchanged lines hidden (view full) --- 830system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses 831system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses 832system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses 833system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses 834system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses 835system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses 836system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses 837system.cpu.dcache.overall_misses::total 510 # number of overall misses |
| 800system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles 801system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles 802system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles 803system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles 804system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles 805system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles 806system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles 807system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles | 838system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles 839system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles 840system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles 841system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles 842system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles 843system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles 844system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles 845system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles |
| 808system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 809system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 810system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 811system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 812system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 813system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 814system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 815system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 816system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 817system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 818system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 819system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 820system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 821system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 822system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 823system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses | 846system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses) 847system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses) 848system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses) 849system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses) 850system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses 851system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses 852system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses 853system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses 854system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses 855system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses 856system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses 857system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses 858system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses 859system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses 860system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses 861system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses |
| 824system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency 825system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency 826system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency 827system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency 828system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency 829system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency 830system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency 831system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency 832system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked | 862system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency 863system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency 864system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency 865system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency 866system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 867system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency 868system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency 869system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency 870system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked |
| 833system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 834system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 835system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked | 871system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked 872system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked 873system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked |
| 836system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked | 874system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked |
| 837system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 838system.cpu.dcache.fast_writes 0 # number of fast writes performed 839system.cpu.dcache.cache_copies 0 # number of cache copies performed 840system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 841system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 842system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 843system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 844system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 845system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 846system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 847system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 848system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 849system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 850system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 851system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 852system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 853system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 854system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 855system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses | 875system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 876system.cpu.dcache.fast_writes 0 # number of fast writes performed 877system.cpu.dcache.cache_copies 0 # number of cache copies performed 878system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits 879system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits 880system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits 881system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits 882system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits 883system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits 884system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits 885system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits 886system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses 887system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses 888system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses 889system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses 890system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 891system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses 892system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 893system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses |
| 856system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles 857system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles 858system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles 859system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles 860system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles 861system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles 862system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles 863system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles | 894system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles 895system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles 896system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles 897system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles 898system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles 899system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles 900system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles 901system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles |
| 864system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 865system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 866system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 867system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 868system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 869system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 870system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 871system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses | 902system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses 903system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses 904system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses 905system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses 906system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses 907system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses 908system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses 909system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses |
| 872system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency 873system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency 874system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency 875system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency 876system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency 877system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency 878system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency 879system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency | 910system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency 911system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency 912system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency 913system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency 914system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 915system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency 916system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency 917system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency |
| 880system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 881 882---------- End Simulation Statistics ---------- | 918system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate 919 920---------- End Simulation Statistics ---------- |