1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000022 # Number of seconds simulated 4sim_ticks 21898500 # Number of ticks simulated 5final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 34889 # Simulator instruction rate (inst/s) 8host_op_rate 34885 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 148144968 # Simulator tick rate (ticks/s) 10host_mem_usage 274956 # Number of bytes of host memory used 11host_seconds 0.15 # Real time elapsed on the host |
12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30528 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory --- 183 unchanged lines hidden (view full) --- 203system.membus.trans_dist::ReadExReq 51 # Transaction distribution 204system.membus.trans_dist::ReadExResp 51 # Transaction distribution 205system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes) 206system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes) 207system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes) 208system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes) 209system.membus.data_through_bus 30528 # Total data (bytes) 210system.membus.snoop_data_through_bus 0 # Total snoop data (bytes) |
211system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks) |
212system.membus.reqLayer0.utilization 2.8 # Layer utilization (%) |
213system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks) |
214system.membus.respLayer1.utilization 20.4 # Layer utilization (%) 215system.cpu.branchPred.lookups 2174 # Number of BP lookups 216system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted 217system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect 218system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups 219system.cpu.branchPred.BTBHits 492 # Number of BTB hits 220system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly. 221system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage --- 45 unchanged lines hidden (view full) --- 267system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total) 268system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total) 269system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total) 270system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total) 271system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total) 272system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total) 273system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle 274system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle |
275system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle |
276system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked |
277system.cpu.decode.RunCycles 3025 # Number of cycles decode is running |
278system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking 279system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing 280system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch 281system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction |
282system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode |
283system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode 284system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing |
285system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle |
286system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking 287system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst |
288system.cpu.rename.RunCycles 2898 # Number of cycles rename is running |
289system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking |
290system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename |
291system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full 292system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full 293system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full |
294system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed 295system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made 296system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups |
297system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups 298system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed |
299system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing |
300system.cpu.rename.serializingInsts 16 # count of serializing insts renamed 301system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed 302system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer 303system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit. 304system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit. 305system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads. 306system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores. 307system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec) --- 110 unchanged lines hidden (view full) --- 418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding 419system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled 420system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked 421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle 422system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing 423system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking 424system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking 425system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ |
426system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch |
427system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions 428system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions 429system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions 430system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall 431system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall 432system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations 433system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly 434system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly --- 98 unchanged lines hidden (view full) --- 533system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits 534system.cpu.icache.overall_hits::total 1514 # number of overall hits 535system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses 536system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses 537system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses 538system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses 539system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses 540system.cpu.icache.overall_misses::total 451 # number of overall misses |
541system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles 542system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles 543system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles 544system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles 545system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles 546system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles |
547system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses) 548system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses) 549system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses 550system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses 551system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses 552system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses 553system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses 554system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses 555system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses 556system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses 557system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses 558system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses |
559system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency 560system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency 561system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency 562system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency 563system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency 564system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency |
565system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked 566system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked 567system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked 568system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked 569system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked 570system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 571system.cpu.icache.fast_writes 0 # number of fast writes performed 572system.cpu.icache.cache_copies 0 # number of cache copies performed --- 4 unchanged lines hidden (view full) --- 577system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits 578system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits 579system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses 580system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses 581system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses 582system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses 583system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses 584system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses |
585system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles 586system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles 587system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles 588system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles 589system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles 590system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles |
591system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses 592system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses 593system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses 594system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses 595system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses 596system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses |
597system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency 598system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency 599system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency 600system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency 601system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency 602system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency |
603system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 604system.cpu.l2cache.tags.replacements 0 # number of replacements |
605system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use |
606system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks. 607system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks. 608system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks. 609system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
610system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor |
611system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor 612system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy 613system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy 614system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy 615system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 616system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 617system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 618system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits --- 5 unchanged lines hidden (view full) --- 624system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses 625system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses 626system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses 627system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses 628system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses 629system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses 630system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses 631system.cpu.l2cache.overall_misses::total 477 # number of overall misses |
632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles |
633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles |
634system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles |
635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles 636system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles |
637system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles |
638system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles |
639system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles 640system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles |
641system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles |
642system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles |
643system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses) 644system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses) 645system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses) 646system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses) 647system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses) 648system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses 649system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses 650system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses --- 6 unchanged lines hidden (view full) --- 657system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses 658system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses 659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses 660system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses 661system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses 662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses 663system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses 664system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses |
665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency |
666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency |
667system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency |
668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency 669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency |
670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency |
671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency |
672system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency 673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency |
674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency |
675system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency |
676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked 677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked 678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked 679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked 680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked 681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked 682system.cpu.l2cache.fast_writes 0 # number of fast writes performed 683system.cpu.l2cache.cache_copies 0 # number of cache copies performed --- 153 unchanged lines hidden --- |