1 2---------- Begin Simulation Statistics ---------- 3sim_seconds 0.000017 # Number of seconds simulated 4sim_ticks 17026500 # Number of ticks simulated 5final_tick 17026500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset) 6sim_freq 1000000000000 # Frequency of simulated ticks |
7host_inst_rate 44899 # Simulator instruction rate (inst/s) 8host_op_rate 44889 # Simulator op (including micro ops) rate (op/s) 9host_tick_rate 148205995 # Simulator tick rate (ticks/s) 10host_mem_usage 226388 # Number of bytes of host memory used 11host_seconds 0.12 # Real time elapsed on the host |
12sim_insts 5156 # Number of instructions simulated 13sim_ops 5156 # Number of ops (including micro ops) simulated 14system.physmem.bytes_read::cpu.inst 21504 # Number of bytes read from this memory 15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory 16system.physmem.bytes_read::total 30592 # Number of bytes read from this memory 17system.physmem.bytes_inst_read::cpu.inst 21504 # Number of instructions bytes read from this memory 18system.physmem.bytes_inst_read::total 21504 # Number of instructions bytes read from this memory 19system.physmem.num_reads::cpu.inst 336 # Number of read requests responded to by this memory --- 53 unchanged lines hidden (view full) --- 73system.physmem.totGap 16967000 # Total gap between requests 74system.physmem.readPktSize::0 0 # Categorize read packet sizes 75system.physmem.readPktSize::1 0 # Categorize read packet sizes 76system.physmem.readPktSize::2 0 # Categorize read packet sizes 77system.physmem.readPktSize::3 0 # Categorize read packet sizes 78system.physmem.readPktSize::4 0 # Categorize read packet sizes 79system.physmem.readPktSize::5 0 # Categorize read packet sizes 80system.physmem.readPktSize::6 478 # Categorize read packet sizes |
81system.physmem.writePktSize::0 0 # Categorize write packet sizes 82system.physmem.writePktSize::1 0 # Categorize write packet sizes 83system.physmem.writePktSize::2 0 # Categorize write packet sizes 84system.physmem.writePktSize::3 0 # Categorize write packet sizes 85system.physmem.writePktSize::4 0 # Categorize write packet sizes 86system.physmem.writePktSize::5 0 # Categorize write packet sizes 87system.physmem.writePktSize::6 0 # Categorize write packet sizes |
88system.physmem.rdQLenPdf::0 253 # What read queue length does an incoming req see 89system.physmem.rdQLenPdf::1 152 # What read queue length does an incoming req see 90system.physmem.rdQLenPdf::2 48 # What read queue length does an incoming req see 91system.physmem.rdQLenPdf::3 19 # What read queue length does an incoming req see 92system.physmem.rdQLenPdf::4 6 # What read queue length does an incoming req see 93system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see 94system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see 95system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 112system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see 113system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see 114system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see 115system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see 116system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see 117system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see 118system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see 119system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see |
120system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see 121system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see 122system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see 123system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see 124system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see 125system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see 126system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see 127system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see --- 16 unchanged lines hidden (view full) --- 144system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see 145system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see 146system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see 147system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see 148system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see 149system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see 150system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see 151system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see |
152system.physmem.totQLat 2863000 # Total cycles spent in queuing delays 153system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests |
154system.physmem.totBusLat 2390000 # Total cycles spent in databus access 155system.physmem.totBankLat 9363750 # Total cycles spent in bank access |
156system.physmem.avgQLat 5989.54 # Average queueing delay per request |
157system.physmem.avgBankLat 19589.44 # Average bank access latency per request 158system.physmem.avgBusLat 5000.00 # Average bus latency per request |
159system.physmem.avgMemAccLat 30578.97 # Average memory access latency |
160system.physmem.avgRdBW 1796.73 # Average achieved read bandwidth in MB/s 161system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MB/s 162system.physmem.avgConsumedRdBW 1796.73 # Average consumed read bandwidth in MB/s 163system.physmem.avgConsumedWrBW 0.00 # Average consumed write bandwidth in MB/s 164system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MB/s 165system.physmem.busUtil 14.04 # Data bus utilization in percentage 166system.physmem.avgRdQLen 0.86 # Average read queue length over time 167system.physmem.avgWrQLen 0.00 # Average write queue length over time --- 368 unchanged lines hidden (view full) --- 536system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 52572.271386 # average ReadReq mshr miss latency 537system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 52572.271386 # average ReadReq mshr miss latency 538system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency 539system.cpu.icache.demand_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency 540system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 52572.271386 # average overall mshr miss latency 541system.cpu.icache.overall_avg_mshr_miss_latency::total 52572.271386 # average overall mshr miss latency 542system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate 543system.cpu.l2cache.replacements 0 # number of replacements |
544system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use |
545system.cpu.l2cache.total_refs 3 # Total number of references to valid blocks. 546system.cpu.l2cache.sampled_refs 427 # Sample count of references to valid blocks. 547system.cpu.l2cache.avg_refs 0.007026 # Average number of references to valid blocks. 548system.cpu.l2cache.warmup_cycle 0 # Cycle when the warmup percentage was hit. |
549system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor 550system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor |
551system.cpu.l2cache.occ_percent::cpu.inst 0.005024 # Average percentage of cache occupancy 552system.cpu.l2cache.occ_percent::cpu.data 0.001764 # Average percentage of cache occupancy 553system.cpu.l2cache.occ_percent::total 0.006788 # Average percentage of cache occupancy 554system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits 555system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits 556system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits 557system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits 558system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits --- 67 unchanged lines hidden (view full) --- 626system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses 627system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses 628system.cpu.l2cache.demand_mshr_misses::cpu.inst 336 # number of demand (read+write) MSHR misses 629system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses 630system.cpu.l2cache.demand_mshr_misses::total 478 # number of demand (read+write) MSHR misses 631system.cpu.l2cache.overall_mshr_misses::cpu.inst 336 # number of overall MSHR misses 632system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses 633system.cpu.l2cache.overall_mshr_misses::total 478 # number of overall MSHR misses |
634system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles 635system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles 636system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles 637system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles 638system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles 639system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles 640system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles 641system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles 642system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles 643system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles 644system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles |
645system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for ReadReq accesses 646system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses 647system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993023 # mshr miss rate for ReadReq accesses 648system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses 649system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses 650system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for demand accesses 651system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses 652system.cpu.l2cache.demand_mshr_miss_rate::total 0.993763 # mshr miss rate for demand accesses 653system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991150 # mshr miss rate for overall accesses 654system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses 655system.cpu.l2cache.overall_mshr_miss_rate::total 0.993763 # mshr miss rate for overall accesses |
656system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency 657system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency 658system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency 659system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency 660system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency 661system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency 662system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency 663system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency 664system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency 665system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency 666system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency |
667system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate 668system.cpu.dcache.replacements 0 # number of replacements 669system.cpu.dcache.tagsinuse 91.642501 # Cycle average of tags in use 670system.cpu.dcache.total_refs 2424 # Total number of references to valid blocks. 671system.cpu.dcache.sampled_refs 142 # Sample count of references to valid blocks. 672system.cpu.dcache.avg_refs 17.070423 # Average number of references to valid blocks. 673system.cpu.dcache.warmup_cycle 0 # Cycle when the warmup percentage was hit. 674system.cpu.dcache.occ_blocks::cpu.data 91.642501 # Average occupied blocks per requestor --- 101 unchanged lines hidden --- |