7,11c7,11
< host_inst_rate 64871 # Simulator instruction rate (inst/s)
< host_op_rate 64859 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 275425114 # Simulator tick rate (ticks/s)
< host_mem_usage 255508 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 34889 # Simulator instruction rate (inst/s)
> host_op_rate 34885 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 148144968 # Simulator tick rate (ticks/s)
> host_mem_usage 274956 # Number of bytes of host memory used
> host_seconds 0.15 # Real time elapsed on the host
211c211
< system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
213c213
< system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks)
275c275
< system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle
277c277
< system.cpu.decode.RunCycles 3026 # Number of cycles decode is running
---
> system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
282c282
< system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
285c285
< system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle
288c288
< system.cpu.rename.RunCycles 2899 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
290c290
< system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
294,296c294,296
< system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
299c299
< system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
426c426
< system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
541,546c541,546
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles
559,564c559,564
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency
585,590c585,590
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles
597,602c597,602
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
605c605
< system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use
610c610
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor
632c632
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles
634c634
< system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles
637c637
< system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles
639,640c639,640
< system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles
642c642
< system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles
665c665
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency
667c667
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency
670c670
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
672,673c672,673
< system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
675c675
< system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency
< host_inst_rate 64871 # Simulator instruction rate (inst/s)
< host_op_rate 64859 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 275425114 # Simulator tick rate (ticks/s)
< host_mem_usage 255508 # Number of bytes of host memory used
< host_seconds 0.08 # Real time elapsed on the host
---
> host_inst_rate 34889 # Simulator instruction rate (inst/s)
> host_op_rate 34885 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 148144968 # Simulator tick rate (ticks/s)
> host_mem_usage 274956 # Number of bytes of host memory used
> host_seconds 0.15 # Real time elapsed on the host
211c211
< system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
213c213
< system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4474750 # Layer occupancy (ticks)
275c275
< system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle
---
> system.cpu.decode.IdleCycles 8890 # Number of cycles decode is idle
277c277
< system.cpu.decode.RunCycles 3026 # Number of cycles decode is running
---
> system.cpu.decode.RunCycles 3025 # Number of cycles decode is running
282c282
< system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12292 # Number of instructions handled by decode
285c285
< system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle
---
> system.cpu.rename.IdleCycles 9072 # Number of cycles rename is idle
288c288
< system.cpu.rename.RunCycles 2899 # Number of cycles rename is running
---
> system.cpu.rename.RunCycles 2898 # Number of cycles rename is running
290c290
< system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename
---
> system.cpu.rename.RenamedInsts 11862 # Number of instructions processed by rename
294,296c294,296
< system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups
---
> system.cpu.rename.RenamedOperands 7176 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 14099 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13870 # Number of integer rename lookups
299c299
< system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3778 # Number of HB maps that are undone due to squashing
426c426
< system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch
---
> system.cpu.iew.iewDispSquashedInsts 85 # Number of squashed instructions skipped by dispatch
541,546c541,546
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31196500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31196500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31196500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31196500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31196500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31196500 # number of overall miss cycles
559,564c559,564
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69171.840355 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69171.840355 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69171.840355 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69171.840355 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69171.840355 # average overall miss latency
585,590c585,590
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24201750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24201750 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24201750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24201750 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24201750 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24201750 # number of overall MSHR miss cycles
597,602c597,602
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71602.810651 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71602.810651 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71602.810651 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71602.810651 # average overall mshr miss latency
605c605
< system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.801023 # Cycle average of tags in use
610c610
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923735 # Average occupied blocks per requestor
632c632
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23833750 # number of ReadReq miss cycles
634c634
< system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::total 30860500 # number of ReadReq miss cycles
637c637
< system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles
---
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23833750 # number of demand (read+write) miss cycles
639,640c639,640
< system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles
---
> system.cpu.l2cache.demand_miss_latency::total 34674750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23833750 # number of overall miss cycles
642c642
< system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles
---
> system.cpu.l2cache.overall_miss_latency::total 34674750 # number of overall miss cycles
665c665
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71145.522388 # average ReadReq miss latency
667c667
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72442.488263 # average ReadReq miss latency
670c670
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
672,673c672,673
< system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
---
> system.cpu.l2cache.demand_avg_miss_latency::total 72693.396226 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71145.522388 # average overall miss latency
675c675
< system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency
---
> system.cpu.l2cache.overall_avg_miss_latency::total 72693.396226 # average overall miss latency