7,11c7,11
< host_inst_rate 76348 # Simulator instruction rate (inst/s)
< host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 251939378 # Simulator tick rate (ticks/s)
< host_mem_usage 226380 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 44899 # Simulator instruction rate (inst/s)
> host_op_rate 44889 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 148205995 # Simulator tick rate (ticks/s)
> host_mem_usage 226388 # Number of bytes of host memory used
> host_seconds 0.12 # Real time elapsed on the host
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 2863474 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2863000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 5990.53 # Average queueing delay per request
---
> system.physmem.avgQLat 5989.54 # Average queueing delay per request
174c159
< system.physmem.avgMemAccLat 30579.97 # Average memory access latency
---
> system.physmem.avgMemAccLat 30578.97 # Average memory access latency
559c544
< system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use
564,565c549,550
< system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor
649,659c634,644
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles
671,681c656,666
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
< host_inst_rate 76348 # Simulator instruction rate (inst/s)
< host_op_rate 76319 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 251939378 # Simulator tick rate (ticks/s)
< host_mem_usage 226380 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 44899 # Simulator instruction rate (inst/s)
> host_op_rate 44889 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 148205995 # Simulator tick rate (ticks/s)
> host_mem_usage 226388 # Number of bytes of host memory used
> host_seconds 0.12 # Real time elapsed on the host
81,100c81,87
< system.physmem.readPktSize::7 0 # Categorize read packet sizes
< system.physmem.readPktSize::8 0 # Categorize read packet sizes
< system.physmem.writePktSize::0 0 # categorize write packet sizes
< system.physmem.writePktSize::1 0 # categorize write packet sizes
< system.physmem.writePktSize::2 0 # categorize write packet sizes
< system.physmem.writePktSize::3 0 # categorize write packet sizes
< system.physmem.writePktSize::4 0 # categorize write packet sizes
< system.physmem.writePktSize::5 0 # categorize write packet sizes
< system.physmem.writePktSize::6 0 # categorize write packet sizes
< system.physmem.writePktSize::7 0 # categorize write packet sizes
< system.physmem.writePktSize::8 0 # categorize write packet sizes
< system.physmem.neitherpktsize::0 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::1 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::2 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::3 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::4 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::5 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::6 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::7 0 # categorize neither packet sizes
< system.physmem.neitherpktsize::8 0 # categorize neither packet sizes
---
> system.physmem.writePktSize::0 0 # Categorize write packet sizes
> system.physmem.writePktSize::1 0 # Categorize write packet sizes
> system.physmem.writePktSize::2 0 # Categorize write packet sizes
> system.physmem.writePktSize::3 0 # Categorize write packet sizes
> system.physmem.writePktSize::4 0 # Categorize write packet sizes
> system.physmem.writePktSize::5 0 # Categorize write packet sizes
> system.physmem.writePktSize::6 0 # Categorize write packet sizes
133d119
< system.physmem.rdQLenPdf::32 0 # What read queue length does an incoming req see
166,168c152,153
< system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
< system.physmem.totQLat 2863474 # Total cycles spent in queuing delays
< system.physmem.totMemAccLat 14617224 # Sum of mem lat for all requests
---
> system.physmem.totQLat 2863000 # Total cycles spent in queuing delays
> system.physmem.totMemAccLat 14616750 # Sum of mem lat for all requests
171c156
< system.physmem.avgQLat 5990.53 # Average queueing delay per request
---
> system.physmem.avgQLat 5989.54 # Average queueing delay per request
174c159
< system.physmem.avgMemAccLat 30579.97 # Average memory access latency
---
> system.physmem.avgMemAccLat 30578.97 # Average memory access latency
559c544
< system.cpu.l2cache.tagsinuse 222.426618 # Cycle average of tags in use
---
> system.cpu.l2cache.tagsinuse 222.426637 # Cycle average of tags in use
564,565c549,550
< system.cpu.l2cache.occ_blocks::cpu.inst 164.638321 # Average occupied blocks per requestor
< system.cpu.l2cache.occ_blocks::cpu.data 57.788297 # Average occupied blocks per requestor
---
> system.cpu.l2cache.occ_blocks::cpu.inst 164.638337 # Average occupied blocks per requestor
> system.cpu.l2cache.occ_blocks::cpu.data 57.788300 # Average occupied blocks per requestor
649,659c634,644
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273303 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804087 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077390 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032056 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032056 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273303 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836143 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 20109446 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273303 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836143 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 20109446 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 13273027 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 4804044 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 18077071 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 2032028 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 2032028 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 13273027 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 6836072 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 20109099 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 13273027 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 6836072 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 20109099 # number of overall MSHR miss cycles
671,681c656,666
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.877976 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52792.164835 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.807963 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39844.235294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39844.235294 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.877976 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.852113 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.970711 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 39503.056548 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 52791.692308 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 42335.060890 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 39843.686275 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 39843.686275 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 39503.056548 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 48141.352113 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 42069.244770 # average overall mshr miss latency