7,11c7,11
< host_inst_rate 56172 # Simulator instruction rate (inst/s)
< host_op_rate 56163 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 137660070 # Simulator tick rate (ticks/s)
< host_mem_usage 215596 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 63611 # Simulator instruction rate (inst/s)
> host_op_rate 63597 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 155871053 # Simulator tick rate (ticks/s)
> host_mem_usage 216124 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 30912 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 483 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
> system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s)
342a350
> system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses
343a352
> system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses
344a354
> system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses
345a356
> system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency
346a358
> system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency
347a360
> system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency
374a388
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses
375a390
> system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses
376a392
> system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses
377a394
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency
378a396
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency
379a398
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency
422a442
> system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses
423a444
> system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses
424a446
> system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses
425a448
> system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses
426a450
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency
427a452
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency
428a454
> system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency
429a456
> system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency
462a490
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses
463a492
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
464a494
> system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses
465a496
> system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses
466a498
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency
467a500
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency
468a502
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency
469a504
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency
522a558
> system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses
523a560
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
525a563
> system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses
527a566
> system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses
529a569
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency
530a571
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency
532a574
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency
534a577
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency
566a610
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses
567a612
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
569a615
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses
571a618
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses
573a621
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency
574a623
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency
576a626
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency
578a629
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency
< host_inst_rate 56172 # Simulator instruction rate (inst/s)
< host_op_rate 56163 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 137660070 # Simulator tick rate (ticks/s)
< host_mem_usage 215596 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 63611 # Simulator instruction rate (inst/s)
> host_op_rate 63597 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 155871053 # Simulator tick rate (ticks/s)
> host_mem_usage 216124 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
14,22c14,29
< system.physmem.bytes_read 30912 # Number of bytes read from this memory
< system.physmem.bytes_inst_read 21824 # Number of instructions bytes read from this memory
< system.physmem.bytes_written 0 # Number of bytes written to this memory
< system.physmem.num_reads 483 # Number of read requests responded to by this memory
< system.physmem.num_writes 0 # Number of write requests responded to by this memory
< system.physmem.num_other 0 # Number of other requests responded to by this memory
< system.physmem.bw_read 2439490195 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read 1722290179 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total 2439490195 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bytes_read::cpu.inst 21824 # Number of bytes read from this memory
> system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
> system.physmem.bytes_read::total 30912 # Number of bytes read from this memory
> system.physmem.bytes_inst_read::cpu.inst 21824 # Number of instructions bytes read from this memory
> system.physmem.bytes_inst_read::total 21824 # Number of instructions bytes read from this memory
> system.physmem.num_reads::cpu.inst 341 # Number of read requests responded to by this memory
> system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
> system.physmem.num_reads::total 483 # Number of read requests responded to by this memory
> system.physmem.bw_read::cpu.inst 1722290179 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 717200016 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 2439490195 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 1722290179 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 1722290179 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 1722290179 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 717200016 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 2439490195 # Total bandwidth to/from this memory (bytes/s)
342a350
> system.cpu.icache.ReadReq_miss_rate::total 0.219225 # miss rate for ReadReq accesses
343a352
> system.cpu.icache.demand_miss_rate::total 0.219225 # miss rate for demand accesses
344a354
> system.cpu.icache.overall_miss_rate::total 0.219225 # miss rate for overall accesses
345a356
> system.cpu.icache.ReadReq_avg_miss_latency::total 35591.722595 # average ReadReq miss latency
346a358
> system.cpu.icache.demand_avg_miss_latency::total 35591.722595 # average overall miss latency
347a360
> system.cpu.icache.overall_avg_miss_latency::total 35591.722595 # average overall miss latency
374a388
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.168710 # mshr miss rate for ReadReq accesses
375a390
> system.cpu.icache.demand_mshr_miss_rate::total 0.168710 # mshr miss rate for demand accesses
376a392
> system.cpu.icache.overall_mshr_miss_rate::total 0.168710 # mshr miss rate for overall accesses
377a394
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 35072.674419 # average ReadReq mshr miss latency
378a396
> system.cpu.icache.demand_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency
379a398
> system.cpu.icache.overall_avg_mshr_miss_latency::total 35072.674419 # average overall mshr miss latency
422a442
> system.cpu.dcache.ReadReq_miss_rate::total 0.065874 # miss rate for ReadReq accesses
423a444
> system.cpu.dcache.WriteReq_miss_rate::total 0.366486 # miss rate for WriteReq accesses
424a446
> system.cpu.dcache.demand_miss_rate::total 0.160326 # miss rate for demand accesses
425a448
> system.cpu.dcache.overall_miss_rate::total 0.160326 # miss rate for overall accesses
426a450
> system.cpu.dcache.ReadReq_avg_miss_latency::total 36289.473684 # average ReadReq miss latency
427a452
> system.cpu.dcache.WriteReq_avg_miss_latency::total 33609.144543 # average WriteReq miss latency
428a454
> system.cpu.dcache.demand_avg_miss_latency::total 34364.406780 # average overall miss latency
429a456
> system.cpu.dcache.overall_avg_miss_latency::total 34364.406780 # average overall miss latency
462a490
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045072 # mshr miss rate for ReadReq accesses
463a492
> system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
464a494
> system.cpu.dcache.demand_mshr_miss_rate::total 0.048234 # mshr miss rate for demand accesses
465a496
> system.cpu.dcache.overall_mshr_miss_rate::total 0.048234 # mshr miss rate for overall accesses
466a498
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 35906.593407 # average ReadReq mshr miss latency
467a500
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 36186.274510 # average WriteReq mshr miss latency
468a502
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency
469a504
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 36007.042254 # average overall mshr miss latency
522a558
> system.cpu.l2cache.ReadReq_miss_rate::total 0.993103 # miss rate for ReadReq accesses
523a560
> system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
525a563
> system.cpu.l2cache.demand_miss_rate::total 0.993827 # miss rate for demand accesses
527a566
> system.cpu.l2cache.overall_miss_rate::total 0.993827 # miss rate for overall accesses
529a569
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 34335.648148 # average ReadReq miss latency
530a571
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 34686.274510 # average ReadExReq miss latency
532a574
> system.cpu.l2cache.demand_avg_miss_latency::total 34372.670807 # average overall miss latency
534a577
> system.cpu.l2cache.overall_avg_miss_latency::total 34372.670807 # average overall miss latency
566a610
> system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993103 # mshr miss rate for ReadReq accesses
567a612
> system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
569a615
> system.cpu.l2cache.demand_mshr_miss_rate::total 0.993827 # mshr miss rate for demand accesses
571a618
> system.cpu.l2cache.overall_mshr_miss_rate::total 0.993827 # mshr miss rate for overall accesses
573a621
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 31130.787037 # average ReadReq mshr miss latency
574a623
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 31450.980392 # average ReadExReq mshr miss latency
576a626
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency
578a629
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 31164.596273 # average overall mshr miss latency