7,11c7,11
< host_inst_rate 123007 # Simulator instruction rate (inst/s)
< host_op_rate 122970 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 600170719 # Simulator tick rate (ticks/s)
< host_mem_usage 251144 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 38911 # Simulator instruction rate (inst/s)
> host_op_rate 38904 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 189891987 # Simulator tick rate (ticks/s)
> host_mem_usage 234100 # Number of bytes of host memory used
> host_seconds 0.13 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 7578250 # Total ticks spent queuing
< system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 7577250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst
232c232
< system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ)
---
> system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
234c234
< system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states
302c302
< system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss
311,313c311,313
< system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total)
315c315
< system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total)
327c327
< system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total)
331c331
< system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked
341c341
< system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking
359,360c359,360
< system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
363c363
< system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec)
365c365
< system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued
367,368c367,368
< system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph
370,372c370,372
< system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle
374,377c374,377
< system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle
386c386
< system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle
426,457c426,457
< system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued
463,464c463,464
< system.cpu.iq.FU_type_0::total 8119 # Type of FU issued
< system.cpu.iq.rate 0.166335 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8118 # Type of FU issued
> system.cpu.iq.rate 0.166315 # Inst issue rate
466,469c466,469
< system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses
473c473
< system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses
477c477
< system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed
480c480
< system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
487c487
< system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
489c489
< system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ
491,492c491,492
< system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
500,502c500,502
< system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute
504,506c504,506
< system.cpu.iew.exec_nop 1599 # number of nop insts executed
< system.cpu.iew.exec_refs 3179 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1364 # Number of branches executed
---
> system.cpu.iew.exec_nop 1596 # number of nop insts executed
> system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1363 # Number of branches executed
508,510c508,510
< system.cpu.iew.exec_rate 0.159636 # Inst execution rate
< system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7340 # cumulative count of insts written-back
---
> system.cpu.iew.exec_rate 0.159595 # Inst execution rate
> system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7339 # cumulative count of insts written-back
512,515c512,515
< system.cpu.iew.wb_consumers 4275 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_consumers 4274 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit
585,586c585,586
< system.cpu.rob.rob_reads 24808 # The number of ROB reads
< system.cpu.rob.rob_writes 22150 # The number of ROB writes
---
> system.cpu.rob.rob_reads 24800 # The number of ROB reads
> system.cpu.rob.rob_writes 22133 # The number of ROB writes
588c588
< system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling
595c595
< system.cpu.int_regfile_reads 10563 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 10560 # number of integer regfile reads
602,603c602,603
< system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
605c605
< system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
607c607
< system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor
614,615c614,615
< system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
617,618c617,618
< system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits
621,624c621,624
< system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits
< system.cpu.dcache.overall_hits::total 2396 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
> system.cpu.dcache.overall_hits::total 2395 # number of overall hits
633,634c633,634
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles
637,642c637,642
< system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses)
645,650c645,650
< system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses
653,658c653,658
< system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency
661,664c661,664
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency
687,688c687,688
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles
691,696c691,696
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses
699,704c699,704
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency
707,710c707,710
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
784,789c784,789
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles
796,801c796,801
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
804c804
< system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use
810c810
< system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor
843,852c843,852
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles
881,890c881,890
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency
911,920c911,920
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles
935,944c935,944
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
1010c1010
< system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks)
< host_inst_rate 123007 # Simulator instruction rate (inst/s)
< host_op_rate 122970 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 600170719 # Simulator tick rate (ticks/s)
< host_mem_usage 251144 # Number of bytes of host memory used
< host_seconds 0.04 # Real time elapsed on the host
---
> host_inst_rate 38911 # Simulator instruction rate (inst/s)
> host_op_rate 38904 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 189891987 # Simulator tick rate (ticks/s)
> host_mem_usage 234100 # Number of bytes of host memory used
> host_seconds 0.13 # Real time elapsed on the host
204,205c204,205
< system.physmem.totQLat 7578250 # Total ticks spent queuing
< system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 7577250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16371000 # Total ticks spent from burst creation until serviced by the DRAM
207c207
< system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16156.18 # Average queueing delay per DRAM burst
209c209
< system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 34906.18 # Average memory access latency per DRAM burst
232c232
< system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ)
---
> system.physmem_0.preBackEnergy 46560 # Energy for precharge background per rank (pJ)
234c234
< system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ)
---
> system.physmem_0.prePowerDownEnergy 952800 # Energy for precharge power-down per rank (pJ)
242c242
< system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states
---
> system.physmem_0.memoryStateTime::PRE_PDN 2481250 # Time in different power states
244c244
< system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT_PDN 18291500 # Time in different power states
302c302
< system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss
---
> system.cpu.fetch.icacheStallCycles 9088 # Number of cycles fetch is stalled on an Icache miss
311,313c311,313
< system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15174 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856795 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.144946 # Number of instructions fetched each cycle (Total)
315c315
< system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11814 77.86% 77.86% # Number of instructions fetched each cycle (Total)
327c327
< system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::total 15174 # Number of instructions fetched each cycle (Total)
331c331
< system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 3450 # Number of cycles decode is blocked
341c341
< system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking
---
> system.cpu.rename.BlockCycles 620 # Number of cycles rename is blocking
359,360c359,360
< system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 2468 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
363c363
< system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 9014 # Number of instructions added to the IQ (excludes non-spec)
365c365
< system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8118 # Number of instructions issued
367,368c367,368
< system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4025 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2012 # Number of squashed operands that are examined and possibly removed from graph
370,372c370,372
< system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 15174 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.534994 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.265800 # Number of insts issued each cycle
374,377c374,377
< system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11850 78.09% 78.09% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1336 8.80% 86.90% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 728 4.80% 91.70% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 453 2.99% 94.68% # Number of insts issued each cycle
386c386
< system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15174 # Number of insts issued each cycle
426,457c426,457
< system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4775 58.82% 58.82% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.87% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.88% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.91% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2273 28.00% 86.91% # Type of FU issued
463,464c463,464
< system.cpu.iq.FU_type_0::total 8119 # Type of FU issued
< system.cpu.iq.rate 0.166335 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8118 # Type of FU issued
> system.cpu.iq.rate 0.166315 # Inst issue rate
466,469c466,469
< system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.022173 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31605 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 13057 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7337 # Number of integer instruction queue wakeup accesses
473c473
< system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8296 # Number of integer alu accesses
477c477
< system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1333 # Number of loads squashed
480c480
< system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
487c487
< system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking
---
> system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
489c489
< system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ
---
> system.cpu.iew.iewDispatchedInsts 10621 # Number of instructions dispatched to IQ
491,492c491,492
< system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions
---
> system.cpu.iew.iewDispLoadInsts 2468 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
500,502c500,502
< system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecutedInsts 7790 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2129 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 328 # Number of squashed instructions skipped in execute
504,506c504,506
< system.cpu.iew.exec_nop 1599 # number of nop insts executed
< system.cpu.iew.exec_refs 3179 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1364 # Number of branches executed
---
> system.cpu.iew.exec_nop 1596 # number of nop insts executed
> system.cpu.iew.exec_refs 3178 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1363 # Number of branches executed
508,510c508,510
< system.cpu.iew.exec_rate 0.159636 # Inst execution rate
< system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7340 # cumulative count of insts written-back
---
> system.cpu.iew.exec_rate 0.159595 # Inst execution rate
> system.cpu.iew.wb_sent 7432 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7339 # cumulative count of insts written-back
512,515c512,515
< system.cpu.iew.wb_consumers 4275 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_consumers 4274 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.150355 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.670800 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4982 # The number of squashed insts skipped by commit
585,586c585,586
< system.cpu.rob.rob_reads 24808 # The number of ROB reads
< system.cpu.rob.rob_writes 22150 # The number of ROB writes
---
> system.cpu.rob.rob_reads 24800 # The number of ROB reads
> system.cpu.rob.rob_writes 22133 # The number of ROB writes
588c588
< system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 33637 # Total number of cycles that the CPU has spent unscheduled due to idling
595c595
< system.cpu.int_regfile_reads 10563 # number of integer regfile reads
---
> system.cpu.int_regfile_reads 10560 # number of integer regfile reads
602,603c602,603
< system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 91.114159 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
605c605
< system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
607c607
< system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 91.114159 # Average occupied blocks per requestor
614,615c614,615
< system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses
---
> system.cpu.dcache.tags.tag_accesses 5952 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5952 # Number of data accesses
617,618c617,618
< system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits
---
> system.cpu.dcache.ReadReq_hits::cpu.data 1838 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1838 # number of ReadReq hits
621,624c621,624
< system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits
< system.cpu.dcache.overall_hits::total 2396 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
> system.cpu.dcache.overall_hits::total 2395 # number of overall hits
633,634c633,634
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12709500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12709500 # number of ReadReq miss cycles
637,642c637,642
< system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.demand_miss_latency::cpu.data 46928999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 46928999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 46928999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 46928999 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2005 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2005 # number of ReadReq accesses(hits+misses)
645,650c645,650
< system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2906 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2906 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2906 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2906 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083292 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.083292 # miss rate for ReadReq accesses
653,658c653,658
< system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.175843 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.175843 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.175843 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.175843 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76104.790419 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 76104.790419 # average ReadReq miss latency
661,664c661,664
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency
---
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91837.571429 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91837.571429 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91837.571429 # average overall miss latency
687,688c687,688
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8094500 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8094500 # number of ReadReq MSHR miss cycles
691,696c691,696
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13010499 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010499 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13010499 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044888 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044888 # mshr miss rate for ReadReq accesses
699,704c699,704
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.048176 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048176 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.048176 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89938.888889 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89938.888889 # average ReadReq mshr miss latency
707,710c707,710
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
---
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92932.135714 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 92932.135714 # average overall mshr miss latency
784,789c784,789
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28112000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28112000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28112000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28112000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28112000 # number of overall MSHR miss cycles
796,801c796,801
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84674.698795 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84674.698795 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84674.698795 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84674.698795 # average overall mshr miss latency
804c804
< system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 253.317649 # Cycle average of tags in use
810c810
< system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174392 # Average occupied blocks per requestor
843,852c843,852
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27581000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27581000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7956500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7956500 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27581000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12796500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40377500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27581000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12796500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40377500 # number of overall miss cycles
881,890c881,890
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83832.826748 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83832.826748 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88405.555556 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88405.555556 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86092.750533 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83832.826748 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91403.571429 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86092.750533 # average overall miss latency
911,920c911,920
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24291000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24291000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7056500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7056500 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24291000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11396500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 35687500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24291000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11396500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 35687500 # number of overall MSHR miss cycles
935,944c935,944
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73832.826748 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73832.826748 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78405.555556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78405.555556 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73832.826748 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81403.571429 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76092.750533 # average overall mshr miss latency
1010c1010
< system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 581000 # Layer occupancy (ticks)