3,5c3,5
< sim_seconds 0.000023 # Number of seconds simulated
< sim_ticks 22838000 # Number of ticks simulated
< final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_seconds 0.000024 # Number of seconds simulated
> sim_ticks 24405000 # Number of ticks simulated
> final_tick 24405000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 76246 # Simulator instruction rate (inst/s)
< host_op_rate 76230 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 348191953 # Simulator tick rate (ticks/s)
< host_mem_usage 252304 # Number of bytes of host memory used
< host_seconds 0.07 # Real time elapsed on the host
---
> host_inst_rate 101939 # Simulator instruction rate (inst/s)
> host_op_rate 101907 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 497362491 # Simulator tick rate (ticks/s)
> host_mem_usage 250452 # Number of bytes of host memory used
> host_seconds 0.05 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 862774022 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 367137882 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1229911903 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 862774022 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 862774022 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 862774022 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 367137882 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1229911903 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 22751500 # Total gap between requests
---
> system.physmem.totGap 24305500 # Total gap between requests
94,96c94,96
< system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 270 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::2 40 # What read queue length does an incoming req see
98c98
< system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::4 7 # What read queue length does an incoming req see
190,204c190,205
< system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation
< system.physmem.totQLat 4619250 # Total ticks spent queuing
< system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 114 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 261.614035 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 175.762153 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 255.654479 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 36 31.58% 31.58% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 34 29.82% 61.40% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 19 16.67% 78.07% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 7.02% 85.09% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 3.51% 88.60% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 1.75% 90.35% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 4 3.51% 93.86% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 3 2.63% 96.49% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 4 3.51% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 114 # Bytes accessed per row activation
> system.physmem.totQLat 7578250 # Total ticks spent queuing
> system.physmem.totMemAccLat 16372000 # Total ticks spent from burst creation until serviced by the DRAM
206c207
< system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 16158.32 # Average queueing delay per DRAM burst
208,209c209,210
< system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 34908.32 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1229.91 # Average DRAM read bandwidth in MiByte/s
211c212
< system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1229.91 # Average system read bandwidth in MiByte/s
214,215c215,216
< system.physmem.busUtil 10.27 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 9.61 # Data bus utilization in percentage
> system.physmem.busUtilRead 9.61 # Data bus utilization in percentage for reads
217c218
< system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
---
> system.physmem.avgRdQLen 1.76 # Average read queue length when enqueuing
219c220
< system.physmem.readRowHits 353 # Number of row buffer hits during reads
---
> system.physmem.readRowHits 352 # Number of row buffer hits during reads
221c222
< system.physmem.readRowHitRate 75.27 # Row buffer hit rate for reads
---
> system.physmem.readRowHitRate 75.05 # Row buffer hit rate for reads
223,227c224,228
< system.physmem.avgGap 48510.66 # Average gap between requests
< system.physmem.pageHitRate 75.27 # Row buffer hit rate, read and write combined
< system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
< system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
< system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ)
---
> system.physmem.avgGap 51824.09 # Average gap between requests
> system.physmem.pageHitRate 75.05 # Row buffer hit rate, read and write combined
> system.physmem_0.actEnergy 192780 # Energy for activate commands per rank (pJ)
> system.physmem_0.preEnergy 98670 # Energy for precharge commands per rank (pJ)
> system.physmem_0.readEnergy 756840 # Energy for read commands per rank (pJ)
229,241c230,247
< system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ)
< system.physmem_0.averagePower 783.164377 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states
< system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
< system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states
< system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
---
> system.physmem_0.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_0.actBackEnergy 1602840 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 46080 # Energy for precharge background per rank (pJ)
> system.physmem_0.actPowerDownEnergy 8339100 # Energy for active power-down per rank (pJ)
> system.physmem_0.prePowerDownEnergy 953280 # Energy for precharge power-down per rank (pJ)
> system.physmem_0.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_0.totalEnergy 13833510 # Total energy per rank (pJ)
> system.physmem_0.averagePower 566.830977 # Core power per rank (mW)
> system.physmem_0.totalIdleTime 20709000 # Total Idle time Per DRAM Rank
> system.physmem_0.memoryStateTime::IDLE 23500 # Time in different power states
> system.physmem_0.memoryStateTime::REF 780000 # Time in different power states
> system.physmem_0.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_0.memoryStateTime::PRE_PDN 2481750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT 2828750 # Time in different power states
> system.physmem_0.memoryStateTime::ACT_PDN 18291000 # Time in different power states
> system.physmem_1.actEnergy 642600 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 333960 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 2591820 # Energy for read commands per rank (pJ)
243,256c249,267
< system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
< system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ)
< system.physmem_1.averagePower 935.350071 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states
< system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
< system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
< system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states
< system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
< system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2189 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted
< system.cpu.branchPred.condIncorrect 425 # Number of conditional branches incorrect
---
> system.physmem_1.refreshEnergy 1843920.000000 # Energy for refresh commands per rank (pJ)
> system.physmem_1.actBackEnergy 4214580 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 89760 # Energy for precharge background per rank (pJ)
> system.physmem_1.actPowerDownEnergy 6593190 # Energy for active power-down per rank (pJ)
> system.physmem_1.prePowerDownEnergy 180480 # Energy for precharge power-down per rank (pJ)
> system.physmem_1.selfRefreshEnergy 0 # Energy for self refresh per rank (pJ)
> system.physmem_1.totalEnergy 16490310 # Total energy per rank (pJ)
> system.physmem_1.averagePower 675.693915 # Core power per rank (mW)
> system.physmem_1.totalIdleTime 14889250 # Total Idle time Per DRAM Rank
> system.physmem_1.memoryStateTime::IDLE 122500 # Time in different power states
> system.physmem_1.memoryStateTime::REF 780000 # Time in different power states
> system.physmem_1.memoryStateTime::SREF 0 # Time in different power states
> system.physmem_1.memoryStateTime::PRE_PDN 470250 # Time in different power states
> system.physmem_1.memoryStateTime::ACT 8563750 # Time in different power states
> system.physmem_1.memoryStateTime::ACT_PDN 14468500 # Time in different power states
> system.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2188 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1456 # Number of conditional branches predicted
> system.cpu.branchPred.condIncorrect 424 # Number of conditional branches incorrect
261c272
< system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.usedRAS 252 # Number of times the RAS was used to get a target.
266c277
< system.cpu.branchPredindirectMispredicted 96 # Number of mispredicted indirect branches.
---
> system.cpu.branchPredindirectMispredicted 95 # Number of mispredicted indirect branches.
287,288c298,299
< system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 45677 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 24405000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 48811 # number of cpu cycles simulated
291,296c302,307
< system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked
< system.cpu.fetch.SquashCycles 870 # Number of cycles fetch has spent squashing
---
> system.cpu.fetch.icacheStallCycles 9089 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13001 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2188 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 841 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 5447 # Number of cycles fetch has run and was not squashing or blocked
> system.cpu.fetch.SquashCycles 868 # Number of cycles fetch has spent squashing
300,302c311,313
< system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 15175 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.856738 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.144886 # Number of instructions fetched each cycle (Total)
304,312c315,323
< system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11815 77.86% 77.86% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1507 9.93% 87.79% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 111 0.73% 88.52% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 162 1.07% 89.59% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 279 1.84% 91.43% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 100 0.66% 92.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 140 0.92% 93.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 158 1.04% 94.05% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 903 5.95% 100.00% # Number of instructions fetched each cycle (Total)
316,323c327,334
< system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2777 # Number of cycles decode is running
< system.cpu.decode.UnblockCycles 140 # Number of cycles decode is unblocking
< system.cpu.decode.SquashCycles 395 # Number of cycles decode is squashing
---
> system.cpu.fetch.rateDist::total 15175 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.044826 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.266354 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8420 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 3451 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2768 # Number of cycles decode is running
> system.cpu.decode.UnblockCycles 142 # Number of cycles decode is unblocking
> system.cpu.decode.SquashCycles 394 # Number of cycles decode is squashing
326c337
< system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12000 # Number of instructions handled by decode
328,334c339,345
< system.cpu.rename.SquashCycles 395 # Number of cycles rename is squashing
< system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2748 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename
---
> system.cpu.rename.SquashCycles 394 # Number of cycles rename is squashing
> system.cpu.rename.IdleCycles 8571 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 621 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 1023 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2740 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1826 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11562 # Number of instructions processed by rename
337,341c348,352
< system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups
---
> system.cpu.rename.LQFullEvents 193 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 1606 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 6927 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 13556 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13323 # Number of integer rename lookups
344c355
< system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3635 # Number of HB maps that are undone due to squashing
347,349c358,360
< system.cpu.rename.skidInsts 307 # count of insts added to the skid buffer
< system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit.
< system.cpu.memDep0.insertedStores 1158 # Number of stores inserted to the mem dependence unit.
---
> system.cpu.rename.skidInsts 323 # count of insts added to the skid buffer
> system.cpu.memDep0.insertedLoads 2470 # Number of loads inserted to the mem dependence unit.
> system.cpu.memDep0.insertedStores 1160 # Number of stores inserted to the mem dependence unit.
352,354c363,365
< system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec)
< system.cpu.iq.iqNonSpecInstsAdded 10 # Number of non-speculative instructions added to the IQ
< system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued
---
> system.cpu.iq.iqInstsAdded 9019 # Number of instructions added to the IQ (excludes non-spec)
> system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
> system.cpu.iq.iqInstsIssued 8119 # Number of instructions issued
356,361c367,372
< system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph
< system.cpu.iq.iqSquashedNonSpecRemoved 1 # Number of squashed non-spec instructions that were removed
< system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle
---
> system.cpu.iq.iqSquashedInstsExamined 4030 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2019 # Number of squashed operands that are examined and possibly removed from graph
> system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
> system.cpu.iq.issued_per_cycle::samples 15175 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.535025 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.265920 # Number of insts issued each cycle
363,370c374,381
< system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11852 78.10% 78.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1334 8.79% 86.89% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 728 4.80% 91.69% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 454 2.99% 94.68% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 341 2.25% 96.93% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 284 1.87% 98.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 110 0.72% 99.53% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 53 0.35% 99.87% # Number of insts issued each cycle
375c386
< system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 15175 # Number of insts issued each cycle
377,407c388,418
< system.cpu.iq.fu_full::IntAlu 7 3.87% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntMult 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::IntDiv 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatMult 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMult 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShift 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.87% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemRead 117 64.64% 68.51% # attempts to use FU when none available
< system.cpu.iq.fu_full::MemWrite 57 31.49% 100.00% # attempts to use FU when none available
---
> system.cpu.iq.fu_full::IntAlu 6 3.33% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntMult 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::IntDiv 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatMult 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMult 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShift 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemRead 117 65.00% 68.33% # attempts to use FU when none available
> system.cpu.iq.fu_full::MemWrite 57 31.67% 100.00% # attempts to use FU when none available
411,441c422,452
< system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued
< system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.93% # Type of FU issued
< system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.94% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued
< system.cpu.iq.FU_type_0::MemWrite 1061 13.06% 100.00% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4775 58.81% 58.81% # Type of FU issued
> system.cpu.iq.FU_type_0::IntMult 4 0.05% 58.86% # Type of FU issued
> system.cpu.iq.FU_type_0::IntDiv 1 0.01% 58.87% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.90% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2274 28.01% 86.91% # Type of FU issued
> system.cpu.iq.FU_type_0::MemWrite 1063 13.09% 100.00% # Type of FU issued
444,450c455,461
< system.cpu.iq.FU_type_0::total 8125 # Type of FU issued
< system.cpu.iq.rate 0.177879 # Inst issue rate
< system.cpu.iq.fu_busy_cnt 181 # FU busy when requested
< system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.FU_type_0::total 8119 # Type of FU issued
> system.cpu.iq.rate 0.166335 # Inst issue rate
> system.cpu.iq.fu_busy_cnt 180 # FU busy when requested
> system.cpu.iq.fu_busy_rate 0.022170 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 31608 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 13067 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7338 # Number of integer instruction queue wakeup accesses
454c465
< system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8297 # Number of integer alu accesses
458c469
< system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1335 # Number of loads squashed
461c472
< system.cpu.iew.lsq.thread0.squashedStores 257 # Number of stores squashed
---
> system.cpu.iew.lsq.thread0.squashedStores 259 # Number of stores squashed
467c478
< system.cpu.iew.iewSquashCycles 395 # Number of cycles IEW is squashing
---
> system.cpu.iew.iewSquashCycles 394 # Number of cycles IEW is squashing
469,474c480,485
< system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions
< system.cpu.iew.iewDispStoreInsts 1158 # Number of dispatched store instructions
< system.cpu.iew.iewDispNonSpecInsts 10 # Number of dispatched non-speculative instructions
---
> system.cpu.iew.iewUnblockCycles 74 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 10629 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 154 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2470 # Number of dispatched load instructions
> system.cpu.iew.iewDispStoreInsts 1160 # Number of dispatched store instructions
> system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
476c487
< system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 75 # Number of times the LSQ has become full, causing a stall
479,481c490,492
< system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions
---
> system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 7792 # Number of executed instructions
483c494
< system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.iewExecSquashedInsts 327 # Number of squashed instructions skipped in execute
485c496
< system.cpu.iew.exec_nop 1602 # number of nop insts executed
---
> system.cpu.iew.exec_nop 1599 # number of nop insts executed
487c498
< system.cpu.iew.exec_branches 1368 # Number of branches executed
---
> system.cpu.iew.exec_branches 1364 # Number of branches executed
489,496c500,507
< system.cpu.iew.exec_rate 0.170742 # Inst execution rate
< system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7349 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2873 # num instructions producing a value
< system.cpu.iew.wb_consumers 4285 # num instructions consuming a value
< system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit
---
> system.cpu.iew.exec_rate 0.159636 # Inst execution rate
> system.cpu.iew.wb_sent 7433 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7340 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2867 # num instructions producing a value
> system.cpu.iew.wb_consumers 4275 # num instructions consuming a value
> system.cpu.iew.wb_rate 0.150376 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.670643 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4990 # The number of squashed insts skipped by commit
498,501c509,512
< system.cpu.commit.branchMispredicts 385 # The number of times a branch was mispredicted
< system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle
---
> system.cpu.commit.branchMispredicts 384 # The number of times a branch was mispredicted
> system.cpu.commit.committed_per_cycle::samples 14293 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.394599 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.198950 # Number of insts commited each cycle
503,511c514,522
< system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 12101 84.66% 84.66% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 885 6.19% 90.86% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 521 3.65% 94.50% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 254 1.78% 96.28% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 160 1.12% 97.40% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 166 1.16% 98.56% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 63 0.44% 99.00% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 41 0.29% 99.29% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 102 0.71% 100.00% # Number of insts commited each cycle
515c526
< system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 14293 # Number of insts commited each cycle
561,563c572,574
< system.cpu.commit.bw_lim_events 104 # number cycles where commit BW limit reached
< system.cpu.rob.rob_reads 24134 # The number of ROB reads
< system.cpu.rob.rob_writes 22169 # The number of ROB writes
---
> system.cpu.commit.bw_lim_events 102 # number cycles where commit BW limit reached
> system.cpu.rob.rob_reads 24808 # The number of ROB reads
> system.cpu.rob.rob_writes 22150 # The number of ROB writes
565c576
< system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.idleCycles 33636 # Total number of cycles that the CPU has spent unscheduled due to idling
568,573c579,584
< system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 10569 # number of integer regfile reads
< system.cpu.int_regfile_writes 5149 # number of integer regfile writes
---
> system.cpu.cpi 9.764153 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 9.764153 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.102415 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.102415 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 10563 # number of integer regfile reads
> system.cpu.int_regfile_writes 5141 # number of integer regfile writes
576,577c587,588
< system.cpu.misc_regfile_reads 160 # number of misc regfile reads
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.misc_regfile_reads 161 # number of misc regfile reads
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
579,580c590,591
< system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 91.114118 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2396 # Total number of references to valid blocks.
582c593
< system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 17.114286 # Average number of references to valid blocks.
584,586c595,597
< system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 91.114118 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.022245 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.022245 # Average percentage of cache occupancy
588,589c599,600
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 31 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 109 # Occupied blocks per task id
593c604
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
596,601c607,612
< system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
< system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
< system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
< system.cpu.dcache.overall_hits::total 2395 # number of overall hits
---
> system.cpu.dcache.WriteReq_hits::cpu.data 557 # number of WriteReq hits
> system.cpu.dcache.WriteReq_hits::total 557 # number of WriteReq hits
> system.cpu.dcache.demand_hits::cpu.data 2396 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2396 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2396 # number of overall hits
> system.cpu.dcache.overall_hits::total 2396 # number of overall hits
604,617c615,628
< system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
< system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
< system.cpu.dcache.demand_misses::cpu.data 512 # number of demand (read+write) misses
< system.cpu.dcache.demand_misses::total 512 # number of demand (read+write) misses
< system.cpu.dcache.overall_misses::cpu.data 512 # number of overall misses
< system.cpu.dcache.overall_misses::total 512 # number of overall misses
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles
---
> system.cpu.dcache.WriteReq_misses::cpu.data 344 # number of WriteReq misses
> system.cpu.dcache.WriteReq_misses::total 344 # number of WriteReq misses
> system.cpu.dcache.demand_misses::cpu.data 511 # number of demand (read+write) misses
> system.cpu.dcache.demand_misses::total 511 # number of demand (read+write) misses
> system.cpu.dcache.overall_misses::cpu.data 511 # number of overall misses
> system.cpu.dcache.overall_misses::total 511 # number of overall misses
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12711500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12711500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 34219499 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 34219499 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 46930999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 46930999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 46930999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 46930999 # number of overall miss cycles
628,642c639,653
< system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
< system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
< system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked
---
> system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.381798 # miss rate for WriteReq accesses
> system.cpu.dcache.WriteReq_miss_rate::total 0.381798 # miss rate for WriteReq accesses
> system.cpu.dcache.demand_miss_rate::cpu.data 0.175783 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.175783 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.175783 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.175783 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 76116.766467 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 76116.766467 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 99475.287791 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 99475.287791 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 91841.485323 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 91841.485323 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 91841.485323 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 636 # number of cycles access was blocked
646c657
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 63.600000 # average number of cycles each access was blocked
650,655c661,666
< system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
< system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
< system.cpu.dcache.demand_mshr_hits::cpu.data 372 # number of demand (read+write) MSHR hits
< system.cpu.dcache.demand_mshr_hits::total 372 # number of demand (read+write) MSHR hits
< system.cpu.dcache.overall_mshr_hits::cpu.data 372 # number of overall MSHR hits
< system.cpu.dcache.overall_mshr_hits::total 372 # number of overall MSHR hits
---
> system.cpu.dcache.WriteReq_mshr_hits::cpu.data 294 # number of WriteReq MSHR hits
> system.cpu.dcache.WriteReq_mshr_hits::total 294 # number of WriteReq MSHR hits
> system.cpu.dcache.demand_mshr_hits::cpu.data 371 # number of demand (read+write) MSHR hits
> system.cpu.dcache.demand_mshr_hits::total 371 # number of demand (read+write) MSHR hits
> system.cpu.dcache.overall_mshr_hits::cpu.data 371 # number of overall MSHR hits
> system.cpu.dcache.overall_mshr_hits::total 371 # number of overall MSHR hits
664,671c675,682
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 8095000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 8095000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4915999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4915999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 13010999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 13010999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 13010999 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 13010999 # number of overall MSHR miss cycles
680,688c691,699
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 89944.444444 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 89944.444444 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 98319.980000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 98319.980000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 92935.707143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 92935.707143 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
690,691c701,702
< system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 160.115290 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1613 # Total number of references to valid blocks.
693c704
< system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.858434 # Average number of references to valid blocks.
695,697c706,708
< system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 160.115290 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078181 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078181 # Average percentage of cache occupancy
699,700c710,711
< system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 132 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 183 # Occupied blocks per task id
704,722c715,733
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits
< system.cpu.icache.overall_hits::total 1612 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses
< system.cpu.icache.overall_misses::total 438 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles
---
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1613 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1613 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1613 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1613 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1613 # number of overall hits
> system.cpu.icache.overall_hits::total 1613 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
> system.cpu.icache.overall_misses::total 437 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 35529000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 35529000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 35529000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 35529000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 35529000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 35529000 # number of overall miss cycles
729,740c740,751
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency
---
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213171 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.213171 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.213171 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.213171 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.213171 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.213171 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 81302.059497 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 81302.059497 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 81302.059497 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 81302.059497 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 81302.059497 # average overall miss latency
749,754c760,765
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits
761,766c772,777
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 28113000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 28113000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 28113000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 28113000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 28113000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 28113000 # number of overall MSHR miss cycles
773,779c784,790
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 84677.710843 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 84677.710843 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 84677.710843 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 84677.710843 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
781c792
< system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 253.317608 # Cycle average of tags in use
786,790c797,801
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 162.143256 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 91.174352 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004948 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002782 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007731 # Average percentage of cache occupancy
792,793c803,804
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
---
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 171 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 298 # Occupied blocks per task id
797c808
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
818,829c829,840
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4840000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4840000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 27582000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 27582000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7957000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7957000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 27582000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 12797000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 40379000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 27582000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 12797000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 40379000 # number of overall miss cycles
856,867c867,878
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 96800 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 96800 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 83835.866261 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 83835.866261 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 88411.111111 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 88411.111111 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 86095.948827 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 83835.866261 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 91407.142857 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 86095.948827 # average overall miss latency
886,897c897,908
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 4340000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 4340000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 24292000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 24292000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 7057000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 7057000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 24292000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 11397000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 35689000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 24292000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 11397000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 35689000 # number of overall MSHR miss cycles
910,921c921,932
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 86800 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 86800 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 73835.866261 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 73835.866261 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 78411.111111 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 78411.111111 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 73835.866261 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 81407.142857 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 76095.948827 # average overall mshr miss latency
928c939
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
957c968
< system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
---
> system.cpu.toL2Bus.respLayer0.utilization 2.0 # Layer utilization (%)
966c977
< system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
---
> system.membus.pwrStateResidencyTicks::UNDEFINED 24405000 # Cumulative time (in ticks) in various power states
988,990c999,1001
< system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 10.9 # Layer utilization (%)
---
> system.membus.reqLayer0.utilization 2.4 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2488500 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 10.2 # Layer utilization (%)