4,5c4,5
< sim_ticks 22532000 # Number of ticks simulated
< final_tick 22532000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 22838000 # Number of ticks simulated
> final_tick 22838000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 94024 # Simulator instruction rate (inst/s)
< host_op_rate 93989 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 423490323 # Simulator tick rate (ticks/s)
< host_mem_usage 248172 # Number of bytes of host memory used
< host_seconds 0.05 # Real time elapsed on the host
---
> host_inst_rate 76246 # Simulator instruction rate (inst/s)
> host_op_rate 76230 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 348191953 # Simulator tick rate (ticks/s)
> host_mem_usage 252304 # Number of bytes of host memory used
> host_seconds 0.07 # Real time elapsed on the host
16c16
< system.physmem.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.physmem.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
25,32c25,32
< system.physmem.bw_read::cpu.inst 934493165 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 397656666 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1332149831 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 934493165 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 934493165 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 934493165 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 397656666 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1332149831 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 921972152 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 392328575 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1314300727 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 921972152 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 921972152 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 921972152 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 392328575 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1314300727 # Total bandwidth to/from this memory (bytes/s)
79c79
< system.physmem.totGap 22446500 # Total gap between requests
---
> system.physmem.totGap 22751500 # Total gap between requests
94,95c94,95
< system.physmem.rdQLenPdf::0 275 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 131 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 276 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 130 # What read queue length does an incoming req see
190,204c190,204
< system.physmem.bytesPerActivate::samples 106 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 257.207547 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 176.154447 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 250.139569 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 32 30.19% 30.19% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32 30.19% 60.38% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 19 17.92% 78.30% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 9 8.49% 86.79% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 4 3.77% 90.57% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 2 1.89% 92.45% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 1.89% 94.34% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 6 5.66% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 106 # Bytes accessed per row activation
< system.physmem.totQLat 4611250 # Total ticks spent queuing
< system.physmem.totMemAccLat 13405000 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 105 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 259.047619 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 178.738362 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 250.145511 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 30 28.57% 28.57% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 33 31.43% 60.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 19 18.10% 78.10% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 9 8.57% 86.67% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 3.81% 90.48% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 2 1.90% 92.38% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 2 1.90% 94.29% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 6 5.71% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 105 # Bytes accessed per row activation
> system.physmem.totQLat 4619250 # Total ticks spent queuing
> system.physmem.totMemAccLat 13413000 # Total ticks spent from burst creation until serviced by the DRAM
206c206
< system.physmem.avgQLat 9832.09 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 9849.15 # Average queueing delay per DRAM burst
208,209c208,209
< system.physmem.avgMemAccLat 28582.09 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1332.15 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28599.15 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1314.30 # Average DRAM read bandwidth in MiByte/s
211c211
< system.physmem.avgRdBWSys 1332.15 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1314.30 # Average system read bandwidth in MiByte/s
214,215c214,215
< system.physmem.busUtil 10.41 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.41 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.27 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.27 # Data bus utilization in percentage for reads
223c223
< system.physmem.avgGap 47860.34 # Average gap between requests
---
> system.physmem.avgGap 48510.66 # Average gap between requests
227c227
< system.physmem_0.readEnergy 538200 # Energy for read commands per rank (pJ)
---
> system.physmem_0.readEnergy 514800 # Energy for read commands per rank (pJ)
230,234c230,234
< system.physmem_0.actBackEnergy 9591390 # Energy for active background per rank (pJ)
< system.physmem_0.preBackEnergy 1086000 # Energy for precharge background per rank (pJ)
< system.physmem_0.totalEnergy 12431355 # Total energy per rank (pJ)
< system.physmem_0.averagePower 785.179536 # Core power per rank (mW)
< system.physmem_0.memoryStateTime::IDLE 2005750 # Time in different power states
---
> system.physmem_0.actBackEnergy 9522135 # Energy for active background per rank (pJ)
> system.physmem_0.preBackEnergy 1146750 # Energy for precharge background per rank (pJ)
> system.physmem_0.totalEnergy 12399450 # Total energy per rank (pJ)
> system.physmem_0.averagePower 783.164377 # Core power per rank (mW)
> system.physmem_0.memoryStateTime::IDLE 1868000 # Time in different power states
237c237
< system.physmem_0.memoryStateTime::ACT 13559250 # Time in different power states
---
> system.physmem_0.memoryStateTime::ACT 13458250 # Time in different power states
239,241c239,241
< system.physmem_1.actEnergy 529200 # Energy for activate commands per rank (pJ)
< system.physmem_1.preEnergy 288750 # Energy for precharge commands per rank (pJ)
< system.physmem_1.readEnergy 2176200 # Energy for read commands per rank (pJ)
---
> system.physmem_1.actEnergy 521640 # Energy for activate commands per rank (pJ)
> system.physmem_1.preEnergy 284625 # Energy for precharge commands per rank (pJ)
> system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
244,248c244,248
< system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
< system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
< system.physmem_1.totalEnergy 14828520 # Total energy per rank (pJ)
< system.physmem_1.averagePower 936.587399 # Core power per rank (mW)
< system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
---
> system.physmem_1.actBackEnergy 10729395 # Energy for active background per rank (pJ)
> system.physmem_1.preBackEnergy 87750 # Energy for precharge background per rank (pJ)
> system.physmem_1.totalEnergy 14808930 # Total energy per rank (pJ)
> system.physmem_1.averagePower 935.350071 # Core power per rank (mW)
> system.physmem_1.memoryStateTime::IDLE 200750 # Time in different power states
251c251
< system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
---
> system.physmem_1.memoryStateTime::ACT 15221750 # Time in different power states
253,255c253,255
< system.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
< system.cpu.branchPred.lookups 2183 # Number of BP lookups
< system.cpu.branchPred.condPredicted 1455 # Number of conditional branches predicted
---
> system.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
> system.cpu.branchPred.lookups 2189 # Number of BP lookups
> system.cpu.branchPred.condPredicted 1457 # Number of conditional branches predicted
257c257
< system.cpu.branchPred.BTBLookups 1779 # Number of BTB lookups
---
> system.cpu.branchPred.BTBLookups 1784 # Number of BTB lookups
260,261c260,261
< system.cpu.branchPred.BTBHitPct 32.996065 # BTB Hit Percentage
< system.cpu.branchPred.usedRAS 250 # Number of times the RAS was used to get a target.
---
> system.cpu.branchPred.BTBHitPct 32.903587 # BTB Hit Percentage
> system.cpu.branchPred.usedRAS 251 # Number of times the RAS was used to get a target.
263c263
< system.cpu.branchPred.indirectLookups 269 # Number of indirect predictor lookups.
---
> system.cpu.branchPred.indirectLookups 270 # Number of indirect predictor lookups.
265c265
< system.cpu.branchPred.indirectMisses 267 # Number of indirect misses.
---
> system.cpu.branchPred.indirectMisses 268 # Number of indirect misses.
287,288c287,288
< system.cpu.pwrStateResidencyTicks::ON 22532000 # Cumulative time (in ticks) in various power states
< system.cpu.numCycles 45065 # number of cpu cycles simulated
---
> system.cpu.pwrStateResidencyTicks::ON 22838000 # Cumulative time (in ticks) in various power states
> system.cpu.numCycles 45677 # number of cpu cycles simulated
291,295c291,295
< system.cpu.fetch.icacheStallCycles 9068 # Number of cycles fetch is stalled on an Icache miss
< system.cpu.fetch.Insts 12986 # Number of instructions fetch has processed
< system.cpu.fetch.Branches 2183 # Number of branches that fetch encountered
< system.cpu.fetch.predictedBranches 839 # Number of branches that fetch has predicted taken
< system.cpu.fetch.Cycles 4746 # Number of cycles fetch has run and was not squashing or blocked
---
> system.cpu.fetch.icacheStallCycles 9081 # Number of cycles fetch is stalled on an Icache miss
> system.cpu.fetch.Insts 13012 # Number of instructions fetch has processed
> system.cpu.fetch.Branches 2189 # Number of branches that fetch encountered
> system.cpu.fetch.predictedBranches 840 # Number of branches that fetch has predicted taken
> system.cpu.fetch.Cycles 4774 # Number of cycles fetch has run and was not squashing or blocked
298,302c298,302
< system.cpu.fetch.CacheLines 2047 # Number of cache lines fetched
< system.cpu.fetch.IcacheSquashes 264 # Number of outstanding Icache misses that were squashed
< system.cpu.fetch.rateDist::samples 14454 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.898436 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.187928 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.CacheLines 2050 # Number of cache lines fetched
> system.cpu.fetch.IcacheSquashes 263 # Number of outstanding Icache misses that were squashed
> system.cpu.fetch.rateDist::samples 14495 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.897689 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.187204 # Number of instructions fetched each cycle (Total)
304,312c304,312
< system.cpu.fetch.rateDist::0 11097 76.77% 76.77% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1507 10.43% 87.20% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 110 0.76% 87.96% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 162 1.12% 89.08% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::4 279 1.93% 91.01% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::5 99 0.68% 91.70% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::6 140 0.97% 92.67% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::7 158 1.09% 93.76% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::8 902 6.24% 100.00% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11134 76.81% 76.81% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1506 10.39% 87.20% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 111 0.77% 87.97% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 162 1.12% 89.09% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::4 279 1.92% 91.01% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::5 100 0.69% 91.70% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::6 142 0.98% 92.68% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::7 158 1.09% 93.77% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::8 903 6.23% 100.00% # Number of instructions fetched each cycle (Total)
316,321c316,321
< system.cpu.fetch.rateDist::total 14454 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.048441 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.288162 # Number of inst fetches per cycle
< system.cpu.decode.IdleCycles 8443 # Number of cycles decode is idle
< system.cpu.decode.BlockedCycles 2703 # Number of cycles decode is blocked
< system.cpu.decode.RunCycles 2773 # Number of cycles decode is running
---
> system.cpu.fetch.rateDist::total 14495 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.047923 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.284870 # Number of inst fetches per cycle
> system.cpu.decode.IdleCycles 8449 # Number of cycles decode is idle
> system.cpu.decode.BlockedCycles 2734 # Number of cycles decode is blocked
> system.cpu.decode.RunCycles 2777 # Number of cycles decode is running
324c324
< system.cpu.decode.BranchResolved 182 # Number of times decode resolved a branch
---
> system.cpu.decode.BranchResolved 183 # Number of times decode resolved a branch
326c326
< system.cpu.decode.DecodedInsts 12006 # Number of instructions handled by decode
---
> system.cpu.decode.DecodedInsts 12026 # Number of instructions handled by decode
329,334c329,334
< system.cpu.rename.IdleCycles 8593 # Number of cycles rename is idle
< system.cpu.rename.BlockCycles 592 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
< system.cpu.rename.RunCycles 2745 # Number of cycles rename is running
< system.cpu.rename.UnblockCycles 1156 # Number of cycles rename is unblocking
< system.cpu.rename.RenamedInsts 11571 # Number of instructions processed by rename
---
> system.cpu.rename.IdleCycles 8600 # Number of cycles rename is idle
> system.cpu.rename.BlockCycles 597 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
> system.cpu.rename.RunCycles 2748 # Number of cycles rename is running
> system.cpu.rename.UnblockCycles 1172 # Number of cycles rename is unblocking
> system.cpu.rename.RenamedInsts 11590 # Number of instructions processed by rename
337,341c337,341
< system.cpu.rename.LQFullEvents 175 # Number of times rename has blocked due to LQ full
< system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
< system.cpu.rename.RenamedOperands 6940 # Number of destination operands rename has renamed
< system.cpu.rename.RenameLookups 13573 # Number of register rename lookups that rename has made
< system.cpu.rename.int_rename_lookups 13340 # Number of integer rename lookups
---
> system.cpu.rename.LQFullEvents 177 # Number of times rename has blocked due to LQ full
> system.cpu.rename.SQFullEvents 968 # Number of times rename has blocked due to SQ full
> system.cpu.rename.RenamedOperands 6955 # Number of destination operands rename has renamed
> system.cpu.rename.RenameLookups 13597 # Number of register rename lookups that rename has made
> system.cpu.rename.int_rename_lookups 13364 # Number of integer rename lookups
344c344
< system.cpu.rename.UndoneMaps 3648 # Number of HB maps that are undone due to squashing
---
> system.cpu.rename.UndoneMaps 3663 # Number of HB maps that are undone due to squashing
348c348
< system.cpu.memDep0.insertedLoads 2471 # Number of loads inserted to the mem dependence unit.
---
> system.cpu.memDep0.insertedLoads 2472 # Number of loads inserted to the mem dependence unit.
352c352
< system.cpu.iq.iqInstsAdded 9030 # Number of instructions added to the IQ (excludes non-spec)
---
> system.cpu.iq.iqInstsAdded 9034 # Number of instructions added to the IQ (excludes non-spec)
354c354
< system.cpu.iq.iqInstsIssued 8122 # Number of instructions issued
---
> system.cpu.iq.iqInstsIssued 8125 # Number of instructions issued
356,357c356,357
< system.cpu.iq.iqSquashedInstsExamined 4040 # Number of squashed instructions iterated over during squash; mainly for profiling
< system.cpu.iq.iqSquashedOperandsExamined 2024 # Number of squashed operands that are examined and possibly removed from graph
---
> system.cpu.iq.iqSquashedInstsExamined 4044 # Number of squashed instructions iterated over during squash; mainly for profiling
> system.cpu.iq.iqSquashedOperandsExamined 2026 # Number of squashed operands that are examined and possibly removed from graph
359,361c359,361
< system.cpu.iq.issued_per_cycle::samples 14454 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.561921 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.290505 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 14495 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.560538 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.289389 # Number of insts issued each cycle
363,370c363,370
< system.cpu.iq.issued_per_cycle::0 11129 77.00% 77.00% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1334 9.23% 86.23% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 725 5.02% 91.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 461 3.19% 94.43% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::4 340 2.35% 96.78% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::5 284 1.96% 98.75% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::6 111 0.77% 99.52% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::7 51 0.35% 99.87% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 11167 77.04% 77.04% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1340 9.24% 86.28% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 721 4.97% 91.26% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 460 3.17% 94.43% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::4 343 2.37% 96.80% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::5 283 1.95% 98.75% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::6 110 0.76% 99.51% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::7 52 0.36% 99.87% # Number of insts issued each cycle
375c375
< system.cpu.iq.issued_per_cycle::total 14454 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 14495 # Number of insts issued each cycle
411c411
< system.cpu.iq.FU_type_0::IntAlu 4782 58.88% 58.88% # Type of FU issued
---
> system.cpu.iq.FU_type_0::IntAlu 4784 58.88% 58.88% # Type of FU issued
414,440c414,440
< system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.96% # Type of FU issued
< system.cpu.iq.FU_type_0::MemRead 2272 27.97% 86.94% # Type of FU issued
---
> system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatMult 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMult 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShift 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 58.97% # Type of FU issued
> system.cpu.iq.FU_type_0::MemRead 2273 27.98% 86.94% # Type of FU issued
444,445c444,445
< system.cpu.iq.FU_type_0::total 8122 # Type of FU issued
< system.cpu.iq.rate 0.180229 # Inst issue rate
---
> system.cpu.iq.FU_type_0::total 8125 # Type of FU issued
> system.cpu.iq.rate 0.177879 # Inst issue rate
447,450c447,450
< system.cpu.iq.fu_busy_rate 0.022285 # FU busy rate (busy events/executed inst)
< system.cpu.iq.int_inst_queue_reads 30894 # Number of integer instruction queue reads
< system.cpu.iq.int_inst_queue_writes 13087 # Number of integer instruction queue writes
< system.cpu.iq.int_inst_queue_wakeup_accesses 7350 # Number of integer instruction queue wakeup accesses
---
> system.cpu.iq.fu_busy_rate 0.022277 # FU busy rate (busy events/executed inst)
> system.cpu.iq.int_inst_queue_reads 30941 # Number of integer instruction queue reads
> system.cpu.iq.int_inst_queue_writes 13095 # Number of integer instruction queue writes
> system.cpu.iq.int_inst_queue_wakeup_accesses 7347 # Number of integer instruction queue wakeup accesses
454c454
< system.cpu.iq.int_alu_accesses 8301 # Number of integer alu accesses
---
> system.cpu.iq.int_alu_accesses 8304 # Number of integer alu accesses
458c458
< system.cpu.iew.lsq.thread0.squashedLoads 1336 # Number of loads squashed
---
> system.cpu.iew.lsq.thread0.squashedLoads 1337 # Number of loads squashed
468,472c468,472
< system.cpu.iew.iewBlockCycles 490 # Number of cycles IEW is blocking
< system.cpu.iew.iewUnblockCycles 57 # Number of cycles IEW is unblocking
< system.cpu.iew.iewDispatchedInsts 10642 # Number of instructions dispatched to IQ
< system.cpu.iew.iewDispSquashedInsts 148 # Number of squashed instructions skipped by dispatch
< system.cpu.iew.iewDispLoadInsts 2471 # Number of dispatched load instructions
---
> system.cpu.iew.iewBlockCycles 491 # Number of cycles IEW is blocking
> system.cpu.iew.iewUnblockCycles 59 # Number of cycles IEW is unblocking
> system.cpu.iew.iewDispatchedInsts 10646 # Number of instructions dispatched to IQ
> system.cpu.iew.iewDispSquashedInsts 156 # Number of squashed instructions skipped by dispatch
> system.cpu.iew.iewDispLoadInsts 2472 # Number of dispatched load instructions
476c476
< system.cpu.iew.iewLSQFullEvents 57 # Number of times the LSQ has become full, causing a stall
---
> system.cpu.iew.iewLSQFullEvents 59 # Number of times the LSQ has become full, causing a stall
479,483c479,483
< system.cpu.iew.predictedNotTakenIncorrect 338 # Number of branches that were predicted not taken incorrectly
< system.cpu.iew.branchMispredicts 439 # Number of branch mispredicts detected at execute
< system.cpu.iew.iewExecutedInsts 7800 # Number of executed instructions
< system.cpu.iew.iewExecLoadInsts 2128 # Number of load instructions executed
< system.cpu.iew.iewExecSquashedInsts 322 # Number of squashed instructions skipped in execute
---
> system.cpu.iew.predictedNotTakenIncorrect 339 # Number of branches that were predicted not taken incorrectly
> system.cpu.iew.branchMispredicts 440 # Number of branch mispredicts detected at execute
> system.cpu.iew.iewExecutedInsts 7799 # Number of executed instructions
> system.cpu.iew.iewExecLoadInsts 2130 # Number of load instructions executed
> system.cpu.iew.iewExecSquashedInsts 326 # Number of squashed instructions skipped in execute
486,487c486,487
< system.cpu.iew.exec_refs 3177 # number of memory reference insts executed
< system.cpu.iew.exec_branches 1369 # Number of branches executed
---
> system.cpu.iew.exec_refs 3179 # number of memory reference insts executed
> system.cpu.iew.exec_branches 1368 # Number of branches executed
489,492c489,492
< system.cpu.iew.exec_rate 0.173083 # Inst execution rate
< system.cpu.iew.wb_sent 7447 # cumulative count of insts sent to commit
< system.cpu.iew.wb_count 7352 # cumulative count of insts written-back
< system.cpu.iew.wb_producers 2874 # num instructions producing a value
---
> system.cpu.iew.exec_rate 0.170742 # Inst execution rate
> system.cpu.iew.wb_sent 7444 # cumulative count of insts sent to commit
> system.cpu.iew.wb_count 7349 # cumulative count of insts written-back
> system.cpu.iew.wb_producers 2873 # num instructions producing a value
494,496c494,496
< system.cpu.iew.wb_rate 0.163142 # insts written-back per cycle
< system.cpu.iew.wb_fanout 0.670712 # average fanout of values written-back
< system.cpu.commit.commitSquashedInsts 4995 # The number of squashed insts skipped by commit
---
> system.cpu.iew.wb_rate 0.160891 # insts written-back per cycle
> system.cpu.iew.wb_fanout 0.670478 # average fanout of values written-back
> system.cpu.commit.commitSquashedInsts 4999 # The number of squashed insts skipped by commit
499,501c499,501
< system.cpu.commit.committed_per_cycle::samples 13572 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.415561 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.228101 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13612 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.414340 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.226502 # Number of insts commited each cycle
503,511c503,511
< system.cpu.commit.committed_per_cycle::0 11381 83.86% 83.86% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::1 886 6.53% 90.38% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::2 519 3.82% 94.21% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::3 254 1.87% 96.08% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::4 162 1.19% 97.27% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::5 163 1.20% 98.47% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::6 62 0.46% 98.93% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::7 41 0.30% 99.23% # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::8 104 0.77% 100.00% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11422 83.91% 83.91% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::1 884 6.49% 90.41% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::2 520 3.82% 94.23% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::3 254 1.87% 96.09% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::4 161 1.18% 97.27% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::5 165 1.21% 98.49% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::6 61 0.45% 98.93% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::7 41 0.30% 99.24% # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::8 104 0.76% 100.00% # Number of insts commited each cycle
515c515
< system.cpu.commit.committed_per_cycle::total 13572 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13612 # Number of insts commited each cycle
562,565c562,565
< system.cpu.rob.rob_reads 24090 # The number of ROB reads
< system.cpu.rob.rob_writes 22160 # The number of ROB writes
< system.cpu.timesIdled 263 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 30611 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.rob.rob_reads 24134 # The number of ROB reads
> system.cpu.rob.rob_writes 22169 # The number of ROB writes
> system.cpu.timesIdled 264 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 31182 # Total number of cycles that the CPU has spent unscheduled due to idling
568,573c568,573
< system.cpu.cpi 9.014803 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 9.014803 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.110929 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.110929 # IPC: Total IPC of All Threads
< system.cpu.int_regfile_reads 10573 # number of integer regfile reads
< system.cpu.int_regfile_writes 5151 # number of integer regfile writes
---
> system.cpu.cpi 9.137227 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 9.137227 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.109442 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.109442 # IPC: Total IPC of All Threads
> system.cpu.int_regfile_reads 10569 # number of integer regfile reads
> system.cpu.int_regfile_writes 5149 # number of integer regfile writes
577c577
< system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
579,580c579,580
< system.cpu.dcache.tags.tagsinuse 90.625823 # Cycle average of tags in use
< system.cpu.dcache.tags.total_refs 2393 # Total number of references to valid blocks.
---
> system.cpu.dcache.tags.tagsinuse 90.737808 # Cycle average of tags in use
> system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
582c582
< system.cpu.dcache.tags.avg_refs 17.092857 # Average number of references to valid blocks.
---
> system.cpu.dcache.tags.avg_refs 17.107143 # Average number of references to valid blocks.
584,586c584,586
< system.cpu.dcache.tags.occ_blocks::cpu.data 90.625823 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.022125 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.022125 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 90.737808 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.022153 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.022153 # Average percentage of cache occupancy
588,589c588,589
< system.cpu.dcache.tags.age_task_id_blocks_1024::0 35 # Occupied blocks per task id
< system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
---
> system.cpu.dcache.tags.age_task_id_blocks_1024::0 34 # Occupied blocks per task id
> system.cpu.dcache.tags.age_task_id_blocks_1024::1 106 # Occupied blocks per task id
591,595c591,595
< system.cpu.dcache.tags.tag_accesses 5950 # Number of tag accesses
< system.cpu.dcache.tags.data_accesses 5950 # Number of data accesses
< system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
< system.cpu.dcache.ReadReq_hits::cpu.data 1837 # number of ReadReq hits
< system.cpu.dcache.ReadReq_hits::total 1837 # number of ReadReq hits
---
> system.cpu.dcache.tags.tag_accesses 5954 # Number of tag accesses
> system.cpu.dcache.tags.data_accesses 5954 # Number of data accesses
> system.cpu.dcache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
> system.cpu.dcache.ReadReq_hits::cpu.data 1839 # number of ReadReq hits
> system.cpu.dcache.ReadReq_hits::total 1839 # number of ReadReq hits
598,601c598,601
< system.cpu.dcache.demand_hits::cpu.data 2393 # number of demand (read+write) hits
< system.cpu.dcache.demand_hits::total 2393 # number of demand (read+write) hits
< system.cpu.dcache.overall_hits::cpu.data 2393 # number of overall hits
< system.cpu.dcache.overall_hits::total 2393 # number of overall hits
---
> system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
> system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
> system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
> system.cpu.dcache.overall_hits::total 2395 # number of overall hits
610,619c610,619
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11867500 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11867500 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 24012499 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 24012499 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 35879999 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 35879999 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 35879999 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 35879999 # number of overall miss cycles
< system.cpu.dcache.ReadReq_accesses::cpu.data 2004 # number of ReadReq accesses(hits+misses)
< system.cpu.dcache.ReadReq_accesses::total 2004 # number of ReadReq accesses(hits+misses)
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 12256500 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 12256500 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 24340499 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 24340499 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 36596999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 36596999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 36596999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 36596999 # number of overall miss cycles
> system.cpu.dcache.ReadReq_accesses::cpu.data 2006 # number of ReadReq accesses(hits+misses)
> system.cpu.dcache.ReadReq_accesses::total 2006 # number of ReadReq accesses(hits+misses)
622,627c622,627
< system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
< system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
< system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
< system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
< system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083333 # miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_miss_rate::total 0.083333 # miss rate for ReadReq accesses
---
> system.cpu.dcache.demand_accesses::cpu.data 2907 # number of demand (read+write) accesses
> system.cpu.dcache.demand_accesses::total 2907 # number of demand (read+write) accesses
> system.cpu.dcache.overall_accesses::cpu.data 2907 # number of overall (read+write) accesses
> system.cpu.dcache.overall_accesses::total 2907 # number of overall (read+write) accesses
> system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.083250 # miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_miss_rate::total 0.083250 # miss rate for ReadReq accesses
630,642c630,642
< system.cpu.dcache.demand_miss_rate::cpu.data 0.176248 # miss rate for demand accesses
< system.cpu.dcache.demand_miss_rate::total 0.176248 # miss rate for demand accesses
< system.cpu.dcache.overall_miss_rate::cpu.data 0.176248 # miss rate for overall accesses
< system.cpu.dcache.overall_miss_rate::total 0.176248 # miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71062.874251 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 71062.874251 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69601.446377 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 69601.446377 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 70078.123047 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 70078.123047 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 70078.123047 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 592 # number of cycles access was blocked
---
> system.cpu.dcache.demand_miss_rate::cpu.data 0.176127 # miss rate for demand accesses
> system.cpu.dcache.demand_miss_rate::total 0.176127 # miss rate for demand accesses
> system.cpu.dcache.overall_miss_rate::cpu.data 0.176127 # miss rate for overall accesses
> system.cpu.dcache.overall_miss_rate::total 0.176127 # miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 73392.215569 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 73392.215569 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 70552.171014 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 70552.171014 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 71478.513672 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 71478.513672 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 71478.513672 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 600 # number of cycles access was blocked
646c646
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 59.200000 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 60 # average number of cycles each access was blocked
664,673c664,673
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7550000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7550000 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4082999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4082999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11632999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11632999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11632999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11632999 # number of overall MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044910 # mshr miss rate for ReadReq accesses
< system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044910 # mshr miss rate for ReadReq accesses
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7898000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7898000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4132999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4132999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 12030999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 12030999 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 12030999 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 12030999 # number of overall MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.044865 # mshr miss rate for ReadReq accesses
> system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.044865 # mshr miss rate for ReadReq accesses
676,688c676,688
< system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for demand accesses
< system.cpu.dcache.demand_mshr_miss_rate::total 0.048193 # mshr miss rate for demand accesses
< system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048193 # mshr miss rate for overall accesses
< system.cpu.dcache.overall_mshr_miss_rate::total 0.048193 # mshr miss rate for overall accesses
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83888.888889 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83888.888889 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81659.980000 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81659.980000 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 83092.850000 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 83092.850000 # average overall mshr miss latency
< system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for demand accesses
> system.cpu.dcache.demand_mshr_miss_rate::total 0.048160 # mshr miss rate for demand accesses
> system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048160 # mshr miss rate for overall accesses
> system.cpu.dcache.overall_mshr_miss_rate::total 0.048160 # mshr miss rate for overall accesses
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 87755.555556 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 87755.555556 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 82659.980000 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 82659.980000 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 85935.707143 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 85935.707143 # average overall mshr miss latency
> system.cpu.icache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
690,691c690,691
< system.cpu.icache.tags.tagsinuse 158.780297 # Cycle average of tags in use
< system.cpu.icache.tags.total_refs 1610 # Total number of references to valid blocks.
---
> system.cpu.icache.tags.tagsinuse 158.952170 # Cycle average of tags in use
> system.cpu.icache.tags.total_refs 1612 # Total number of references to valid blocks.
693c693
< system.cpu.icache.tags.avg_refs 4.849398 # Average number of references to valid blocks.
---
> system.cpu.icache.tags.avg_refs 4.855422 # Average number of references to valid blocks.
695,697c695,697
< system.cpu.icache.tags.occ_blocks::cpu.inst 158.780297 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.077529 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.077529 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 158.952170 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.077613 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.077613 # Average percentage of cache occupancy
699,700c699,700
< system.cpu.icache.tags.age_task_id_blocks_1024::0 143 # Occupied blocks per task id
< system.cpu.icache.tags.age_task_id_blocks_1024::1 172 # Occupied blocks per task id
---
> system.cpu.icache.tags.age_task_id_blocks_1024::0 141 # Occupied blocks per task id
> system.cpu.icache.tags.age_task_id_blocks_1024::1 174 # Occupied blocks per task id
702,740c702,740
< system.cpu.icache.tags.tag_accesses 4426 # Number of tag accesses
< system.cpu.icache.tags.data_accesses 4426 # Number of data accesses
< system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
< system.cpu.icache.ReadReq_hits::cpu.inst 1610 # number of ReadReq hits
< system.cpu.icache.ReadReq_hits::total 1610 # number of ReadReq hits
< system.cpu.icache.demand_hits::cpu.inst 1610 # number of demand (read+write) hits
< system.cpu.icache.demand_hits::total 1610 # number of demand (read+write) hits
< system.cpu.icache.overall_hits::cpu.inst 1610 # number of overall hits
< system.cpu.icache.overall_hits::total 1610 # number of overall hits
< system.cpu.icache.ReadReq_misses::cpu.inst 437 # number of ReadReq misses
< system.cpu.icache.ReadReq_misses::total 437 # number of ReadReq misses
< system.cpu.icache.demand_misses::cpu.inst 437 # number of demand (read+write) misses
< system.cpu.icache.demand_misses::total 437 # number of demand (read+write) misses
< system.cpu.icache.overall_misses::cpu.inst 437 # number of overall misses
< system.cpu.icache.overall_misses::total 437 # number of overall misses
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 32774000 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 32774000 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 32774000 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 32774000 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 32774000 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 32774000 # number of overall miss cycles
< system.cpu.icache.ReadReq_accesses::cpu.inst 2047 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.ReadReq_accesses::total 2047 # number of ReadReq accesses(hits+misses)
< system.cpu.icache.demand_accesses::cpu.inst 2047 # number of demand (read+write) accesses
< system.cpu.icache.demand_accesses::total 2047 # number of demand (read+write) accesses
< system.cpu.icache.overall_accesses::cpu.inst 2047 # number of overall (read+write) accesses
< system.cpu.icache.overall_accesses::total 2047 # number of overall (read+write) accesses
< system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213483 # miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_miss_rate::total 0.213483 # miss rate for ReadReq accesses
< system.cpu.icache.demand_miss_rate::cpu.inst 0.213483 # miss rate for demand accesses
< system.cpu.icache.demand_miss_rate::total 0.213483 # miss rate for demand accesses
< system.cpu.icache.overall_miss_rate::cpu.inst 0.213483 # miss rate for overall accesses
< system.cpu.icache.overall_miss_rate::total 0.213483 # miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 74997.711670 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 74997.711670 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 74997.711670 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 74997.711670 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 74997.711670 # average overall miss latency
---
> system.cpu.icache.tags.tag_accesses 4432 # Number of tag accesses
> system.cpu.icache.tags.data_accesses 4432 # Number of data accesses
> system.cpu.icache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
> system.cpu.icache.ReadReq_hits::cpu.inst 1612 # number of ReadReq hits
> system.cpu.icache.ReadReq_hits::total 1612 # number of ReadReq hits
> system.cpu.icache.demand_hits::cpu.inst 1612 # number of demand (read+write) hits
> system.cpu.icache.demand_hits::total 1612 # number of demand (read+write) hits
> system.cpu.icache.overall_hits::cpu.inst 1612 # number of overall hits
> system.cpu.icache.overall_hits::total 1612 # number of overall hits
> system.cpu.icache.ReadReq_misses::cpu.inst 438 # number of ReadReq misses
> system.cpu.icache.ReadReq_misses::total 438 # number of ReadReq misses
> system.cpu.icache.demand_misses::cpu.inst 438 # number of demand (read+write) misses
> system.cpu.icache.demand_misses::total 438 # number of demand (read+write) misses
> system.cpu.icache.overall_misses::cpu.inst 438 # number of overall misses
> system.cpu.icache.overall_misses::total 438 # number of overall misses
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 33275000 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 33275000 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 33275000 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 33275000 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 33275000 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 33275000 # number of overall miss cycles
> system.cpu.icache.ReadReq_accesses::cpu.inst 2050 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.ReadReq_accesses::total 2050 # number of ReadReq accesses(hits+misses)
> system.cpu.icache.demand_accesses::cpu.inst 2050 # number of demand (read+write) accesses
> system.cpu.icache.demand_accesses::total 2050 # number of demand (read+write) accesses
> system.cpu.icache.overall_accesses::cpu.inst 2050 # number of overall (read+write) accesses
> system.cpu.icache.overall_accesses::total 2050 # number of overall (read+write) accesses
> system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.213659 # miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_miss_rate::total 0.213659 # miss rate for ReadReq accesses
> system.cpu.icache.demand_miss_rate::cpu.inst 0.213659 # miss rate for demand accesses
> system.cpu.icache.demand_miss_rate::total 0.213659 # miss rate for demand accesses
> system.cpu.icache.overall_miss_rate::cpu.inst 0.213659 # miss rate for overall accesses
> system.cpu.icache.overall_miss_rate::total 0.213659 # miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75970.319635 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 75970.319635 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 75970.319635 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 75970.319635 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 75970.319635 # average overall miss latency
749,754c749,754
< system.cpu.icache.ReadReq_mshr_hits::cpu.inst 105 # number of ReadReq MSHR hits
< system.cpu.icache.ReadReq_mshr_hits::total 105 # number of ReadReq MSHR hits
< system.cpu.icache.demand_mshr_hits::cpu.inst 105 # number of demand (read+write) MSHR hits
< system.cpu.icache.demand_mshr_hits::total 105 # number of demand (read+write) MSHR hits
< system.cpu.icache.overall_mshr_hits::cpu.inst 105 # number of overall MSHR hits
< system.cpu.icache.overall_mshr_hits::total 105 # number of overall MSHR hits
---
> system.cpu.icache.ReadReq_mshr_hits::cpu.inst 106 # number of ReadReq MSHR hits
> system.cpu.icache.ReadReq_mshr_hits::total 106 # number of ReadReq MSHR hits
> system.cpu.icache.demand_mshr_hits::cpu.inst 106 # number of demand (read+write) MSHR hits
> system.cpu.icache.demand_mshr_hits::total 106 # number of demand (read+write) MSHR hits
> system.cpu.icache.overall_mshr_hits::cpu.inst 106 # number of overall MSHR hits
> system.cpu.icache.overall_mshr_hits::total 106 # number of overall MSHR hits
761,779c761,779
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26055500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 26055500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26055500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 26055500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26055500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 26055500 # number of overall MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for ReadReq accesses
< system.cpu.icache.ReadReq_mshr_miss_rate::total 0.162189 # mshr miss rate for ReadReq accesses
< system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for demand accesses
< system.cpu.icache.demand_mshr_miss_rate::total 0.162189 # mshr miss rate for demand accesses
< system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.162189 # mshr miss rate for overall accesses
< system.cpu.icache.overall_mshr_miss_rate::total 0.162189 # mshr miss rate for overall accesses
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78480.421687 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78480.421687 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78480.421687 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 78480.421687 # average overall mshr miss latency
< system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 26133000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 26133000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 26133000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 26133000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 26133000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 26133000 # number of overall MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for ReadReq accesses
> system.cpu.icache.ReadReq_mshr_miss_rate::total 0.161951 # mshr miss rate for ReadReq accesses
> system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for demand accesses
> system.cpu.icache.demand_mshr_miss_rate::total 0.161951 # mshr miss rate for demand accesses
> system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.161951 # mshr miss rate for overall accesses
> system.cpu.icache.overall_mshr_miss_rate::total 0.161951 # mshr miss rate for overall accesses
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78713.855422 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78713.855422 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78713.855422 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 78713.855422 # average overall mshr miss latency
> system.cpu.l2cache.tags.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
781c781
< system.cpu.l2cache.tags.tagsinuse 218.003826 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 251.694203 # Cycle average of tags in use
783,784c783,784
< system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
< system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
---
> system.cpu.l2cache.tags.sampled_refs 469 # Sample count of references to valid blocks.
> system.cpu.l2cache.tags.avg_refs 0.042644 # Average number of references to valid blocks.
786,794c786,794
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.713393 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.290433 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004905 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::cpu.data 0.001748 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_percent::total 0.006653 # Average percentage of cache occupancy
< system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::0 181 # Occupied blocks per task id
< system.cpu.l2cache.tags.age_task_id_blocks_1024::1 238 # Occupied blocks per task id
< system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 160.892029 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 90.802174 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004910 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::cpu.data 0.002771 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_percent::total 0.007681 # Average percentage of cache occupancy
> system.cpu.l2cache.tags.occ_task_id_blocks::1024 469 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::0 187 # Occupied blocks per task id
> system.cpu.l2cache.tags.age_task_id_blocks_1024::1 282 # Occupied blocks per task id
> system.cpu.l2cache.tags.occ_task_id_percent::1024 0.014313 # Percentage of cache occupancy per task id
797c797
< system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.cpu.l2cache.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
818,829c818,829
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4007000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25524500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadCleanReq_miss_latency::total 25524500 # number of ReadCleanReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7412000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.ReadSharedReq_miss_latency::total 7412000 # number of ReadSharedReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 25524500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11419000 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 36943500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 25524500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11419000 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 36943500 # number of overall miss cycles
---
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4057000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4057000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25602000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadCleanReq_miss_latency::total 25602000 # number of ReadCleanReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7760000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.ReadSharedReq_miss_latency::total 7760000 # number of ReadSharedReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 25602000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11817000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 37419000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 25602000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11817000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 37419000 # number of overall miss cycles
856,867c856,867
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80140 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80140 # average ReadExReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77582.066869 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77582.066869 # average ReadCleanReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 82355.555556 # average ReadSharedReq miss latency
< system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 82355.555556 # average ReadSharedReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 78770.788913 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77582.066869 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81564.285714 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 78770.788913 # average overall miss latency
---
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 81140 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 81140 # average ReadExReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77817.629179 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77817.629179 # average ReadCleanReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 86222.222222 # average ReadSharedReq miss latency
> system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 86222.222222 # average ReadSharedReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 79784.648188 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77817.629179 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 84407.142857 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 79784.648188 # average overall miss latency
886,897c886,897
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507000 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22234500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22234500 # number of ReadCleanReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6512000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6512000 # number of ReadSharedReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22234500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10019000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 32253500 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22234500 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10019000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 32253500 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3557000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3557000 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22312000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22312000 # number of ReadCleanReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6860000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6860000 # number of ReadSharedReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22312000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10417000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 32729000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22312000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10417000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 32729000 # number of overall MSHR miss cycles
910,921c910,921
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70140 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70140 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67582.066869 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67582.066869 # average ReadCleanReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 72355.555556 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 72355.555556 # average ReadSharedReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67582.066869 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71564.285714 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68770.788913 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 71140 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 71140 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67817.629179 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67817.629179 # average ReadCleanReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 76222.222222 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 76222.222222 # average ReadSharedReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67817.629179 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 74407.142857 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 69784.648188 # average overall mshr miss latency
928c928
< system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.cpu.toL2Bus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
955c955
< system.cpu.toL2Bus.reqLayer0.utilization 1.2 # Layer utilization (%)
---
> system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
960c960,966
< system.membus.pwrStateResidencyTicks::UNDEFINED 22532000 # Cumulative time (in ticks) in various power states
---
> system.membus.snoop_filter.tot_requests 469 # Total number of requests made to the snoop filter.
> system.membus.snoop_filter.hit_single_requests 0 # Number of requests hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
> system.membus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
> system.membus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
> system.membus.pwrStateResidencyTicks::UNDEFINED 22838000 # Cumulative time (in ticks) in various power states
981,984c987,990
< system.membus.reqLayer0.occupancy 582000 # Layer occupancy (ticks)
< system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
< system.membus.respLayer1.occupancy 2494000 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
---
> system.membus.reqLayer0.occupancy 581500 # Layer occupancy (ticks)
> system.membus.reqLayer0.utilization 2.5 # Layer utilization (%)
> system.membus.respLayer1.occupancy 2494250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 10.9 # Layer utilization (%)