7,11c7,11
< host_inst_rate 39362 # Simulator instruction rate (inst/s)
< host_op_rate 39354 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 164927772 # Simulator tick rate (ticks/s)
< host_mem_usage 235848 # Number of bytes of host memory used
< host_seconds 0.13 # Real time elapsed on the host
---
> host_inst_rate 87050 # Simulator instruction rate (inst/s)
> host_op_rate 87030 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 364707967 # Simulator tick rate (ticks/s)
> host_mem_usage 288672 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
202,203c202,203
< system.physmem.totQLat 5548500 # Total ticks spent queuing
< system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 5601000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst
229d228
< system.membus.throughput 1418504037 # Throughput (bytes/s)
236,239c235,247
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 30656 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 479 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 479 # Request fanout histogram
242c250
< system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks)
565d572
< system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s)
573,577c580,594
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
585c602
< system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use
590,592c607,609
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy
611,616c628,633
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles
629,634c646,651
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency
655,660c672,677
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles
667,672c684,689
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency
675c692
< system.cpu.l2cache.tags.tagsinuse 222.300532 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use
680,681c697,698
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685875 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor
708,718c725,735
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24254500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7288250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 31542750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24254500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11346250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 35600750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24254500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11346250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 35600750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles
741,751c758,768
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71971.810089 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80090.659341 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73698.014019 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79568.627451 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79568.627451 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74323.068894 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency
771,781c788,798
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19999000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6168250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26167250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3423500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3423500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19999000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9591750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29590750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19999000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9591750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29590750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles
793,803c810,820
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
806c823
< system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use
811c828
< system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor
836,843c853,860
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles
860,867c877,884
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency
892,899c909,916
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles
908,915c925,932
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency
< host_inst_rate 39362 # Simulator instruction rate (inst/s)
< host_op_rate 39354 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 164927772 # Simulator tick rate (ticks/s)
< host_mem_usage 235848 # Number of bytes of host memory used
< host_seconds 0.13 # Real time elapsed on the host
---
> host_inst_rate 87050 # Simulator instruction rate (inst/s)
> host_op_rate 87030 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 364707967 # Simulator tick rate (ticks/s)
> host_mem_usage 288672 # Number of bytes of host memory used
> host_seconds 0.06 # Real time elapsed on the host
202,203c202,203
< system.physmem.totQLat 5548500 # Total ticks spent queuing
< system.physmem.totMemAccLat 14529750 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.totQLat 5601000 # Total ticks spent queuing
> system.physmem.totMemAccLat 14582250 # Total ticks spent from burst creation until serviced by the DRAM
205c205
< system.physmem.avgQLat 11583.51 # Average queueing delay per DRAM burst
---
> system.physmem.avgQLat 11693.11 # Average queueing delay per DRAM burst
207c207
< system.physmem.avgMemAccLat 30333.51 # Average memory access latency per DRAM burst
---
> system.physmem.avgMemAccLat 30443.11 # Average memory access latency per DRAM burst
229d228
< system.membus.throughput 1418504037 # Throughput (bytes/s)
236,239c235,247
< system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes)
< system.membus.tot_pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
< system.membus.data_through_bus 30656 # Total data (bytes)
< system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30656 # Cumulative packet size per connected master and slave (bytes)
> system.membus.pkt_size::total 30656 # Cumulative packet size per connected master and slave (bytes)
> system.membus.snoops 0 # Total snoops (count)
> system.membus.snoop_fanout::samples 479 # Request fanout histogram
> system.membus.snoop_fanout::mean 0 # Request fanout histogram
> system.membus.snoop_fanout::stdev 0 # Request fanout histogram
> system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.membus.snoop_fanout::0 479 100.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.membus.snoop_fanout::min_value 0 # Request fanout histogram
> system.membus.snoop_fanout::max_value 0 # Request fanout histogram
> system.membus.snoop_fanout::total 479 # Request fanout histogram
242c250
< system.membus.respLayer1.occupancy 4492750 # Layer occupancy (ticks)
---
> system.membus.respLayer1.occupancy 4492250 # Layer occupancy (ticks)
565d572
< system.cpu.toL2Bus.throughput 1427388196 # Throughput (bytes/s)
573,577c580,594
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.tot_pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
< system.cpu.toL2Bus.data_through_bus 30848 # Total data (bytes)
< system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
---
> system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21760 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.pkt_size::total 30848 # Cumulative packet size per connected master and slave (bytes)
> system.cpu.toL2Bus.snoops 0 # Total snoops (count)
> system.cpu.toL2Bus.snoop_fanout::samples 482 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::1 482 100.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
> system.cpu.toL2Bus.snoop_fanout::total 482 # Request fanout histogram
585c602
< system.cpu.icache.tags.tagsinuse 161.374264 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.371303 # Cycle average of tags in use
590,592c607,609
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.374264 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078796 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078796 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.371303 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078795 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078795 # Average percentage of cache occupancy
611,616c628,633
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31448500 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31448500 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31448500 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31448500 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31448500 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31448500 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31446500 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31446500 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31446500 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31446500 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31446500 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31446500 # number of overall miss cycles
629,634c646,651
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69422.737307 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69422.737307 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69422.737307 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69422.737307 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69422.737307 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69418.322296 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69418.322296 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69418.322296 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69418.322296 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69418.322296 # average overall miss latency
655,660c672,677
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24624500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24624500 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24624500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24624500 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24624500 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24624500 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24622500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24622500 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24622500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24622500 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24622500 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24622500 # number of overall MSHR miss cycles
667,672c684,689
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72425 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72425 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72425 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 72425 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 72419.117647 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 72419.117647 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 72419.117647 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 72419.117647 # average overall mshr miss latency
675c692
< system.cpu.l2cache.tags.tagsinuse 222.300532 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 222.296900 # Cycle average of tags in use
680,681c697,698
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.614658 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685875 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.611488 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 58.685412 # Average occupied blocks per requestor
708,718c725,735
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24254500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7288250 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 31542750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 4058000 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 24254500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 11346250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 35600750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 24254500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 11346250 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 35600750 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 24252500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7286250 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 31538750 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4056000 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 4056000 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 24252500 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 11342250 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 35594750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 24252500 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 11342250 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 35594750 # number of overall miss cycles
741,751c758,768
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71971.810089 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80090.659341 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 73698.014019 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79568.627451 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79568.627451 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 74323.068894 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71971.810089 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79903.169014 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 74323.068894 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71965.875371 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 80068.681319 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 73688.668224 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 79529.411765 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 79529.411765 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 79875 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 74310.542797 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71965.875371 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 79875 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 74310.542797 # average overall miss latency
771,781c788,798
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19999000 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6168250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26167250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3423500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3423500 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19999000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9591750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 29590750 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19999000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9591750 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 29590750 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19997500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 6166250 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 26163750 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3421500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3421500 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19997500 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9587750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 29585250 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19997500 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9587750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 29585250 # number of overall MSHR miss cycles
793,803c810,820
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59344.213650 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67782.967033 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61138.434579 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67127.450980 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67127.450980 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59344.213650 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67547.535211 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61776.096033 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 59339.762611 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 67760.989011 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 61130.257009 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 67088.235294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 67088.235294 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 59339.762611 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 67519.366197 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 61764.613779 # average overall mshr miss latency
806c823
< system.cpu.dcache.tags.tagsinuse 92.430317 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 92.429669 # Cycle average of tags in use
811c828
< system.cpu.dcache.tags.occ_blocks::cpu.data 92.430317 # Average occupied blocks per requestor
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 92.429669 # Average occupied blocks per requestor
836,843c853,860
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 11709000 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 11709000 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 23266249 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 23266249 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 34975249 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 34975249 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 34975249 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 34975249 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 11707000 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 11707000 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 23264249 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 23264249 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 34971249 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 34971249 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 34971249 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 34971249 # number of overall miss cycles
860,867c877,884
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69284.023669 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69284.023669 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64271.406077 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 64271.406077 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 65866.758945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 65866.758945 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 65866.758945 # average overall miss latency
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69272.189349 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69272.189349 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 64265.881215 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 64265.881215 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 65859.225989 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 65859.225989 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 65859.225989 # average overall miss latency
892,899c909,916
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7382750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7382750 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4109999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 4109999 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11492749 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11492749 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11492749 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11492749 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7380750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7380750 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4107999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 4107999 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11488749 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 11488749 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11488749 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 11488749 # number of overall MSHR miss cycles
908,915c925,932
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81129.120879 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81129.120879 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80588.215686 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80588.215686 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80934.852113 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 80934.852113 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 81107.142857 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 81107.142857 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 80549 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 80549 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 80906.683099 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 80906.683099 # average overall mshr miss latency