4,5c4,5
< sim_ticks 21918500 # Number of ticks simulated
< final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21843500 # Number of ticks simulated
> final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 56826 # Simulator instruction rate (inst/s)
< host_op_rate 56817 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 241494238 # Simulator tick rate (ticks/s)
< host_mem_usage 266500 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 63396 # Simulator instruction rate (inst/s)
> host_op_rate 63384 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 268482897 # Simulator tick rate (ticks/s)
> host_mem_usage 267540 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 21839000 # Total gap between requests
---
> system.physmem.totGap 21764000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
96,97c96,97
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
189,203c189,204
< system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation
< system.physmem.totQLat 2715000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation
> system.physmem.totQLat 4715500 # Total ticks spent queuing
> system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM
205,207c206
< system.physmem.totBankLat 8676250 # Total ticks spent accessing banks
< system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst
209,210c208,209
< system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s
212c211
< system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.physmem.busUtil 10.88 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads
224c223
< system.physmem.avgGap 45784.07 # Average gap between requests
---
> system.physmem.avgGap 45626.83 # Average gap between requests
226,227c225,230
< system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1392796040 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15319000 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1397578227 # Throughput (bytes/s)
238c241
< system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks)
240,241c243,244
< system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 20.5 # Layer utilization (%)
271c274
< system.cpu.numCycles 43838 # number of cpu cycles simulated
---
> system.cpu.numCycles 43688 # number of cpu cycles simulated
280c283
< system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked
284,286c287,289
< system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total)
288,291c291,294
< system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total)
300,302c303,305
< system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle
---
> system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle
304c307
< system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked
314,315c317,318
< system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
342,344c345,347
< system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle
346,349c349,352
< system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle
358c361
< system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle
428c431
< system.cpu.iq.rate 0.189174 # Inst issue rate
---
> system.cpu.iq.rate 0.189823 # Inst issue rate
431c434
< system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads
472c475
< system.cpu.iew.exec_rate 0.180483 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.181102 # Inst execution rate
478c481
< system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle
484,486c487,489
< system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle
488c491
< system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle
500c503
< system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle
510a514,548
> system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5813 # Class of committed instruction
513c551
< system.cpu.rob.rob_reads 24245 # The number of ROB reads
---
> system.cpu.rob.rob_reads 24239 # The number of ROB reads
515,516c553,554
< system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling
520,523c558,561
< system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads
529c567
< system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s)
544c582
< system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks)
546c584
< system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks)
549c587
< system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use
554,556c592,594
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy
575,580c613,618
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles
593,598c631,636
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency
619,624c657,662
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles
631,636c669,674
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
639c677
< system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use
644,645c682,683
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor
648c686
< system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy
672,682c710,720
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles
705,715c743,753
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency
735,745c773,783
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles
757,767c795,805
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
770c808
< system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use
775,777c813,815
< system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy
800,807c838,845
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles
824,832c862,870
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
836c874
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked
856,863c894,901
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles
872,879c910,917
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
< sim_ticks 21918500 # Number of ticks simulated
< final_tick 21918500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
---
> sim_ticks 21843500 # Number of ticks simulated
> final_tick 21843500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
7,11c7,11
< host_inst_rate 56826 # Simulator instruction rate (inst/s)
< host_op_rate 56817 # Simulator op (including micro ops) rate (op/s)
< host_tick_rate 241494238 # Simulator tick rate (ticks/s)
< host_mem_usage 266500 # Number of bytes of host memory used
< host_seconds 0.09 # Real time elapsed on the host
---
> host_inst_rate 63396 # Simulator instruction rate (inst/s)
> host_op_rate 63384 # Simulator op (including micro ops) rate (op/s)
> host_tick_rate 268482897 # Simulator tick rate (ticks/s)
> host_mem_usage 267540 # Number of bytes of host memory used
> host_seconds 0.08 # Real time elapsed on the host
24,31c24,31
< system.physmem.bw_read::cpu.inst 978169127 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::cpu.data 414626913 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_read::total 1392796040 # Total read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::cpu.inst 978169127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_inst_read::total 978169127 # Instruction read bandwidth from this memory (bytes/s)
< system.physmem.bw_total::cpu.inst 978169127 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::cpu.data 414626913 # Total bandwidth to/from this memory (bytes/s)
< system.physmem.bw_total::total 1392796040 # Total bandwidth to/from this memory (bytes/s)
---
> system.physmem.bw_read::cpu.inst 981527686 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::cpu.data 416050541 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_read::total 1397578227 # Total read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::cpu.inst 981527686 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_inst_read::total 981527686 # Instruction read bandwidth from this memory (bytes/s)
> system.physmem.bw_total::cpu.inst 981527686 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::cpu.data 416050541 # Total bandwidth to/from this memory (bytes/s)
> system.physmem.bw_total::total 1397578227 # Total bandwidth to/from this memory (bytes/s)
78c78
< system.physmem.totGap 21839000 # Total gap between requests
---
> system.physmem.totGap 21764000 # Total gap between requests
93,94c93,94
< system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::0 284 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::1 133 # What read queue length does an incoming req see
96,97c96,97
< system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
< system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
---
> system.physmem.rdQLenPdf::3 14 # What read queue length does an incoming req see
> system.physmem.rdQLenPdf::4 5 # What read queue length does an incoming req see
189,203c189,204
< system.physmem.bytesPerActivate::samples 87 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::mean 246.436782 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::gmean 168.540369 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::stdev 250.647056 # Bytes accessed per row activation
< system.physmem.bytesPerActivate::0-127 26 29.89% 29.89% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::128-255 32 36.78% 66.67% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::256-383 13 14.94% 81.61% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::384-511 6 6.90% 88.51% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::512-639 2 2.30% 90.80% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::640-767 1 1.15% 91.95% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::768-895 2 2.30% 94.25% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::1024-1151 5 5.75% 100.00% # Bytes accessed per row activation
< system.physmem.bytesPerActivate::total 87 # Bytes accessed per row activation
< system.physmem.totQLat 2715000 # Total ticks spent queuing
< system.physmem.totMemAccLat 13776250 # Total ticks spent from burst creation until serviced by the DRAM
---
> system.physmem.bytesPerActivate::samples 109 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::mean 254.238532 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::gmean 174.990405 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::stdev 249.769927 # Bytes accessed per row activation
> system.physmem.bytesPerActivate::0-127 31 28.44% 28.44% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::128-255 40 36.70% 65.14% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::256-383 16 14.68% 79.82% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::384-511 8 7.34% 87.16% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::512-639 4 3.67% 90.83% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::640-767 1 0.92% 91.74% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::768-895 3 2.75% 94.50% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::896-1023 1 0.92% 95.41% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::1024-1151 5 4.59% 100.00% # Bytes accessed per row activation
> system.physmem.bytesPerActivate::total 109 # Bytes accessed per row activation
> system.physmem.totQLat 4715500 # Total ticks spent queuing
> system.physmem.totMemAccLat 13659250 # Total ticks spent from burst creation until serviced by the DRAM
205,207c206
< system.physmem.totBankLat 8676250 # Total ticks spent accessing banks
< system.physmem.avgQLat 5691.82 # Average queueing delay per DRAM burst
< system.physmem.avgBankLat 18189.20 # Average bank access latency per DRAM burst
---
> system.physmem.avgQLat 9885.74 # Average queueing delay per DRAM burst
209,210c208,209
< system.physmem.avgMemAccLat 28881.03 # Average memory access latency per DRAM burst
< system.physmem.avgRdBW 1392.80 # Average DRAM read bandwidth in MiByte/s
---
> system.physmem.avgMemAccLat 28635.74 # Average memory access latency per DRAM burst
> system.physmem.avgRdBW 1397.58 # Average DRAM read bandwidth in MiByte/s
212c211
< system.physmem.avgRdBWSys 1392.80 # Average system read bandwidth in MiByte/s
---
> system.physmem.avgRdBWSys 1397.58 # Average system read bandwidth in MiByte/s
215,216c214,215
< system.physmem.busUtil 10.88 # Data bus utilization in percentage
< system.physmem.busUtilRead 10.88 # Data bus utilization in percentage for reads
---
> system.physmem.busUtil 10.92 # Data bus utilization in percentage
> system.physmem.busUtilRead 10.92 # Data bus utilization in percentage for reads
224c223
< system.physmem.avgGap 45784.07 # Average gap between requests
---
> system.physmem.avgGap 45626.83 # Average gap between requests
226,227c225,230
< system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
< system.membus.throughput 1392796040 # Throughput (bytes/s)
---
> system.physmem.memoryStateTime::IDLE 11000 # Time in different power states
> system.physmem.memoryStateTime::REF 520000 # Time in different power states
> system.physmem.memoryStateTime::PRE_PDN 0 # Time in different power states
> system.physmem.memoryStateTime::ACT 15319000 # Time in different power states
> system.physmem.memoryStateTime::ACT_PDN 0 # Time in different power states
> system.membus.throughput 1397578227 # Throughput (bytes/s)
238c241
< system.membus.reqLayer0.occupancy 605000 # Layer occupancy (ticks)
---
> system.membus.reqLayer0.occupancy 604500 # Layer occupancy (ticks)
240,241c243,244
< system.membus.respLayer1.occupancy 4473250 # Layer occupancy (ticks)
< system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
---
> system.membus.respLayer1.occupancy 4474250 # Layer occupancy (ticks)
> system.membus.respLayer1.utilization 20.5 # Layer utilization (%)
271c274
< system.cpu.numCycles 43838 # number of cpu cycles simulated
---
> system.cpu.numCycles 43688 # number of cpu cycles simulated
280c283
< system.cpu.fetch.BlockedCycles 1408 # Number of cycles fetch has spent blocked
---
> system.cpu.fetch.BlockedCycles 1402 # Number of cycles fetch has spent blocked
284,286c287,289
< system.cpu.fetch.rateDist::samples 14505 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::mean 0.908859 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::stdev 2.220900 # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::samples 14499 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::mean 0.909235 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::stdev 2.221283 # Number of instructions fetched each cycle (Total)
288,291c291,294
< system.cpu.fetch.rateDist::0 11292 77.85% 77.85% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::1 1317 9.08% 86.93% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::2 104 0.72% 87.65% # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.rateDist::3 131 0.90% 88.55% # Number of instructions fetched each cycle (Total)
---
> system.cpu.fetch.rateDist::0 11286 77.84% 77.84% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::1 1317 9.08% 86.92% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::2 104 0.72% 87.64% # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.rateDist::3 131 0.90% 88.54% # Number of instructions fetched each cycle (Total)
300,302c303,305
< system.cpu.fetch.rateDist::total 14505 # Number of instructions fetched each cycle (Total)
< system.cpu.fetch.branchRate 0.049592 # Number of branch fetches per cycle
< system.cpu.fetch.rate 0.300721 # Number of inst fetches per cycle
---
> system.cpu.fetch.rateDist::total 14499 # Number of instructions fetched each cycle (Total)
> system.cpu.fetch.branchRate 0.049762 # Number of branch fetches per cycle
> system.cpu.fetch.rate 0.301753 # Number of inst fetches per cycle
304c307
< system.cpu.decode.BlockedCycles 1660 # Number of cycles decode is blocked
---
> system.cpu.decode.BlockedCycles 1654 # Number of cycles decode is blocked
314,315c317,318
< system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
< system.cpu.rename.serializeStallCycles 983 # count of cycles rename stalled for serializing inst
---
> system.cpu.rename.BlockCycles 531 # Number of cycles rename is blocking
> system.cpu.rename.serializeStallCycles 973 # count of cycles rename stalled for serializing inst
342,344c345,347
< system.cpu.iq.issued_per_cycle::samples 14505 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::mean 0.571734 # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::stdev 1.240341 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::samples 14499 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::mean 0.571970 # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::stdev 1.240543 # Number of insts issued each cycle
346,349c349,352
< system.cpu.iq.issued_per_cycle::0 10922 75.30% 75.30% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::1 1422 9.80% 85.10% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::2 891 6.14% 91.24% # Number of insts issued each cycle
< system.cpu.iq.issued_per_cycle::3 553 3.81% 95.06% # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::0 10916 75.29% 75.29% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::1 1422 9.81% 85.10% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::2 891 6.15% 91.24% # Number of insts issued each cycle
> system.cpu.iq.issued_per_cycle::3 553 3.81% 95.05% # Number of insts issued each cycle
358c361
< system.cpu.iq.issued_per_cycle::total 14505 # Number of insts issued each cycle
---
> system.cpu.iq.issued_per_cycle::total 14499 # Number of insts issued each cycle
428c431
< system.cpu.iq.rate 0.189174 # Inst issue rate
---
> system.cpu.iq.rate 0.189823 # Inst issue rate
431c434
< system.cpu.iq.int_inst_queue_reads 31286 # Number of integer instruction queue reads
---
> system.cpu.iq.int_inst_queue_reads 31280 # Number of integer instruction queue reads
472c475
< system.cpu.iew.exec_rate 0.180483 # Inst execution rate
---
> system.cpu.iew.exec_rate 0.181102 # Inst execution rate
478c481
< system.cpu.iew.wb_rate 0.170058 # insts written-back per cycle
---
> system.cpu.iew.wb_rate 0.170642 # insts written-back per cycle
484,486c487,489
< system.cpu.commit.committed_per_cycle::samples 13637 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::mean 0.426267 # Number of insts commited each cycle
< system.cpu.commit.committed_per_cycle::stdev 1.206560 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::samples 13631 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::mean 0.426454 # Number of insts commited each cycle
> system.cpu.commit.committed_per_cycle::stdev 1.206792 # Number of insts commited each cycle
488c491
< system.cpu.commit.committed_per_cycle::0 11235 82.39% 82.39% # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::0 11229 82.38% 82.38% # Number of insts commited each cycle
500c503
< system.cpu.commit.committed_per_cycle::total 13637 # Number of insts commited each cycle
---
> system.cpu.commit.committed_per_cycle::total 13631 # Number of insts commited each cycle
510a514,548
> system.cpu.commit.op_class_0::No_OpClass 657 11.30% 11.30% # Class of committed instruction
> system.cpu.commit.op_class_0::IntAlu 3062 52.68% 63.98% # Class of committed instruction
> system.cpu.commit.op_class_0::IntMult 3 0.05% 64.03% # Class of committed instruction
> system.cpu.commit.op_class_0::IntDiv 1 0.02% 64.05% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatAdd 2 0.03% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatDiv 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAdd 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdAlu 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMisc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShift 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 64.08% # Class of committed instruction
> system.cpu.commit.op_class_0::MemRead 1163 20.01% 84.09% # Class of committed instruction
> system.cpu.commit.op_class_0::MemWrite 925 15.91% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
> system.cpu.commit.op_class_0::total 5813 # Class of committed instruction
513c551
< system.cpu.rob.rob_reads 24245 # The number of ROB reads
---
> system.cpu.rob.rob_reads 24239 # The number of ROB reads
515,516c553,554
< system.cpu.timesIdled 286 # Number of times that the entire CPU went into an idle state and unscheduled itself
< system.cpu.idleCycles 29333 # Total number of cycles that the CPU has spent unscheduled due to idling
---
> system.cpu.timesIdled 287 # Number of times that the entire CPU went into an idle state and unscheduled itself
> system.cpu.idleCycles 29189 # Total number of cycles that the CPU has spent unscheduled due to idling
520,523c558,561
< system.cpu.cpi 8.502327 # CPI: Cycles Per Instruction
< system.cpu.cpi_total 8.502327 # CPI: Total CPI of All Threads
< system.cpu.ipc 0.117615 # IPC: Instructions Per Cycle
< system.cpu.ipc_total 0.117615 # IPC: Total IPC of All Threads
---
> system.cpu.cpi 8.473235 # CPI: Cycles Per Instruction
> system.cpu.cpi_total 8.473235 # CPI: Total CPI of All Threads
> system.cpu.ipc 0.118019 # IPC: Instructions Per Cycle
> system.cpu.ipc_total 0.118019 # IPC: Total IPC of All Threads
529c567
< system.cpu.toL2Bus.throughput 1401555763 # Throughput (bytes/s)
---
> system.cpu.toL2Bus.throughput 1406368027 # Throughput (bytes/s)
544c582
< system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer0.occupancy 571500 # Layer occupancy (ticks)
546c584
< system.cpu.toL2Bus.respLayer1.occupancy 227000 # Layer occupancy (ticks)
---
> system.cpu.toL2Bus.respLayer1.occupancy 228250 # Layer occupancy (ticks)
549c587
< system.cpu.icache.tags.tagsinuse 161.390328 # Cycle average of tags in use
---
> system.cpu.icache.tags.tagsinuse 161.382673 # Cycle average of tags in use
554,556c592,594
< system.cpu.icache.tags.occ_blocks::cpu.inst 161.390328 # Average occupied blocks per requestor
< system.cpu.icache.tags.occ_percent::cpu.inst 0.078804 # Average percentage of cache occupancy
< system.cpu.icache.tags.occ_percent::total 0.078804 # Average percentage of cache occupancy
---
> system.cpu.icache.tags.occ_blocks::cpu.inst 161.382673 # Average occupied blocks per requestor
> system.cpu.icache.tags.occ_percent::cpu.inst 0.078800 # Average percentage of cache occupancy
> system.cpu.icache.tags.occ_percent::total 0.078800 # Average percentage of cache occupancy
575,580c613,618
< system.cpu.icache.ReadReq_miss_latency::cpu.inst 31256750 # number of ReadReq miss cycles
< system.cpu.icache.ReadReq_miss_latency::total 31256750 # number of ReadReq miss cycles
< system.cpu.icache.demand_miss_latency::cpu.inst 31256750 # number of demand (read+write) miss cycles
< system.cpu.icache.demand_miss_latency::total 31256750 # number of demand (read+write) miss cycles
< system.cpu.icache.overall_miss_latency::cpu.inst 31256750 # number of overall miss cycles
< system.cpu.icache.overall_miss_latency::total 31256750 # number of overall miss cycles
---
> system.cpu.icache.ReadReq_miss_latency::cpu.inst 31159250 # number of ReadReq miss cycles
> system.cpu.icache.ReadReq_miss_latency::total 31159250 # number of ReadReq miss cycles
> system.cpu.icache.demand_miss_latency::cpu.inst 31159250 # number of demand (read+write) miss cycles
> system.cpu.icache.demand_miss_latency::total 31159250 # number of demand (read+write) miss cycles
> system.cpu.icache.overall_miss_latency::cpu.inst 31159250 # number of overall miss cycles
> system.cpu.icache.overall_miss_latency::total 31159250 # number of overall miss cycles
593,598c631,636
< system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69305.432373 # average ReadReq miss latency
< system.cpu.icache.ReadReq_avg_miss_latency::total 69305.432373 # average ReadReq miss latency
< system.cpu.icache.demand_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
< system.cpu.icache.demand_avg_miss_latency::total 69305.432373 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::cpu.inst 69305.432373 # average overall miss latency
< system.cpu.icache.overall_avg_miss_latency::total 69305.432373 # average overall miss latency
---
> system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69089.246120 # average ReadReq miss latency
> system.cpu.icache.ReadReq_avg_miss_latency::total 69089.246120 # average ReadReq miss latency
> system.cpu.icache.demand_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
> system.cpu.icache.demand_avg_miss_latency::total 69089.246120 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::cpu.inst 69089.246120 # average overall miss latency
> system.cpu.icache.overall_avg_miss_latency::total 69089.246120 # average overall miss latency
619,624c657,662
< system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24262750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.ReadReq_mshr_miss_latency::total 24262750 # number of ReadReq MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24262750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.demand_mshr_miss_latency::total 24262750 # number of demand (read+write) MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24262750 # number of overall MSHR miss cycles
< system.cpu.icache.overall_mshr_miss_latency::total 24262750 # number of overall MSHR miss cycles
---
> system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24154000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.ReadReq_mshr_miss_latency::total 24154000 # number of ReadReq MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24154000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.demand_mshr_miss_latency::total 24154000 # number of demand (read+write) MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24154000 # number of overall MSHR miss cycles
> system.cpu.icache.overall_mshr_miss_latency::total 24154000 # number of overall MSHR miss cycles
631,636c669,674
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71783.284024 # average ReadReq mshr miss latency
< system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71783.284024 # average ReadReq mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
< system.cpu.icache.demand_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71783.284024 # average overall mshr miss latency
< system.cpu.icache.overall_avg_mshr_miss_latency::total 71783.284024 # average overall mshr miss latency
---
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71461.538462 # average ReadReq mshr miss latency
> system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71461.538462 # average ReadReq mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
> system.cpu.icache.demand_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71461.538462 # average overall mshr miss latency
> system.cpu.icache.overall_avg_mshr_miss_latency::total 71461.538462 # average overall mshr miss latency
639c677
< system.cpu.l2cache.tags.tagsinuse 221.496759 # Cycle average of tags in use
---
> system.cpu.l2cache.tags.tagsinuse 221.484913 # Cycle average of tags in use
644,645c682,683
< system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.678282 # Average occupied blocks per requestor
< system.cpu.l2cache.tags.occ_blocks::cpu.data 57.818477 # Average occupied blocks per requestor
---
> system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.674419 # Average occupied blocks per requestor
> system.cpu.l2cache.tags.occ_blocks::cpu.data 57.810494 # Average occupied blocks per requestor
648c686
< system.cpu.l2cache.tags.occ_percent::total 0.006760 # Average percentage of cache occupancy
---
> system.cpu.l2cache.tags.occ_percent::total 0.006759 # Average percentage of cache occupancy
672,682c710,720
< system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23894750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7065750 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadReq_miss_latency::total 30960500 # number of ReadReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3800750 # number of ReadExReq miss cycles
< system.cpu.l2cache.ReadExReq_miss_latency::total 3800750 # number of ReadExReq miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.inst 23894750 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::cpu.data 10866500 # number of demand (read+write) miss cycles
< system.cpu.l2cache.demand_miss_latency::total 34761250 # number of demand (read+write) miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.inst 23894750 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::cpu.data 10866500 # number of overall miss cycles
< system.cpu.l2cache.overall_miss_latency::total 34761250 # number of overall miss cycles
---
> system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23786000 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7056500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadReq_miss_latency::total 30842500 # number of ReadReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3776250 # number of ReadExReq miss cycles
> system.cpu.l2cache.ReadExReq_miss_latency::total 3776250 # number of ReadExReq miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.inst 23786000 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::cpu.data 10832750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.demand_miss_latency::total 34618750 # number of demand (read+write) miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.inst 23786000 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::cpu.data 10832750 # number of overall miss cycles
> system.cpu.l2cache.overall_miss_latency::total 34618750 # number of overall miss cycles
705,715c743,753
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71327.611940 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77645.604396 # average ReadReq miss latency
< system.cpu.l2cache.ReadReq_avg_miss_latency::total 72677.230047 # average ReadReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74524.509804 # average ReadExReq miss latency
< system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74524.509804 # average ReadExReq miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
< system.cpu.l2cache.demand_avg_miss_latency::total 72874.737945 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71327.611940 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76524.647887 # average overall miss latency
< system.cpu.l2cache.overall_avg_miss_latency::total 72874.737945 # average overall miss latency
---
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71002.985075 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77543.956044 # average ReadReq miss latency
> system.cpu.l2cache.ReadReq_avg_miss_latency::total 72400.234742 # average ReadReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74044.117647 # average ReadExReq miss latency
> system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74044.117647 # average ReadExReq miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
> system.cpu.l2cache.demand_avg_miss_latency::total 72575.995807 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71002.985075 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76286.971831 # average overall miss latency
> system.cpu.l2cache.overall_avg_miss_latency::total 72575.995807 # average overall miss latency
735,745c773,783
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19660250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5948250 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25608500 # number of ReadReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3170750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3170750 # number of ReadExReq MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19660250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9119000 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.demand_mshr_miss_latency::total 28779250 # number of demand (read+write) MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19660250 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9119000 # number of overall MSHR miss cycles
< system.cpu.l2cache.overall_mshr_miss_latency::total 28779250 # number of overall MSHR miss cycles
---
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19551000 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5938500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25489500 # number of ReadReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3144250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3144250 # number of ReadExReq MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19551000 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9082750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.demand_mshr_miss_latency::total 28633750 # number of demand (read+write) MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19551000 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9082750 # number of overall MSHR miss cycles
> system.cpu.l2cache.overall_mshr_miss_latency::total 28633750 # number of overall MSHR miss cycles
757,767c795,805
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58687.313433 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65365.384615 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 60113.849765 # average ReadReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62171.568627 # average ReadExReq mshr miss latency
< system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62171.568627 # average ReadExReq mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
< system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58687.313433 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64218.309859 # average overall mshr miss latency
< system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60333.857442 # average overall mshr miss latency
---
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58361.194030 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 65258.241758 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59834.507042 # average ReadReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 61651.960784 # average ReadExReq mshr miss latency
> system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 61651.960784 # average ReadExReq mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
> system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58361.194030 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 63963.028169 # average overall mshr miss latency
> system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60028.825996 # average overall mshr miss latency
770c808
< system.cpu.dcache.tags.tagsinuse 91.623425 # Cycle average of tags in use
---
> system.cpu.dcache.tags.tagsinuse 91.603992 # Cycle average of tags in use
775,777c813,815
< system.cpu.dcache.tags.occ_blocks::cpu.data 91.623425 # Average occupied blocks per requestor
< system.cpu.dcache.tags.occ_percent::cpu.data 0.022369 # Average percentage of cache occupancy
< system.cpu.dcache.tags.occ_percent::total 0.022369 # Average percentage of cache occupancy
---
> system.cpu.dcache.tags.occ_blocks::cpu.data 91.603992 # Average occupied blocks per requestor
> system.cpu.dcache.tags.occ_percent::cpu.data 0.022364 # Average percentage of cache occupancy
> system.cpu.dcache.tags.occ_percent::total 0.022364 # Average percentage of cache occupancy
800,807c838,845
< system.cpu.dcache.ReadReq_miss_latency::cpu.data 10261250 # number of ReadReq miss cycles
< system.cpu.dcache.ReadReq_miss_latency::total 10261250 # number of ReadReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::cpu.data 22413999 # number of WriteReq miss cycles
< system.cpu.dcache.WriteReq_miss_latency::total 22413999 # number of WriteReq miss cycles
< system.cpu.dcache.demand_miss_latency::cpu.data 32675249 # number of demand (read+write) miss cycles
< system.cpu.dcache.demand_miss_latency::total 32675249 # number of demand (read+write) miss cycles
< system.cpu.dcache.overall_miss_latency::cpu.data 32675249 # number of overall miss cycles
< system.cpu.dcache.overall_miss_latency::total 32675249 # number of overall miss cycles
---
> system.cpu.dcache.ReadReq_miss_latency::cpu.data 10242750 # number of ReadReq miss cycles
> system.cpu.dcache.ReadReq_miss_latency::total 10242750 # number of ReadReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::cpu.data 22302249 # number of WriteReq miss cycles
> system.cpu.dcache.WriteReq_miss_latency::total 22302249 # number of WriteReq miss cycles
> system.cpu.dcache.demand_miss_latency::cpu.data 32544999 # number of demand (read+write) miss cycles
> system.cpu.dcache.demand_miss_latency::total 32544999 # number of demand (read+write) miss cycles
> system.cpu.dcache.overall_miss_latency::cpu.data 32544999 # number of overall miss cycles
> system.cpu.dcache.overall_miss_latency::total 32544999 # number of overall miss cycles
824,832c862,870
< system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69332.770270 # average ReadReq miss latency
< system.cpu.dcache.ReadReq_avg_miss_latency::total 69332.770270 # average ReadReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61917.124309 # average WriteReq miss latency
< system.cpu.dcache.WriteReq_avg_miss_latency::total 61917.124309 # average WriteReq miss latency
< system.cpu.dcache.demand_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
< system.cpu.dcache.demand_avg_miss_latency::total 64069.115686 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::cpu.data 64069.115686 # average overall miss latency
< system.cpu.dcache.overall_avg_miss_latency::total 64069.115686 # average overall miss latency
< system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked
---
> system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 69207.770270 # average ReadReq miss latency
> system.cpu.dcache.ReadReq_avg_miss_latency::total 69207.770270 # average ReadReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 61608.422652 # average WriteReq miss latency
> system.cpu.dcache.WriteReq_avg_miss_latency::total 61608.422652 # average WriteReq miss latency
> system.cpu.dcache.demand_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
> system.cpu.dcache.demand_avg_miss_latency::total 63813.723529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::cpu.data 63813.723529 # average overall miss latency
> system.cpu.dcache.overall_avg_miss_latency::total 63813.723529 # average overall miss latency
> system.cpu.dcache.blocked_cycles::no_mshrs 611 # number of cycles access was blocked
836c874
< system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
---
> system.cpu.dcache.avg_blocked_cycles::no_mshrs 55.545455 # average number of cycles each access was blocked
856,863c894,901
< system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7160250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.ReadReq_mshr_miss_latency::total 7160250 # number of ReadReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3852749 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.WriteReq_mshr_miss_latency::total 3852749 # number of WriteReq MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11012999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.demand_mshr_miss_latency::total 11012999 # number of demand (read+write) MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11012999 # number of overall MSHR miss cycles
< system.cpu.dcache.overall_mshr_miss_latency::total 11012999 # number of overall MSHR miss cycles
---
> system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7151000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.ReadReq_mshr_miss_latency::total 7151000 # number of ReadReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3828249 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.WriteReq_mshr_miss_latency::total 3828249 # number of WriteReq MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10979249 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.demand_mshr_miss_latency::total 10979249 # number of demand (read+write) MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10979249 # number of overall MSHR miss cycles
> system.cpu.dcache.overall_mshr_miss_latency::total 10979249 # number of overall MSHR miss cycles
872,879c910,917
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78684.065934 # average ReadReq mshr miss latency
< system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78684.065934 # average ReadReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75544.098039 # average WriteReq mshr miss latency
< system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75544.098039 # average WriteReq mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.demand_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77556.330986 # average overall mshr miss latency
< system.cpu.dcache.overall_avg_mshr_miss_latency::total 77556.330986 # average overall mshr miss latency
---
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78582.417582 # average ReadReq mshr miss latency
> system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78582.417582 # average ReadReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75063.705882 # average WriteReq mshr miss latency
> system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75063.705882 # average WriteReq mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.demand_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77318.654930 # average overall mshr miss latency
> system.cpu.dcache.overall_avg_mshr_miss_latency::total 77318.654930 # average overall mshr miss latency