1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 22451000 # Number of ticks simulated
5final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
| 1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 22451000 # Number of ticks simulated
5final_tick 22451000 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
|
7host_inst_rate 41665 # Simulator instruction rate (inst/s)
8host_op_rate 41658 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 187549895 # Simulator tick rate (ticks/s)
10host_mem_usage 287968 # Number of bytes of host memory used
11host_seconds 0.12 # Real time elapsed on the host
| 7host_inst_rate 76638 # Simulator instruction rate (inst/s)
8host_op_rate 76622 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 344943613 # Simulator tick rate (ticks/s)
10host_mem_usage 294148 # Number of bytes of host memory used
11host_seconds 0.07 # Real time elapsed on the host
|
12sim_insts 4986 # Number of instructions simulated
13sim_ops 4986 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
18system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 469 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 29 # Per bank write bursts
45system.physmem.perBankRdBursts::1 0 # Per bank write bursts
46system.physmem.perBankRdBursts::2 1 # Per bank write bursts
47system.physmem.perBankRdBursts::3 0 # Per bank write bursts
48system.physmem.perBankRdBursts::4 7 # Per bank write bursts
49system.physmem.perBankRdBursts::5 3 # Per bank write bursts
50system.physmem.perBankRdBursts::6 13 # Per bank write bursts
51system.physmem.perBankRdBursts::7 53 # Per bank write bursts
52system.physmem.perBankRdBursts::8 59 # Per bank write bursts
53system.physmem.perBankRdBursts::9 76 # Per bank write bursts
54system.physmem.perBankRdBursts::10 43 # Per bank write bursts
55system.physmem.perBankRdBursts::11 20 # Per bank write bursts
56system.physmem.perBankRdBursts::12 51 # Per bank write bursts
57system.physmem.perBankRdBursts::13 29 # Per bank write bursts
58system.physmem.perBankRdBursts::14 78 # Per bank write bursts
59system.physmem.perBankRdBursts::15 7 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 22364000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 469 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
203system.physmem.totQLat 4505500 # Total ticks spent queuing
204system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 10.44 # Data bus utilization in percentage
215system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 355 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 47684.43 # Average gap between requests
224system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ)
233system.physmem_0.averagePower 784.279760 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ)
247system.physmem_1.averagePower 934.618664 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 2031 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 605 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.dtb.read_hits 0 # DTB read hits
264system.cpu.dtb.read_misses 0 # DTB read misses
265system.cpu.dtb.read_accesses 0 # DTB read accesses
266system.cpu.dtb.write_hits 0 # DTB write hits
267system.cpu.dtb.write_misses 0 # DTB write misses
268system.cpu.dtb.write_accesses 0 # DTB write accesses
269system.cpu.dtb.hits 0 # DTB hits
270system.cpu.dtb.misses 0 # DTB misses
271system.cpu.dtb.accesses 0 # DTB accesses
272system.cpu.itb.read_hits 0 # DTB read hits
273system.cpu.itb.read_misses 0 # DTB read misses
274system.cpu.itb.read_accesses 0 # DTB read accesses
275system.cpu.itb.write_hits 0 # DTB write hits
276system.cpu.itb.write_misses 0 # DTB write misses
277system.cpu.itb.write_accesses 0 # DTB write accesses
278system.cpu.itb.hits 0 # DTB hits
279system.cpu.itb.misses 0 # DTB misses
280system.cpu.itb.accesses 0 # DTB accesses
281system.cpu.workload.num_syscalls 7 # Number of system calls
282system.cpu.numCycles 44903 # number of cpu cycles simulated
283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
285system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
286system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed
287system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered
288system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
289system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked
290system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing
291system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps
292system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
293system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed
294system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle
312system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle
313system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
314system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
315system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
316system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
317system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing
318system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
319system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction
320system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode
321system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
322system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing
323system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle
324system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking
325system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
326system.cpu.rename.RunCycles 2675 # Number of cycles rename is running
327system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
328system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename
329system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
330system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
331system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
332system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
333system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed
334system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
335system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups
336system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
337system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
338system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing
339system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
340system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
341system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
342system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit.
343system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
344system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
345system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
346system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec)
347system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
348system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued
349system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
350system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling
351system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph
352system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
353system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle
354system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle
355system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle
370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
371system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
372system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available
374system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available
375system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available
386system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available
387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available
388system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available
389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available
390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available
391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available
392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available
393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available
394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available
395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available
396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available
397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
400system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available
401system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available
402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
405system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued
406system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued
407system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
408system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued
409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
434system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued
435system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued
436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
438system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
439system.cpu.iq.rate 0.176759 # Inst issue rate
440system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
441system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
442system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
443system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes
444system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses
445system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
446system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
447system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
448system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses
449system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
450system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
452system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
453system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
454system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
455system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
458system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
459system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
461system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing
462system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking
463system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
464system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ
465system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
466system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions
467system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
468system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
469system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
470system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
471system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
472system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
473system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
474system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
475system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions
476system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed
477system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute
478system.cpu.iew.exec_swp 0 # number of swp insts executed
479system.cpu.iew.exec_nop 1483 # number of nop insts executed
480system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
481system.cpu.iew.exec_branches 1353 # Number of branches executed
482system.cpu.iew.exec_stores 1053 # Number of stores executed
483system.cpu.iew.exec_rate 0.170835 # Inst execution rate
484system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
485system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
486system.cpu.iew.wb_producers 2832 # num instructions producing a value
487system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
489system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle
490system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
492system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
493system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
494system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted
495system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle
496system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
499system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle
500system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle
501system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle
502system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle
503system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle
512system.cpu.commit.committedInsts 5623 # Number of instructions committed
513system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
515system.cpu.commit.refs 2033 # Number of memory references committed
516system.cpu.commit.loads 1132 # Number of loads committed
517system.cpu.commit.membars 0 # Number of memory barriers committed
518system.cpu.commit.branches 883 # Number of branches committed
519system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
520system.cpu.commit.int_insts 4942 # Number of committed integer instructions.
521system.cpu.commit.function_calls 85 # Number of function calls committed.
522system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction
523system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction
524system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction
525system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction
526system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction
527system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction
528system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction
529system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction
530system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
531system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
532system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
533system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
534system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
535system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
536system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
537system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
538system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
539system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
540system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
541system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
542system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
543system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
544system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
545system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
546system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
547system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
548system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction
553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction
554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
557system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached
558system.cpu.rob.rob_reads 23467 # The number of ROB reads
559system.cpu.rob.rob_writes 21056 # The number of ROB writes
560system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
561system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling
562system.cpu.committedInsts 4986 # Number of Instructions Simulated
563system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
564system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction
565system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads
566system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle
567system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads
568system.cpu.int_regfile_reads 10418 # number of integer regfile reads
569system.cpu.int_regfile_writes 5064 # number of integer regfile writes
570system.cpu.fp_regfile_reads 3 # number of floating regfile reads
571system.cpu.fp_regfile_writes 1 # number of floating regfile writes
572system.cpu.misc_regfile_reads 158 # number of misc regfile reads
573system.cpu.dcache.tags.replacements 0 # number of replacements
574system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use
575system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
576system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
577system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
579system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor
580system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy
581system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy
582system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
583system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
584system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
585system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
586system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses
587system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses
588system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits
589system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits
590system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
591system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
592system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits
593system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits
594system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits
595system.cpu.dcache.overall_hits::total 2302 # number of overall hits
596system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
597system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
598system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
599system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
600system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
601system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
602system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
603system.cpu.dcache.overall_misses::total 510 # number of overall misses
604system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles
605system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles
606system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
607system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
608system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles
609system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles
610system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles
611system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles
612system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses)
613system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses)
614system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
615system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
616system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses
617system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses
618system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses
619system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses
620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses
621system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses
622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
623system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
624system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses
625system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses
626system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses
627system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses
628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency
629system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency
630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
631system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
632system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
633system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency
634system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
635system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency
636system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
638system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
640system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked
641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
642system.cpu.dcache.fast_writes 0 # number of fast writes performed
643system.cpu.dcache.cache_copies 0 # number of cache copies performed
644system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
645system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
646system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
647system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
648system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
649system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
650system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
651system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
653system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
655system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
656system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
657system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
658system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
659system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles
661system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles
662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles
663system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles
664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles
665system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles
666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles
667system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles
668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses
669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses
670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses
673system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses
674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses
675system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses
676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency
677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency
678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency
679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency
680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
681system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
683system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
685system.cpu.icache.tags.replacements 17 # number of replacements
686system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use
687system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
688system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
689system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
691system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor
692system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy
693system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy
694system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
695system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
696system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
697system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
698system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses
699system.cpu.icache.tags.data_accesses 4289 # Number of data accesses
700system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits
701system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits
702system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits
703system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits
704system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits
705system.cpu.icache.overall_hits::total 1547 # number of overall hits
706system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
707system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
708system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
709system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
710system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
711system.cpu.icache.overall_misses::total 432 # number of overall misses
712system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles
713system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles
714system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles
715system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles
716system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles
717system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles
718system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
719system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
720system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
721system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses
722system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses
723system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
724system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses
725system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses
726system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses
727system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
728system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
729system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
730system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency
731system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency
732system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
733system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency
734system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
735system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency
736system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
737system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
738system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
739system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
740system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
741system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
742system.cpu.icache.fast_writes 0 # number of fast writes performed
743system.cpu.icache.cache_copies 0 # number of cache copies performed
744system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
745system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
746system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
747system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
748system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits
749system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits
750system.cpu.icache.ReadReq_mshr_misses::cpu.inst 331 # number of ReadReq MSHR misses
751system.cpu.icache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
752system.cpu.icache.demand_mshr_misses::cpu.inst 331 # number of demand (read+write) MSHR misses
753system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
754system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
755system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
756system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles
757system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles
758system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles
759system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles
760system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles
761system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles
762system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
763system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
764system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
765system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
766system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
767system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
768system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency
769system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency
770system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
771system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
772system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
773system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
774system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
775system.cpu.l2cache.tags.replacements 0 # number of replacements
776system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use
777system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
778system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
779system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
780system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
781system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor
782system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor
783system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
784system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
785system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
786system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
787system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
788system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
790system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
791system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
792system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
793system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
794system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
795system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
796system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
797system.cpu.l2cache.overall_hits::total 3 # number of overall hits
798system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
799system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
800system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses
801system.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses
802system.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses
803system.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses
804system.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses
805system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
806system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
807system.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses
808system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
809system.cpu.l2cache.overall_misses::total 469 # number of overall misses
810system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
811system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
812system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles
813system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles
814system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
815system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
816system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles
817system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
818system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles
819system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles
820system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
821system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles
822system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
823system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
824system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
825system.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses)
826system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses)
827system.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses)
828system.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses
829system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
830system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
831system.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses
832system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
833system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
834system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
835system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
836system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses
837system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990937 # miss rate for ReadCleanReq accesses
838system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
839system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
840system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses
841system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
842system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
843system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses
844system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
845system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
846system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
847system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
848system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency
849system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency
850system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
851system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
852system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
853system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
854system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency
855system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
856system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
857system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency
858system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
859system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
860system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
861system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
862system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
863system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
864system.cpu.l2cache.fast_writes 0 # number of fast writes performed
865system.cpu.l2cache.cache_copies 0 # number of cache copies performed
866system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
867system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
868system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses
869system.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses
870system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses
871system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses
872system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses
873system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
874system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
875system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses
876system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
877system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
878system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
879system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
880system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles
881system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles
882system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
883system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
884system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles
885system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
886system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles
887system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles
888system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
889system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles
890system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
891system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
892system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
893system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990937 # mshr miss rate for ReadCleanReq accesses
894system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
895system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
896system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses
897system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
898system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
899system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses
900system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
901system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
902system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
903system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
904system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency
905system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency
906system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
907system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
908system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
909system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
910system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
911system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
912system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
913system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
914system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
| 12sim_insts 4986 # Number of instructions simulated
13sim_ops 4986 # Number of ops (including micro ops) simulated
14system.voltage_domain.voltage 1 # Voltage in Volts
15system.clk_domain.clock 1000 # Clock period in ticks
16system.physmem.bytes_read::cpu.inst 20992 # Number of bytes read from this memory
17system.physmem.bytes_read::cpu.data 9024 # Number of bytes read from this memory
18system.physmem.bytes_read::total 30016 # Number of bytes read from this memory
19system.physmem.bytes_inst_read::cpu.inst 20992 # Number of instructions bytes read from this memory
20system.physmem.bytes_inst_read::total 20992 # Number of instructions bytes read from this memory
21system.physmem.num_reads::cpu.inst 328 # Number of read requests responded to by this memory
22system.physmem.num_reads::cpu.data 141 # Number of read requests responded to by this memory
23system.physmem.num_reads::total 469 # Number of read requests responded to by this memory
24system.physmem.bw_read::cpu.inst 935014031 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_read::cpu.data 401942007 # Total read bandwidth from this memory (bytes/s)
26system.physmem.bw_read::total 1336956038 # Total read bandwidth from this memory (bytes/s)
27system.physmem.bw_inst_read::cpu.inst 935014031 # Instruction read bandwidth from this memory (bytes/s)
28system.physmem.bw_inst_read::total 935014031 # Instruction read bandwidth from this memory (bytes/s)
29system.physmem.bw_total::cpu.inst 935014031 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.bw_total::cpu.data 401942007 # Total bandwidth to/from this memory (bytes/s)
31system.physmem.bw_total::total 1336956038 # Total bandwidth to/from this memory (bytes/s)
32system.physmem.readReqs 469 # Number of read requests accepted
33system.physmem.writeReqs 0 # Number of write requests accepted
34system.physmem.readBursts 469 # Number of DRAM read bursts, including those serviced by the write queue
35system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
36system.physmem.bytesReadDRAM 30016 # Total number of bytes read from DRAM
37system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
38system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
39system.physmem.bytesReadSys 30016 # Total read bytes from the system interface side
40system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
41system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
42system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
43system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
44system.physmem.perBankRdBursts::0 29 # Per bank write bursts
45system.physmem.perBankRdBursts::1 0 # Per bank write bursts
46system.physmem.perBankRdBursts::2 1 # Per bank write bursts
47system.physmem.perBankRdBursts::3 0 # Per bank write bursts
48system.physmem.perBankRdBursts::4 7 # Per bank write bursts
49system.physmem.perBankRdBursts::5 3 # Per bank write bursts
50system.physmem.perBankRdBursts::6 13 # Per bank write bursts
51system.physmem.perBankRdBursts::7 53 # Per bank write bursts
52system.physmem.perBankRdBursts::8 59 # Per bank write bursts
53system.physmem.perBankRdBursts::9 76 # Per bank write bursts
54system.physmem.perBankRdBursts::10 43 # Per bank write bursts
55system.physmem.perBankRdBursts::11 20 # Per bank write bursts
56system.physmem.perBankRdBursts::12 51 # Per bank write bursts
57system.physmem.perBankRdBursts::13 29 # Per bank write bursts
58system.physmem.perBankRdBursts::14 78 # Per bank write bursts
59system.physmem.perBankRdBursts::15 7 # Per bank write bursts
60system.physmem.perBankWrBursts::0 0 # Per bank write bursts
61system.physmem.perBankWrBursts::1 0 # Per bank write bursts
62system.physmem.perBankWrBursts::2 0 # Per bank write bursts
63system.physmem.perBankWrBursts::3 0 # Per bank write bursts
64system.physmem.perBankWrBursts::4 0 # Per bank write bursts
65system.physmem.perBankWrBursts::5 0 # Per bank write bursts
66system.physmem.perBankWrBursts::6 0 # Per bank write bursts
67system.physmem.perBankWrBursts::7 0 # Per bank write bursts
68system.physmem.perBankWrBursts::8 0 # Per bank write bursts
69system.physmem.perBankWrBursts::9 0 # Per bank write bursts
70system.physmem.perBankWrBursts::10 0 # Per bank write bursts
71system.physmem.perBankWrBursts::11 0 # Per bank write bursts
72system.physmem.perBankWrBursts::12 0 # Per bank write bursts
73system.physmem.perBankWrBursts::13 0 # Per bank write bursts
74system.physmem.perBankWrBursts::14 0 # Per bank write bursts
75system.physmem.perBankWrBursts::15 0 # Per bank write bursts
76system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
77system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
78system.physmem.totGap 22364000 # Total gap between requests
79system.physmem.readPktSize::0 0 # Read request sizes (log2)
80system.physmem.readPktSize::1 0 # Read request sizes (log2)
81system.physmem.readPktSize::2 0 # Read request sizes (log2)
82system.physmem.readPktSize::3 0 # Read request sizes (log2)
83system.physmem.readPktSize::4 0 # Read request sizes (log2)
84system.physmem.readPktSize::5 0 # Read request sizes (log2)
85system.physmem.readPktSize::6 469 # Read request sizes (log2)
86system.physmem.writePktSize::0 0 # Write request sizes (log2)
87system.physmem.writePktSize::1 0 # Write request sizes (log2)
88system.physmem.writePktSize::2 0 # Write request sizes (log2)
89system.physmem.writePktSize::3 0 # Write request sizes (log2)
90system.physmem.writePktSize::4 0 # Write request sizes (log2)
91system.physmem.writePktSize::5 0 # Write request sizes (log2)
92system.physmem.writePktSize::6 0 # Write request sizes (log2)
93system.physmem.rdQLenPdf::0 273 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::1 135 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::3 16 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
104system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
105system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see
106system.physmem.rdQLenPdf::13 0 # What read queue length does an incoming req see
107system.physmem.rdQLenPdf::14 0 # What read queue length does an incoming req see
108system.physmem.rdQLenPdf::15 0 # What read queue length does an incoming req see
109system.physmem.rdQLenPdf::16 0 # What read queue length does an incoming req see
110system.physmem.rdQLenPdf::17 0 # What read queue length does an incoming req see
111system.physmem.rdQLenPdf::18 0 # What read queue length does an incoming req see
112system.physmem.rdQLenPdf::19 0 # What read queue length does an incoming req see
113system.physmem.rdQLenPdf::20 0 # What read queue length does an incoming req see
114system.physmem.rdQLenPdf::21 0 # What read queue length does an incoming req see
115system.physmem.rdQLenPdf::22 0 # What read queue length does an incoming req see
116system.physmem.rdQLenPdf::23 0 # What read queue length does an incoming req see
117system.physmem.rdQLenPdf::24 0 # What read queue length does an incoming req see
118system.physmem.rdQLenPdf::25 0 # What read queue length does an incoming req see
119system.physmem.rdQLenPdf::26 0 # What read queue length does an incoming req see
120system.physmem.rdQLenPdf::27 0 # What read queue length does an incoming req see
121system.physmem.rdQLenPdf::28 0 # What read queue length does an incoming req see
122system.physmem.rdQLenPdf::29 0 # What read queue length does an incoming req see
123system.physmem.rdQLenPdf::30 0 # What read queue length does an incoming req see
124system.physmem.rdQLenPdf::31 0 # What read queue length does an incoming req see
125system.physmem.wrQLenPdf::0 0 # What write queue length does an incoming req see
126system.physmem.wrQLenPdf::1 0 # What write queue length does an incoming req see
127system.physmem.wrQLenPdf::2 0 # What write queue length does an incoming req see
128system.physmem.wrQLenPdf::3 0 # What write queue length does an incoming req see
129system.physmem.wrQLenPdf::4 0 # What write queue length does an incoming req see
130system.physmem.wrQLenPdf::5 0 # What write queue length does an incoming req see
131system.physmem.wrQLenPdf::6 0 # What write queue length does an incoming req see
132system.physmem.wrQLenPdf::7 0 # What write queue length does an incoming req see
133system.physmem.wrQLenPdf::8 0 # What write queue length does an incoming req see
134system.physmem.wrQLenPdf::9 0 # What write queue length does an incoming req see
135system.physmem.wrQLenPdf::10 0 # What write queue length does an incoming req see
136system.physmem.wrQLenPdf::11 0 # What write queue length does an incoming req see
137system.physmem.wrQLenPdf::12 0 # What write queue length does an incoming req see
138system.physmem.wrQLenPdf::13 0 # What write queue length does an incoming req see
139system.physmem.wrQLenPdf::14 0 # What write queue length does an incoming req see
140system.physmem.wrQLenPdf::15 0 # What write queue length does an incoming req see
141system.physmem.wrQLenPdf::16 0 # What write queue length does an incoming req see
142system.physmem.wrQLenPdf::17 0 # What write queue length does an incoming req see
143system.physmem.wrQLenPdf::18 0 # What write queue length does an incoming req see
144system.physmem.wrQLenPdf::19 0 # What write queue length does an incoming req see
145system.physmem.wrQLenPdf::20 0 # What write queue length does an incoming req see
146system.physmem.wrQLenPdf::21 0 # What write queue length does an incoming req see
147system.physmem.wrQLenPdf::22 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::23 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
155system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
156system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
157system.physmem.wrQLenPdf::32 0 # What write queue length does an incoming req see
158system.physmem.wrQLenPdf::33 0 # What write queue length does an incoming req see
159system.physmem.wrQLenPdf::34 0 # What write queue length does an incoming req see
160system.physmem.wrQLenPdf::35 0 # What write queue length does an incoming req see
161system.physmem.wrQLenPdf::36 0 # What write queue length does an incoming req see
162system.physmem.wrQLenPdf::37 0 # What write queue length does an incoming req see
163system.physmem.wrQLenPdf::38 0 # What write queue length does an incoming req see
164system.physmem.wrQLenPdf::39 0 # What write queue length does an incoming req see
165system.physmem.wrQLenPdf::40 0 # What write queue length does an incoming req see
166system.physmem.wrQLenPdf::41 0 # What write queue length does an incoming req see
167system.physmem.wrQLenPdf::42 0 # What write queue length does an incoming req see
168system.physmem.wrQLenPdf::43 0 # What write queue length does an incoming req see
169system.physmem.wrQLenPdf::44 0 # What write queue length does an incoming req see
170system.physmem.wrQLenPdf::45 0 # What write queue length does an incoming req see
171system.physmem.wrQLenPdf::46 0 # What write queue length does an incoming req see
172system.physmem.wrQLenPdf::47 0 # What write queue length does an incoming req see
173system.physmem.wrQLenPdf::48 0 # What write queue length does an incoming req see
174system.physmem.wrQLenPdf::49 0 # What write queue length does an incoming req see
175system.physmem.wrQLenPdf::50 0 # What write queue length does an incoming req see
176system.physmem.wrQLenPdf::51 0 # What write queue length does an incoming req see
177system.physmem.wrQLenPdf::52 0 # What write queue length does an incoming req see
178system.physmem.wrQLenPdf::53 0 # What write queue length does an incoming req see
179system.physmem.wrQLenPdf::54 0 # What write queue length does an incoming req see
180system.physmem.wrQLenPdf::55 0 # What write queue length does an incoming req see
181system.physmem.wrQLenPdf::56 0 # What write queue length does an incoming req see
182system.physmem.wrQLenPdf::57 0 # What write queue length does an incoming req see
183system.physmem.wrQLenPdf::58 0 # What write queue length does an incoming req see
184system.physmem.wrQLenPdf::59 0 # What write queue length does an incoming req see
185system.physmem.wrQLenPdf::60 0 # What write queue length does an incoming req see
186system.physmem.wrQLenPdf::61 0 # What write queue length does an incoming req see
187system.physmem.wrQLenPdf::62 0 # What write queue length does an incoming req see
188system.physmem.wrQLenPdf::63 0 # What write queue length does an incoming req see
189system.physmem.bytesPerActivate::samples 104 # Bytes accessed per row activation
190system.physmem.bytesPerActivate::mean 262.153846 # Bytes accessed per row activation
191system.physmem.bytesPerActivate::gmean 180.926322 # Bytes accessed per row activation
192system.physmem.bytesPerActivate::stdev 251.694944 # Bytes accessed per row activation
193system.physmem.bytesPerActivate::0-127 29 27.88% 27.88% # Bytes accessed per row activation
194system.physmem.bytesPerActivate::128-255 32 30.77% 58.65% # Bytes accessed per row activation
195system.physmem.bytesPerActivate::256-383 20 19.23% 77.88% # Bytes accessed per row activation
196system.physmem.bytesPerActivate::384-511 9 8.65% 86.54% # Bytes accessed per row activation
197system.physmem.bytesPerActivate::512-639 4 3.85% 90.38% # Bytes accessed per row activation
198system.physmem.bytesPerActivate::640-767 2 1.92% 92.31% # Bytes accessed per row activation
199system.physmem.bytesPerActivate::768-895 1 0.96% 93.27% # Bytes accessed per row activation
200system.physmem.bytesPerActivate::896-1023 1 0.96% 94.23% # Bytes accessed per row activation
201system.physmem.bytesPerActivate::1024-1151 6 5.77% 100.00% # Bytes accessed per row activation
202system.physmem.bytesPerActivate::total 104 # Bytes accessed per row activation
203system.physmem.totQLat 4505500 # Total ticks spent queuing
204system.physmem.totMemAccLat 13299250 # Total ticks spent from burst creation until serviced by the DRAM
205system.physmem.totBusLat 2345000 # Total ticks spent in databus transfers
206system.physmem.avgQLat 9606.61 # Average queueing delay per DRAM burst
207system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
208system.physmem.avgMemAccLat 28356.61 # Average memory access latency per DRAM burst
209system.physmem.avgRdBW 1336.96 # Average DRAM read bandwidth in MiByte/s
210system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
211system.physmem.avgRdBWSys 1336.96 # Average system read bandwidth in MiByte/s
212system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
213system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
214system.physmem.busUtil 10.44 # Data bus utilization in percentage
215system.physmem.busUtilRead 10.44 # Data bus utilization in percentage for reads
216system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
217system.physmem.avgRdQLen 1.73 # Average read queue length when enqueuing
218system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
219system.physmem.readRowHits 355 # Number of row buffer hits during reads
220system.physmem.writeRowHits 0 # Number of row buffer hits during writes
221system.physmem.readRowHitRate 75.69 # Row buffer hit rate for reads
222system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
223system.physmem.avgGap 47684.43 # Average gap between requests
224system.physmem.pageHitRate 75.69 # Row buffer hit rate, read and write combined
225system.physmem_0.actEnergy 128520 # Energy for activate commands per rank (pJ)
226system.physmem_0.preEnergy 70125 # Energy for precharge commands per rank (pJ)
227system.physmem_0.readEnergy 530400 # Energy for read commands per rank (pJ)
228system.physmem_0.writeEnergy 0 # Energy for write commands per rank (pJ)
229system.physmem_0.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
230system.physmem_0.actBackEnergy 9542655 # Energy for active background per rank (pJ)
231system.physmem_0.preBackEnergy 1130250 # Energy for precharge background per rank (pJ)
232system.physmem_0.totalEnergy 12419070 # Total energy per rank (pJ)
233system.physmem_0.averagePower 784.279760 # Core power per rank (mW)
234system.physmem_0.memoryStateTime::IDLE 1840500 # Time in different power states
235system.physmem_0.memoryStateTime::REF 520000 # Time in different power states
236system.physmem_0.memoryStateTime::PRE_PDN 0 # Time in different power states
237system.physmem_0.memoryStateTime::ACT 13487750 # Time in different power states
238system.physmem_0.memoryStateTime::ACT_PDN 0 # Time in different power states
239system.physmem_1.actEnergy 514080 # Energy for activate commands per rank (pJ)
240system.physmem_1.preEnergy 280500 # Energy for precharge commands per rank (pJ)
241system.physmem_1.readEnergy 2168400 # Energy for read commands per rank (pJ)
242system.physmem_1.writeEnergy 0 # Energy for write commands per rank (pJ)
243system.physmem_1.refreshEnergy 1017120 # Energy for refresh commands per rank (pJ)
244system.physmem_1.actBackEnergy 10730250 # Energy for active background per rank (pJ)
245system.physmem_1.preBackEnergy 87000 # Energy for precharge background per rank (pJ)
246system.physmem_1.totalEnergy 14797350 # Total energy per rank (pJ)
247system.physmem_1.averagePower 934.618664 # Core power per rank (mW)
248system.physmem_1.memoryStateTime::IDLE 103500 # Time in different power states
249system.physmem_1.memoryStateTime::REF 520000 # Time in different power states
250system.physmem_1.memoryStateTime::PRE_PDN 0 # Time in different power states
251system.physmem_1.memoryStateTime::ACT 15222750 # Time in different power states
252system.physmem_1.memoryStateTime::ACT_PDN 0 # Time in different power states
253system.cpu.branchPred.lookups 2031 # Number of BP lookups
254system.cpu.branchPred.condPredicted 1362 # Number of conditional branches predicted
255system.cpu.branchPred.condIncorrect 402 # Number of conditional branches incorrect
256system.cpu.branchPred.BTBLookups 1641 # Number of BTB lookups
257system.cpu.branchPred.BTBHits 605 # Number of BTB hits
258system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
259system.cpu.branchPred.BTBHitPct 36.867764 # BTB Hit Percentage
260system.cpu.branchPred.usedRAS 242 # Number of times the RAS was used to get a target.
261system.cpu.branchPred.RASInCorrect 66 # Number of incorrect RAS predictions.
262system.cpu_clk_domain.clock 500 # Clock period in ticks
263system.cpu.dtb.read_hits 0 # DTB read hits
264system.cpu.dtb.read_misses 0 # DTB read misses
265system.cpu.dtb.read_accesses 0 # DTB read accesses
266system.cpu.dtb.write_hits 0 # DTB write hits
267system.cpu.dtb.write_misses 0 # DTB write misses
268system.cpu.dtb.write_accesses 0 # DTB write accesses
269system.cpu.dtb.hits 0 # DTB hits
270system.cpu.dtb.misses 0 # DTB misses
271system.cpu.dtb.accesses 0 # DTB accesses
272system.cpu.itb.read_hits 0 # DTB read hits
273system.cpu.itb.read_misses 0 # DTB read misses
274system.cpu.itb.read_accesses 0 # DTB read accesses
275system.cpu.itb.write_hits 0 # DTB write hits
276system.cpu.itb.write_misses 0 # DTB write misses
277system.cpu.itb.write_accesses 0 # DTB write accesses
278system.cpu.itb.hits 0 # DTB hits
279system.cpu.itb.misses 0 # DTB misses
280system.cpu.itb.accesses 0 # DTB accesses
281system.cpu.workload.num_syscalls 7 # Number of system calls
282system.cpu.numCycles 44903 # number of cpu cycles simulated
283system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
284system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
285system.cpu.fetch.icacheStallCycles 8843 # Number of cycles fetch is stalled on an Icache miss
286system.cpu.fetch.Insts 12328 # Number of instructions fetch has processed
287system.cpu.fetch.Branches 2031 # Number of branches that fetch encountered
288system.cpu.fetch.predictedBranches 847 # Number of branches that fetch has predicted taken
289system.cpu.fetch.Cycles 4817 # Number of cycles fetch has run and was not squashing or blocked
290system.cpu.fetch.SquashCycles 822 # Number of cycles fetch has spent squashing
291system.cpu.fetch.PendingTrapStallCycles 190 # Number of stall cycles due to pending traps
292system.cpu.fetch.CacheLines 1979 # Number of cache lines fetched
293system.cpu.fetch.IcacheSquashes 255 # Number of outstanding Icache misses that were squashed
294system.cpu.fetch.rateDist::samples 14261 # Number of instructions fetched each cycle (Total)
295system.cpu.fetch.rateDist::mean 0.864456 # Number of instructions fetched each cycle (Total)
296system.cpu.fetch.rateDist::stdev 2.133927 # Number of instructions fetched each cycle (Total)
297system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
298system.cpu.fetch.rateDist::0 10999 77.13% 77.13% # Number of instructions fetched each cycle (Total)
299system.cpu.fetch.rateDist::1 1480 10.38% 87.50% # Number of instructions fetched each cycle (Total)
300system.cpu.fetch.rateDist::2 118 0.83% 88.33% # Number of instructions fetched each cycle (Total)
301system.cpu.fetch.rateDist::3 169 1.19% 89.52% # Number of instructions fetched each cycle (Total)
302system.cpu.fetch.rateDist::4 282 1.98% 91.49% # Number of instructions fetched each cycle (Total)
303system.cpu.fetch.rateDist::5 102 0.72% 92.21% # Number of instructions fetched each cycle (Total)
304system.cpu.fetch.rateDist::6 134 0.94% 93.15% # Number of instructions fetched each cycle (Total)
305system.cpu.fetch.rateDist::7 153 1.07% 94.22% # Number of instructions fetched each cycle (Total)
306system.cpu.fetch.rateDist::8 824 5.78% 100.00% # Number of instructions fetched each cycle (Total)
307system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
308system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
309system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
310system.cpu.fetch.rateDist::total 14261 # Number of instructions fetched each cycle (Total)
311system.cpu.fetch.branchRate 0.045231 # Number of branch fetches per cycle
312system.cpu.fetch.rate 0.274547 # Number of inst fetches per cycle
313system.cpu.decode.IdleCycles 8380 # Number of cycles decode is idle
314system.cpu.decode.BlockedCycles 2677 # Number of cycles decode is blocked
315system.cpu.decode.RunCycles 2707 # Number of cycles decode is running
316system.cpu.decode.UnblockCycles 126 # Number of cycles decode is unblocking
317system.cpu.decode.SquashCycles 371 # Number of cycles decode is squashing
318system.cpu.decode.BranchResolved 167 # Number of times decode resolved a branch
319system.cpu.decode.BranchMispred 41 # Number of times decode detected a branch misprediction
320system.cpu.decode.DecodedInsts 11351 # Number of instructions handled by decode
321system.cpu.decode.SquashedInsts 162 # Number of squashed instructions handled by decode
322system.cpu.rename.SquashCycles 371 # Number of cycles rename is squashing
323system.cpu.rename.IdleCycles 8518 # Number of cycles rename is idle
324system.cpu.rename.BlockCycles 542 # Number of cycles rename is blocking
325system.cpu.rename.serializeStallCycles 996 # count of cycles rename stalled for serializing inst
326system.cpu.rename.RunCycles 2675 # Number of cycles rename is running
327system.cpu.rename.UnblockCycles 1159 # Number of cycles rename is unblocking
328system.cpu.rename.RenamedInsts 10918 # Number of instructions processed by rename
329system.cpu.rename.ROBFullEvents 4 # Number of times rename has blocked due to ROB full
330system.cpu.rename.IQFullEvents 4 # Number of times rename has blocked due to IQ full
331system.cpu.rename.LQFullEvents 179 # Number of times rename has blocked due to LQ full
332system.cpu.rename.SQFullEvents 954 # Number of times rename has blocked due to SQ full
333system.cpu.rename.RenamedOperands 6512 # Number of destination operands rename has renamed
334system.cpu.rename.RenameLookups 12905 # Number of register rename lookups that rename has made
335system.cpu.rename.int_rename_lookups 12683 # Number of integer rename lookups
336system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
337system.cpu.rename.CommittedMaps 3282 # Number of HB maps that are committed
338system.cpu.rename.UndoneMaps 3230 # Number of HB maps that are undone due to squashing
339system.cpu.rename.serializingInsts 14 # count of serializing insts renamed
340system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
341system.cpu.rename.skidInsts 314 # count of insts added to the skid buffer
342system.cpu.memDep0.insertedLoads 2295 # Number of loads inserted to the mem dependence unit.
343system.cpu.memDep0.insertedStores 1159 # Number of stores inserted to the mem dependence unit.
344system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
345system.cpu.memDep0.conflictingStores 2 # Number of conflicting stores.
346system.cpu.iq.iqInstsAdded 8632 # Number of instructions added to the IQ (excludes non-spec)
347system.cpu.iq.iqNonSpecInstsAdded 11 # Number of non-speculative instructions added to the IQ
348system.cpu.iq.iqInstsIssued 7937 # Number of instructions issued
349system.cpu.iq.iqSquashedInstsIssued 20 # Number of squashed instructions issued
350system.cpu.iq.iqSquashedInstsExamined 3656 # Number of squashed instructions iterated over during squash; mainly for profiling
351system.cpu.iq.iqSquashedOperandsExamined 1608 # Number of squashed operands that are examined and possibly removed from graph
352system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
353system.cpu.iq.issued_per_cycle::samples 14261 # Number of insts issued each cycle
354system.cpu.iq.issued_per_cycle::mean 0.556553 # Number of insts issued each cycle
355system.cpu.iq.issued_per_cycle::stdev 1.276985 # Number of insts issued each cycle
356system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
357system.cpu.iq.issued_per_cycle::0 10981 77.00% 77.00% # Number of insts issued each cycle
358system.cpu.iq.issued_per_cycle::1 1321 9.26% 86.26% # Number of insts issued each cycle
359system.cpu.iq.issued_per_cycle::2 733 5.14% 91.40% # Number of insts issued each cycle
360system.cpu.iq.issued_per_cycle::3 439 3.08% 94.48% # Number of insts issued each cycle
361system.cpu.iq.issued_per_cycle::4 350 2.45% 96.94% # Number of insts issued each cycle
362system.cpu.iq.issued_per_cycle::5 277 1.94% 98.88% # Number of insts issued each cycle
363system.cpu.iq.issued_per_cycle::6 91 0.64% 99.52% # Number of insts issued each cycle
364system.cpu.iq.issued_per_cycle::7 50 0.35% 99.87% # Number of insts issued each cycle
365system.cpu.iq.issued_per_cycle::8 19 0.13% 100.00% # Number of insts issued each cycle
366system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
367system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
368system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
369system.cpu.iq.issued_per_cycle::total 14261 # Number of insts issued each cycle
370system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
371system.cpu.iq.fu_full::IntAlu 6 3.41% 3.41% # attempts to use FU when none available
372system.cpu.iq.fu_full::IntMult 0 0.00% 3.41% # attempts to use FU when none available
373system.cpu.iq.fu_full::IntDiv 0 0.00% 3.41% # attempts to use FU when none available
374system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.41% # attempts to use FU when none available
375system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.41% # attempts to use FU when none available
376system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.41% # attempts to use FU when none available
377system.cpu.iq.fu_full::FloatMult 0 0.00% 3.41% # attempts to use FU when none available
378system.cpu.iq.fu_full::FloatDiv 0 0.00% 3.41% # attempts to use FU when none available
379system.cpu.iq.fu_full::FloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
380system.cpu.iq.fu_full::SimdAdd 0 0.00% 3.41% # attempts to use FU when none available
381system.cpu.iq.fu_full::SimdAddAcc 0 0.00% 3.41% # attempts to use FU when none available
382system.cpu.iq.fu_full::SimdAlu 0 0.00% 3.41% # attempts to use FU when none available
383system.cpu.iq.fu_full::SimdCmp 0 0.00% 3.41% # attempts to use FU when none available
384system.cpu.iq.fu_full::SimdCvt 0 0.00% 3.41% # attempts to use FU when none available
385system.cpu.iq.fu_full::SimdMisc 0 0.00% 3.41% # attempts to use FU when none available
386system.cpu.iq.fu_full::SimdMult 0 0.00% 3.41% # attempts to use FU when none available
387system.cpu.iq.fu_full::SimdMultAcc 0 0.00% 3.41% # attempts to use FU when none available
388system.cpu.iq.fu_full::SimdShift 0 0.00% 3.41% # attempts to use FU when none available
389system.cpu.iq.fu_full::SimdShiftAcc 0 0.00% 3.41% # attempts to use FU when none available
390system.cpu.iq.fu_full::SimdSqrt 0 0.00% 3.41% # attempts to use FU when none available
391system.cpu.iq.fu_full::SimdFloatAdd 0 0.00% 3.41% # attempts to use FU when none available
392system.cpu.iq.fu_full::SimdFloatAlu 0 0.00% 3.41% # attempts to use FU when none available
393system.cpu.iq.fu_full::SimdFloatCmp 0 0.00% 3.41% # attempts to use FU when none available
394system.cpu.iq.fu_full::SimdFloatCvt 0 0.00% 3.41% # attempts to use FU when none available
395system.cpu.iq.fu_full::SimdFloatDiv 0 0.00% 3.41% # attempts to use FU when none available
396system.cpu.iq.fu_full::SimdFloatMisc 0 0.00% 3.41% # attempts to use FU when none available
397system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.41% # attempts to use FU when none available
398system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.41% # attempts to use FU when none available
399system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.41% # attempts to use FU when none available
400system.cpu.iq.fu_full::MemRead 112 63.64% 67.05% # attempts to use FU when none available
401system.cpu.iq.fu_full::MemWrite 58 32.95% 100.00% # attempts to use FU when none available
402system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
403system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
404system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
405system.cpu.iq.FU_type_0::IntAlu 4719 59.46% 59.46% # Type of FU issued
406system.cpu.iq.FU_type_0::IntMult 4 0.05% 59.51% # Type of FU issued
407system.cpu.iq.FU_type_0::IntDiv 1 0.01% 59.52% # Type of FU issued
408system.cpu.iq.FU_type_0::FloatAdd 2 0.03% 59.54% # Type of FU issued
409system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.54% # Type of FU issued
410system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.54% # Type of FU issued
411system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.54% # Type of FU issued
412system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.54% # Type of FU issued
413system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.54% # Type of FU issued
414system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.54% # Type of FU issued
415system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.54% # Type of FU issued
416system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.54% # Type of FU issued
417system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.54% # Type of FU issued
418system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.54% # Type of FU issued
419system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.54% # Type of FU issued
420system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.54% # Type of FU issued
421system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.54% # Type of FU issued
422system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.54% # Type of FU issued
423system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.54% # Type of FU issued
424system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.54% # Type of FU issued
425system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.54% # Type of FU issued
426system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.54% # Type of FU issued
427system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.54% # Type of FU issued
428system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.54% # Type of FU issued
429system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.54% # Type of FU issued
430system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.54% # Type of FU issued
431system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.54% # Type of FU issued
432system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.54% # Type of FU issued
433system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.54% # Type of FU issued
434system.cpu.iq.FU_type_0::MemRead 2143 27.00% 86.54% # Type of FU issued
435system.cpu.iq.FU_type_0::MemWrite 1068 13.46% 100.00% # Type of FU issued
436system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
437system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
438system.cpu.iq.FU_type_0::total 7937 # Type of FU issued
439system.cpu.iq.rate 0.176759 # Inst issue rate
440system.cpu.iq.fu_busy_cnt 176 # FU busy when requested
441system.cpu.iq.fu_busy_rate 0.022175 # FU busy rate (busy events/executed inst)
442system.cpu.iq.int_inst_queue_reads 30327 # Number of integer instruction queue reads
443system.cpu.iq.int_inst_queue_writes 12306 # Number of integer instruction queue writes
444system.cpu.iq.int_inst_queue_wakeup_accesses 7277 # Number of integer instruction queue wakeup accesses
445system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
446system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
447system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
448system.cpu.iq.int_alu_accesses 8111 # Number of integer alu accesses
449system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
450system.cpu.iew.lsq.thread0.forwLoads 89 # Number of loads that had data forwarded from stores
451system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
452system.cpu.iew.lsq.thread0.squashedLoads 1163 # Number of loads squashed
453system.cpu.iew.lsq.thread0.ignoredResponses 8 # Number of memory responses ignored because the instruction is squashed
454system.cpu.iew.lsq.thread0.memOrderViolation 10 # Number of memory ordering violations
455system.cpu.iew.lsq.thread0.squashedStores 258 # Number of stores squashed
456system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
457system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
458system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
459system.cpu.iew.lsq.thread0.cacheBlocked 22 # Number of times an access to memory failed due to the cache being blocked
460system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
461system.cpu.iew.iewSquashCycles 371 # Number of cycles IEW is squashing
462system.cpu.iew.iewBlockCycles 425 # Number of cycles IEW is blocking
463system.cpu.iew.iewUnblockCycles 88 # Number of cycles IEW is unblocking
464system.cpu.iew.iewDispatchedInsts 10126 # Number of instructions dispatched to IQ
465system.cpu.iew.iewDispSquashedInsts 130 # Number of squashed instructions skipped by dispatch
466system.cpu.iew.iewDispLoadInsts 2295 # Number of dispatched load instructions
467system.cpu.iew.iewDispStoreInsts 1159 # Number of dispatched store instructions
468system.cpu.iew.iewDispNonSpecInsts 11 # Number of dispatched non-speculative instructions
469system.cpu.iew.iewIQFullEvents 0 # Number of times the IQ has become full, causing a stall
470system.cpu.iew.iewLSQFullEvents 89 # Number of times the LSQ has become full, causing a stall
471system.cpu.iew.memOrderViolationEvents 10 # Number of memory order violations
472system.cpu.iew.predictedTakenIncorrect 98 # Number of branches that were predicted taken incorrectly
473system.cpu.iew.predictedNotTakenIncorrect 321 # Number of branches that were predicted not taken incorrectly
474system.cpu.iew.branchMispredicts 419 # Number of branch mispredicts detected at execute
475system.cpu.iew.iewExecutedInsts 7671 # Number of executed instructions
476system.cpu.iew.iewExecLoadInsts 2045 # Number of load instructions executed
477system.cpu.iew.iewExecSquashedInsts 266 # Number of squashed instructions skipped in execute
478system.cpu.iew.exec_swp 0 # number of swp insts executed
479system.cpu.iew.exec_nop 1483 # number of nop insts executed
480system.cpu.iew.exec_refs 3098 # number of memory reference insts executed
481system.cpu.iew.exec_branches 1353 # Number of branches executed
482system.cpu.iew.exec_stores 1053 # Number of stores executed
483system.cpu.iew.exec_rate 0.170835 # Inst execution rate
484system.cpu.iew.wb_sent 7354 # cumulative count of insts sent to commit
485system.cpu.iew.wb_count 7279 # cumulative count of insts written-back
486system.cpu.iew.wb_producers 2832 # num instructions producing a value
487system.cpu.iew.wb_consumers 4198 # num instructions consuming a value
488system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
489system.cpu.iew.wb_rate 0.162105 # insts written-back per cycle
490system.cpu.iew.wb_fanout 0.674607 # average fanout of values written-back
491system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
492system.cpu.commit.commitSquashedInsts 4505 # The number of squashed insts skipped by commit
493system.cpu.commit.commitNonSpecStalls 9 # The number of times commit has been forced to stall to communicate backwards
494system.cpu.commit.branchMispredicts 362 # The number of times a branch was mispredicted
495system.cpu.commit.committed_per_cycle::samples 13468 # Number of insts commited each cycle
496system.cpu.commit.committed_per_cycle::mean 0.417508 # Number of insts commited each cycle
497system.cpu.commit.committed_per_cycle::stdev 1.246465 # Number of insts commited each cycle
498system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
499system.cpu.commit.committed_per_cycle::0 11324 84.08% 84.08% # Number of insts commited each cycle
500system.cpu.commit.committed_per_cycle::1 857 6.36% 90.44% # Number of insts commited each cycle
501system.cpu.commit.committed_per_cycle::2 503 3.73% 94.18% # Number of insts commited each cycle
502system.cpu.commit.committed_per_cycle::3 247 1.83% 96.01% # Number of insts commited each cycle
503system.cpu.commit.committed_per_cycle::4 153 1.14% 97.15% # Number of insts commited each cycle
504system.cpu.commit.committed_per_cycle::5 168 1.25% 98.40% # Number of insts commited each cycle
505system.cpu.commit.committed_per_cycle::6 61 0.45% 98.85% # Number of insts commited each cycle
506system.cpu.commit.committed_per_cycle::7 39 0.29% 99.14% # Number of insts commited each cycle
507system.cpu.commit.committed_per_cycle::8 116 0.86% 100.00% # Number of insts commited each cycle
508system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
509system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
510system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
511system.cpu.commit.committed_per_cycle::total 13468 # Number of insts commited each cycle
512system.cpu.commit.committedInsts 5623 # Number of instructions committed
513system.cpu.commit.committedOps 5623 # Number of ops (including micro ops) committed
514system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
515system.cpu.commit.refs 2033 # Number of memory references committed
516system.cpu.commit.loads 1132 # Number of loads committed
517system.cpu.commit.membars 0 # Number of memory barriers committed
518system.cpu.commit.branches 883 # Number of branches committed
519system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
520system.cpu.commit.int_insts 4942 # Number of committed integer instructions.
521system.cpu.commit.function_calls 85 # Number of function calls committed.
522system.cpu.commit.op_class_0::No_OpClass 637 11.33% 11.33% # Class of committed instruction
523system.cpu.commit.op_class_0::IntAlu 2949 52.45% 63.77% # Class of committed instruction
524system.cpu.commit.op_class_0::IntMult 2 0.04% 63.81% # Class of committed instruction
525system.cpu.commit.op_class_0::IntDiv 0 0.00% 63.81% # Class of committed instruction
526system.cpu.commit.op_class_0::FloatAdd 2 0.04% 63.84% # Class of committed instruction
527system.cpu.commit.op_class_0::FloatCmp 0 0.00% 63.84% # Class of committed instruction
528system.cpu.commit.op_class_0::FloatCvt 0 0.00% 63.84% # Class of committed instruction
529system.cpu.commit.op_class_0::FloatMult 0 0.00% 63.84% # Class of committed instruction
530system.cpu.commit.op_class_0::FloatDiv 0 0.00% 63.84% # Class of committed instruction
531system.cpu.commit.op_class_0::FloatSqrt 0 0.00% 63.84% # Class of committed instruction
532system.cpu.commit.op_class_0::SimdAdd 0 0.00% 63.84% # Class of committed instruction
533system.cpu.commit.op_class_0::SimdAddAcc 0 0.00% 63.84% # Class of committed instruction
534system.cpu.commit.op_class_0::SimdAlu 0 0.00% 63.84% # Class of committed instruction
535system.cpu.commit.op_class_0::SimdCmp 0 0.00% 63.84% # Class of committed instruction
536system.cpu.commit.op_class_0::SimdCvt 0 0.00% 63.84% # Class of committed instruction
537system.cpu.commit.op_class_0::SimdMisc 0 0.00% 63.84% # Class of committed instruction
538system.cpu.commit.op_class_0::SimdMult 0 0.00% 63.84% # Class of committed instruction
539system.cpu.commit.op_class_0::SimdMultAcc 0 0.00% 63.84% # Class of committed instruction
540system.cpu.commit.op_class_0::SimdShift 0 0.00% 63.84% # Class of committed instruction
541system.cpu.commit.op_class_0::SimdShiftAcc 0 0.00% 63.84% # Class of committed instruction
542system.cpu.commit.op_class_0::SimdSqrt 0 0.00% 63.84% # Class of committed instruction
543system.cpu.commit.op_class_0::SimdFloatAdd 0 0.00% 63.84% # Class of committed instruction
544system.cpu.commit.op_class_0::SimdFloatAlu 0 0.00% 63.84% # Class of committed instruction
545system.cpu.commit.op_class_0::SimdFloatCmp 0 0.00% 63.84% # Class of committed instruction
546system.cpu.commit.op_class_0::SimdFloatCvt 0 0.00% 63.84% # Class of committed instruction
547system.cpu.commit.op_class_0::SimdFloatDiv 0 0.00% 63.84% # Class of committed instruction
548system.cpu.commit.op_class_0::SimdFloatMisc 0 0.00% 63.84% # Class of committed instruction
549system.cpu.commit.op_class_0::SimdFloatMult 0 0.00% 63.84% # Class of committed instruction
550system.cpu.commit.op_class_0::SimdFloatMultAcc 0 0.00% 63.84% # Class of committed instruction
551system.cpu.commit.op_class_0::SimdFloatSqrt 0 0.00% 63.84% # Class of committed instruction
552system.cpu.commit.op_class_0::MemRead 1132 20.13% 83.98% # Class of committed instruction
553system.cpu.commit.op_class_0::MemWrite 901 16.02% 100.00% # Class of committed instruction
554system.cpu.commit.op_class_0::IprAccess 0 0.00% 100.00% # Class of committed instruction
555system.cpu.commit.op_class_0::InstPrefetch 0 0.00% 100.00% # Class of committed instruction
556system.cpu.commit.op_class_0::total 5623 # Class of committed instruction
557system.cpu.commit.bw_lim_events 116 # number cycles where commit BW limit reached
558system.cpu.rob.rob_reads 23467 # The number of ROB reads
559system.cpu.rob.rob_writes 21056 # The number of ROB writes
560system.cpu.timesIdled 265 # Number of times that the entire CPU went into an idle state and unscheduled itself
561system.cpu.idleCycles 30642 # Total number of cycles that the CPU has spent unscheduled due to idling
562system.cpu.committedInsts 4986 # Number of Instructions Simulated
563system.cpu.committedOps 4986 # Number of Ops (including micro ops) Simulated
564system.cpu.cpi 9.005816 # CPI: Cycles Per Instruction
565system.cpu.cpi_total 9.005816 # CPI: Total CPI of All Threads
566system.cpu.ipc 0.111039 # IPC: Instructions Per Cycle
567system.cpu.ipc_total 0.111039 # IPC: Total IPC of All Threads
568system.cpu.int_regfile_reads 10418 # number of integer regfile reads
569system.cpu.int_regfile_writes 5064 # number of integer regfile writes
570system.cpu.fp_regfile_reads 3 # number of floating regfile reads
571system.cpu.fp_regfile_writes 1 # number of floating regfile writes
572system.cpu.misc_regfile_reads 158 # number of misc regfile reads
573system.cpu.dcache.tags.replacements 0 # number of replacements
574system.cpu.dcache.tags.tagsinuse 90.670819 # Cycle average of tags in use
575system.cpu.dcache.tags.total_refs 2302 # Total number of references to valid blocks.
576system.cpu.dcache.tags.sampled_refs 141 # Sample count of references to valid blocks.
577system.cpu.dcache.tags.avg_refs 16.326241 # Average number of references to valid blocks.
578system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
579system.cpu.dcache.tags.occ_blocks::cpu.data 90.670819 # Average occupied blocks per requestor
580system.cpu.dcache.tags.occ_percent::cpu.data 0.022136 # Average percentage of cache occupancy
581system.cpu.dcache.tags.occ_percent::total 0.022136 # Average percentage of cache occupancy
582system.cpu.dcache.tags.occ_task_id_blocks::1024 141 # Occupied blocks per task id
583system.cpu.dcache.tags.age_task_id_blocks_1024::0 36 # Occupied blocks per task id
584system.cpu.dcache.tags.age_task_id_blocks_1024::1 105 # Occupied blocks per task id
585system.cpu.dcache.tags.occ_task_id_percent::1024 0.034424 # Percentage of cache occupancy per task id
586system.cpu.dcache.tags.tag_accesses 5765 # Number of tag accesses
587system.cpu.dcache.tags.data_accesses 5765 # Number of data accesses
588system.cpu.dcache.ReadReq_hits::cpu.data 1746 # number of ReadReq hits
589system.cpu.dcache.ReadReq_hits::total 1746 # number of ReadReq hits
590system.cpu.dcache.WriteReq_hits::cpu.data 556 # number of WriteReq hits
591system.cpu.dcache.WriteReq_hits::total 556 # number of WriteReq hits
592system.cpu.dcache.demand_hits::cpu.data 2302 # number of demand (read+write) hits
593system.cpu.dcache.demand_hits::total 2302 # number of demand (read+write) hits
594system.cpu.dcache.overall_hits::cpu.data 2302 # number of overall hits
595system.cpu.dcache.overall_hits::total 2302 # number of overall hits
596system.cpu.dcache.ReadReq_misses::cpu.data 165 # number of ReadReq misses
597system.cpu.dcache.ReadReq_misses::total 165 # number of ReadReq misses
598system.cpu.dcache.WriteReq_misses::cpu.data 345 # number of WriteReq misses
599system.cpu.dcache.WriteReq_misses::total 345 # number of WriteReq misses
600system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
601system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
602system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
603system.cpu.dcache.overall_misses::total 510 # number of overall misses
604system.cpu.dcache.ReadReq_miss_latency::cpu.data 11734000 # number of ReadReq miss cycles
605system.cpu.dcache.ReadReq_miss_latency::total 11734000 # number of ReadReq miss cycles
606system.cpu.dcache.WriteReq_miss_latency::cpu.data 24014999 # number of WriteReq miss cycles
607system.cpu.dcache.WriteReq_miss_latency::total 24014999 # number of WriteReq miss cycles
608system.cpu.dcache.demand_miss_latency::cpu.data 35748999 # number of demand (read+write) miss cycles
609system.cpu.dcache.demand_miss_latency::total 35748999 # number of demand (read+write) miss cycles
610system.cpu.dcache.overall_miss_latency::cpu.data 35748999 # number of overall miss cycles
611system.cpu.dcache.overall_miss_latency::total 35748999 # number of overall miss cycles
612system.cpu.dcache.ReadReq_accesses::cpu.data 1911 # number of ReadReq accesses(hits+misses)
613system.cpu.dcache.ReadReq_accesses::total 1911 # number of ReadReq accesses(hits+misses)
614system.cpu.dcache.WriteReq_accesses::cpu.data 901 # number of WriteReq accesses(hits+misses)
615system.cpu.dcache.WriteReq_accesses::total 901 # number of WriteReq accesses(hits+misses)
616system.cpu.dcache.demand_accesses::cpu.data 2812 # number of demand (read+write) accesses
617system.cpu.dcache.demand_accesses::total 2812 # number of demand (read+write) accesses
618system.cpu.dcache.overall_accesses::cpu.data 2812 # number of overall (read+write) accesses
619system.cpu.dcache.overall_accesses::total 2812 # number of overall (read+write) accesses
620system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.086342 # miss rate for ReadReq accesses
621system.cpu.dcache.ReadReq_miss_rate::total 0.086342 # miss rate for ReadReq accesses
622system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.382908 # miss rate for WriteReq accesses
623system.cpu.dcache.WriteReq_miss_rate::total 0.382908 # miss rate for WriteReq accesses
624system.cpu.dcache.demand_miss_rate::cpu.data 0.181366 # miss rate for demand accesses
625system.cpu.dcache.demand_miss_rate::total 0.181366 # miss rate for demand accesses
626system.cpu.dcache.overall_miss_rate::cpu.data 0.181366 # miss rate for overall accesses
627system.cpu.dcache.overall_miss_rate::total 0.181366 # miss rate for overall accesses
628system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 71115.151515 # average ReadReq miss latency
629system.cpu.dcache.ReadReq_avg_miss_latency::total 71115.151515 # average ReadReq miss latency
630system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 69608.692754 # average WriteReq miss latency
631system.cpu.dcache.WriteReq_avg_miss_latency::total 69608.692754 # average WriteReq miss latency
632system.cpu.dcache.demand_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
633system.cpu.dcache.demand_avg_miss_latency::total 70096.076471 # average overall miss latency
634system.cpu.dcache.overall_avg_miss_latency::cpu.data 70096.076471 # average overall miss latency
635system.cpu.dcache.overall_avg_miss_latency::total 70096.076471 # average overall miss latency
636system.cpu.dcache.blocked_cycles::no_mshrs 587 # number of cycles access was blocked
637system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
638system.cpu.dcache.blocked::no_mshrs 10 # number of cycles access was blocked
639system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
640system.cpu.dcache.avg_blocked_cycles::no_mshrs 58.700000 # average number of cycles each access was blocked
641system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
642system.cpu.dcache.fast_writes 0 # number of fast writes performed
643system.cpu.dcache.cache_copies 0 # number of cache copies performed
644system.cpu.dcache.ReadReq_mshr_hits::cpu.data 74 # number of ReadReq MSHR hits
645system.cpu.dcache.ReadReq_mshr_hits::total 74 # number of ReadReq MSHR hits
646system.cpu.dcache.WriteReq_mshr_hits::cpu.data 295 # number of WriteReq MSHR hits
647system.cpu.dcache.WriteReq_mshr_hits::total 295 # number of WriteReq MSHR hits
648system.cpu.dcache.demand_mshr_hits::cpu.data 369 # number of demand (read+write) MSHR hits
649system.cpu.dcache.demand_mshr_hits::total 369 # number of demand (read+write) MSHR hits
650system.cpu.dcache.overall_mshr_hits::cpu.data 369 # number of overall MSHR hits
651system.cpu.dcache.overall_mshr_hits::total 369 # number of overall MSHR hits
652system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
653system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
654system.cpu.dcache.WriteReq_mshr_misses::cpu.data 50 # number of WriteReq MSHR misses
655system.cpu.dcache.WriteReq_mshr_misses::total 50 # number of WriteReq MSHR misses
656system.cpu.dcache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
657system.cpu.dcache.demand_mshr_misses::total 141 # number of demand (read+write) MSHR misses
658system.cpu.dcache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
659system.cpu.dcache.overall_mshr_misses::total 141 # number of overall MSHR misses
660system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7594500 # number of ReadReq MSHR miss cycles
661system.cpu.dcache.ReadReq_mshr_miss_latency::total 7594500 # number of ReadReq MSHR miss cycles
662system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 4083499 # number of WriteReq MSHR miss cycles
663system.cpu.dcache.WriteReq_mshr_miss_latency::total 4083499 # number of WriteReq MSHR miss cycles
664system.cpu.dcache.demand_mshr_miss_latency::cpu.data 11677999 # number of demand (read+write) MSHR miss cycles
665system.cpu.dcache.demand_mshr_miss_latency::total 11677999 # number of demand (read+write) MSHR miss cycles
666system.cpu.dcache.overall_mshr_miss_latency::cpu.data 11677999 # number of overall MSHR miss cycles
667system.cpu.dcache.overall_mshr_miss_latency::total 11677999 # number of overall MSHR miss cycles
668system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.047619 # mshr miss rate for ReadReq accesses
669system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.047619 # mshr miss rate for ReadReq accesses
670system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055494 # mshr miss rate for WriteReq accesses
671system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055494 # mshr miss rate for WriteReq accesses
672system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for demand accesses
673system.cpu.dcache.demand_mshr_miss_rate::total 0.050142 # mshr miss rate for demand accesses
674system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.050142 # mshr miss rate for overall accesses
675system.cpu.dcache.overall_mshr_miss_rate::total 0.050142 # mshr miss rate for overall accesses
676system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 83456.043956 # average ReadReq mshr miss latency
677system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 83456.043956 # average ReadReq mshr miss latency
678system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 81669.980000 # average WriteReq mshr miss latency
679system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 81669.980000 # average WriteReq mshr miss latency
680system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
681system.cpu.dcache.demand_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
682system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 82822.687943 # average overall mshr miss latency
683system.cpu.dcache.overall_avg_mshr_miss_latency::total 82822.687943 # average overall mshr miss latency
684system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
685system.cpu.icache.tags.replacements 17 # number of replacements
686system.cpu.icache.tags.tagsinuse 156.398029 # Cycle average of tags in use
687system.cpu.icache.tags.total_refs 1547 # Total number of references to valid blocks.
688system.cpu.icache.tags.sampled_refs 331 # Sample count of references to valid blocks.
689system.cpu.icache.tags.avg_refs 4.673716 # Average number of references to valid blocks.
690system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
691system.cpu.icache.tags.occ_blocks::cpu.inst 156.398029 # Average occupied blocks per requestor
692system.cpu.icache.tags.occ_percent::cpu.inst 0.076366 # Average percentage of cache occupancy
693system.cpu.icache.tags.occ_percent::total 0.076366 # Average percentage of cache occupancy
694system.cpu.icache.tags.occ_task_id_blocks::1024 314 # Occupied blocks per task id
695system.cpu.icache.tags.age_task_id_blocks_1024::0 146 # Occupied blocks per task id
696system.cpu.icache.tags.age_task_id_blocks_1024::1 168 # Occupied blocks per task id
697system.cpu.icache.tags.occ_task_id_percent::1024 0.153320 # Percentage of cache occupancy per task id
698system.cpu.icache.tags.tag_accesses 4289 # Number of tag accesses
699system.cpu.icache.tags.data_accesses 4289 # Number of data accesses
700system.cpu.icache.ReadReq_hits::cpu.inst 1547 # number of ReadReq hits
701system.cpu.icache.ReadReq_hits::total 1547 # number of ReadReq hits
702system.cpu.icache.demand_hits::cpu.inst 1547 # number of demand (read+write) hits
703system.cpu.icache.demand_hits::total 1547 # number of demand (read+write) hits
704system.cpu.icache.overall_hits::cpu.inst 1547 # number of overall hits
705system.cpu.icache.overall_hits::total 1547 # number of overall hits
706system.cpu.icache.ReadReq_misses::cpu.inst 432 # number of ReadReq misses
707system.cpu.icache.ReadReq_misses::total 432 # number of ReadReq misses
708system.cpu.icache.demand_misses::cpu.inst 432 # number of demand (read+write) misses
709system.cpu.icache.demand_misses::total 432 # number of demand (read+write) misses
710system.cpu.icache.overall_misses::cpu.inst 432 # number of overall misses
711system.cpu.icache.overall_misses::total 432 # number of overall misses
712system.cpu.icache.ReadReq_miss_latency::cpu.inst 32419500 # number of ReadReq miss cycles
713system.cpu.icache.ReadReq_miss_latency::total 32419500 # number of ReadReq miss cycles
714system.cpu.icache.demand_miss_latency::cpu.inst 32419500 # number of demand (read+write) miss cycles
715system.cpu.icache.demand_miss_latency::total 32419500 # number of demand (read+write) miss cycles
716system.cpu.icache.overall_miss_latency::cpu.inst 32419500 # number of overall miss cycles
717system.cpu.icache.overall_miss_latency::total 32419500 # number of overall miss cycles
718system.cpu.icache.ReadReq_accesses::cpu.inst 1979 # number of ReadReq accesses(hits+misses)
719system.cpu.icache.ReadReq_accesses::total 1979 # number of ReadReq accesses(hits+misses)
720system.cpu.icache.demand_accesses::cpu.inst 1979 # number of demand (read+write) accesses
721system.cpu.icache.demand_accesses::total 1979 # number of demand (read+write) accesses
722system.cpu.icache.overall_accesses::cpu.inst 1979 # number of overall (read+write) accesses
723system.cpu.icache.overall_accesses::total 1979 # number of overall (read+write) accesses
724system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.218292 # miss rate for ReadReq accesses
725system.cpu.icache.ReadReq_miss_rate::total 0.218292 # miss rate for ReadReq accesses
726system.cpu.icache.demand_miss_rate::cpu.inst 0.218292 # miss rate for demand accesses
727system.cpu.icache.demand_miss_rate::total 0.218292 # miss rate for demand accesses
728system.cpu.icache.overall_miss_rate::cpu.inst 0.218292 # miss rate for overall accesses
729system.cpu.icache.overall_miss_rate::total 0.218292 # miss rate for overall accesses
730system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 75045.138889 # average ReadReq miss latency
731system.cpu.icache.ReadReq_avg_miss_latency::total 75045.138889 # average ReadReq miss latency
732system.cpu.icache.demand_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
733system.cpu.icache.demand_avg_miss_latency::total 75045.138889 # average overall miss latency
734system.cpu.icache.overall_avg_miss_latency::cpu.inst 75045.138889 # average overall miss latency
735system.cpu.icache.overall_avg_miss_latency::total 75045.138889 # average overall miss latency
736system.cpu.icache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
737system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
738system.cpu.icache.blocked::no_mshrs 0 # number of cycles access was blocked
739system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
740system.cpu.icache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
741system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
742system.cpu.icache.fast_writes 0 # number of fast writes performed
743system.cpu.icache.cache_copies 0 # number of cache copies performed
744system.cpu.icache.ReadReq_mshr_hits::cpu.inst 101 # number of ReadReq MSHR hits
745system.cpu.icache.ReadReq_mshr_hits::total 101 # number of ReadReq MSHR hits
746system.cpu.icache.demand_mshr_hits::cpu.inst 101 # number of demand (read+write) MSHR hits
747system.cpu.icache.demand_mshr_hits::total 101 # number of demand (read+write) MSHR hits
748system.cpu.icache.overall_mshr_hits::cpu.inst 101 # number of overall MSHR hits
749system.cpu.icache.overall_mshr_hits::total 101 # number of overall MSHR hits
750system.cpu.icache.ReadReq_mshr_misses::cpu.inst 331 # number of ReadReq MSHR misses
751system.cpu.icache.ReadReq_mshr_misses::total 331 # number of ReadReq MSHR misses
752system.cpu.icache.demand_mshr_misses::cpu.inst 331 # number of demand (read+write) MSHR misses
753system.cpu.icache.demand_mshr_misses::total 331 # number of demand (read+write) MSHR misses
754system.cpu.icache.overall_mshr_misses::cpu.inst 331 # number of overall MSHR misses
755system.cpu.icache.overall_mshr_misses::total 331 # number of overall MSHR misses
756system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 25901500 # number of ReadReq MSHR miss cycles
757system.cpu.icache.ReadReq_mshr_miss_latency::total 25901500 # number of ReadReq MSHR miss cycles
758system.cpu.icache.demand_mshr_miss_latency::cpu.inst 25901500 # number of demand (read+write) MSHR miss cycles
759system.cpu.icache.demand_mshr_miss_latency::total 25901500 # number of demand (read+write) MSHR miss cycles
760system.cpu.icache.overall_mshr_miss_latency::cpu.inst 25901500 # number of overall MSHR miss cycles
761system.cpu.icache.overall_mshr_miss_latency::total 25901500 # number of overall MSHR miss cycles
762system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for ReadReq accesses
763system.cpu.icache.ReadReq_mshr_miss_rate::total 0.167256 # mshr miss rate for ReadReq accesses
764system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for demand accesses
765system.cpu.icache.demand_mshr_miss_rate::total 0.167256 # mshr miss rate for demand accesses
766system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.167256 # mshr miss rate for overall accesses
767system.cpu.icache.overall_mshr_miss_rate::total 0.167256 # mshr miss rate for overall accesses
768system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 78252.265861 # average ReadReq mshr miss latency
769system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 78252.265861 # average ReadReq mshr miss latency
770system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
771system.cpu.icache.demand_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
772system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 78252.265861 # average overall mshr miss latency
773system.cpu.icache.overall_avg_mshr_miss_latency::total 78252.265861 # average overall mshr miss latency
774system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
775system.cpu.l2cache.tags.replacements 0 # number of replacements
776system.cpu.l2cache.tags.tagsinuse 215.838012 # Cycle average of tags in use
777system.cpu.l2cache.tags.total_refs 20 # Total number of references to valid blocks.
778system.cpu.l2cache.tags.sampled_refs 419 # Sample count of references to valid blocks.
779system.cpu.l2cache.tags.avg_refs 0.047733 # Average number of references to valid blocks.
780system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
781system.cpu.l2cache.tags.occ_blocks::cpu.inst 158.321641 # Average occupied blocks per requestor
782system.cpu.l2cache.tags.occ_blocks::cpu.data 57.516370 # Average occupied blocks per requestor
783system.cpu.l2cache.tags.occ_percent::cpu.inst 0.004832 # Average percentage of cache occupancy
784system.cpu.l2cache.tags.occ_percent::cpu.data 0.001755 # Average percentage of cache occupancy
785system.cpu.l2cache.tags.occ_percent::total 0.006587 # Average percentage of cache occupancy
786system.cpu.l2cache.tags.occ_task_id_blocks::1024 419 # Occupied blocks per task id
787system.cpu.l2cache.tags.age_task_id_blocks_1024::0 184 # Occupied blocks per task id
788system.cpu.l2cache.tags.age_task_id_blocks_1024::1 235 # Occupied blocks per task id
789system.cpu.l2cache.tags.occ_task_id_percent::1024 0.012787 # Percentage of cache occupancy per task id
790system.cpu.l2cache.tags.tag_accesses 4381 # Number of tag accesses
791system.cpu.l2cache.tags.data_accesses 4381 # Number of data accesses
792system.cpu.l2cache.ReadCleanReq_hits::cpu.inst 3 # number of ReadCleanReq hits
793system.cpu.l2cache.ReadCleanReq_hits::total 3 # number of ReadCleanReq hits
794system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
795system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
796system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
797system.cpu.l2cache.overall_hits::total 3 # number of overall hits
798system.cpu.l2cache.ReadExReq_misses::cpu.data 50 # number of ReadExReq misses
799system.cpu.l2cache.ReadExReq_misses::total 50 # number of ReadExReq misses
800system.cpu.l2cache.ReadCleanReq_misses::cpu.inst 328 # number of ReadCleanReq misses
801system.cpu.l2cache.ReadCleanReq_misses::total 328 # number of ReadCleanReq misses
802system.cpu.l2cache.ReadSharedReq_misses::cpu.data 91 # number of ReadSharedReq misses
803system.cpu.l2cache.ReadSharedReq_misses::total 91 # number of ReadSharedReq misses
804system.cpu.l2cache.demand_misses::cpu.inst 328 # number of demand (read+write) misses
805system.cpu.l2cache.demand_misses::cpu.data 141 # number of demand (read+write) misses
806system.cpu.l2cache.demand_misses::total 469 # number of demand (read+write) misses
807system.cpu.l2cache.overall_misses::cpu.inst 328 # number of overall misses
808system.cpu.l2cache.overall_misses::cpu.data 141 # number of overall misses
809system.cpu.l2cache.overall_misses::total 469 # number of overall misses
810system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 4007500 # number of ReadExReq miss cycles
811system.cpu.l2cache.ReadExReq_miss_latency::total 4007500 # number of ReadExReq miss cycles
812system.cpu.l2cache.ReadCleanReq_miss_latency::cpu.inst 25373500 # number of ReadCleanReq miss cycles
813system.cpu.l2cache.ReadCleanReq_miss_latency::total 25373500 # number of ReadCleanReq miss cycles
814system.cpu.l2cache.ReadSharedReq_miss_latency::cpu.data 7455000 # number of ReadSharedReq miss cycles
815system.cpu.l2cache.ReadSharedReq_miss_latency::total 7455000 # number of ReadSharedReq miss cycles
816system.cpu.l2cache.demand_miss_latency::cpu.inst 25373500 # number of demand (read+write) miss cycles
817system.cpu.l2cache.demand_miss_latency::cpu.data 11462500 # number of demand (read+write) miss cycles
818system.cpu.l2cache.demand_miss_latency::total 36836000 # number of demand (read+write) miss cycles
819system.cpu.l2cache.overall_miss_latency::cpu.inst 25373500 # number of overall miss cycles
820system.cpu.l2cache.overall_miss_latency::cpu.data 11462500 # number of overall miss cycles
821system.cpu.l2cache.overall_miss_latency::total 36836000 # number of overall miss cycles
822system.cpu.l2cache.ReadExReq_accesses::cpu.data 50 # number of ReadExReq accesses(hits+misses)
823system.cpu.l2cache.ReadExReq_accesses::total 50 # number of ReadExReq accesses(hits+misses)
824system.cpu.l2cache.ReadCleanReq_accesses::cpu.inst 331 # number of ReadCleanReq accesses(hits+misses)
825system.cpu.l2cache.ReadCleanReq_accesses::total 331 # number of ReadCleanReq accesses(hits+misses)
826system.cpu.l2cache.ReadSharedReq_accesses::cpu.data 91 # number of ReadSharedReq accesses(hits+misses)
827system.cpu.l2cache.ReadSharedReq_accesses::total 91 # number of ReadSharedReq accesses(hits+misses)
828system.cpu.l2cache.demand_accesses::cpu.inst 331 # number of demand (read+write) accesses
829system.cpu.l2cache.demand_accesses::cpu.data 141 # number of demand (read+write) accesses
830system.cpu.l2cache.demand_accesses::total 472 # number of demand (read+write) accesses
831system.cpu.l2cache.overall_accesses::cpu.inst 331 # number of overall (read+write) accesses
832system.cpu.l2cache.overall_accesses::cpu.data 141 # number of overall (read+write) accesses
833system.cpu.l2cache.overall_accesses::total 472 # number of overall (read+write) accesses
834system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
835system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
836system.cpu.l2cache.ReadCleanReq_miss_rate::cpu.inst 0.990937 # miss rate for ReadCleanReq accesses
837system.cpu.l2cache.ReadCleanReq_miss_rate::total 0.990937 # miss rate for ReadCleanReq accesses
838system.cpu.l2cache.ReadSharedReq_miss_rate::cpu.data 1 # miss rate for ReadSharedReq accesses
839system.cpu.l2cache.ReadSharedReq_miss_rate::total 1 # miss rate for ReadSharedReq accesses
840system.cpu.l2cache.demand_miss_rate::cpu.inst 0.990937 # miss rate for demand accesses
841system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
842system.cpu.l2cache.demand_miss_rate::total 0.993644 # miss rate for demand accesses
843system.cpu.l2cache.overall_miss_rate::cpu.inst 0.990937 # miss rate for overall accesses
844system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
845system.cpu.l2cache.overall_miss_rate::total 0.993644 # miss rate for overall accesses
846system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 80150 # average ReadExReq miss latency
847system.cpu.l2cache.ReadExReq_avg_miss_latency::total 80150 # average ReadExReq miss latency
848system.cpu.l2cache.ReadCleanReq_avg_miss_latency::cpu.inst 77358.231707 # average ReadCleanReq miss latency
849system.cpu.l2cache.ReadCleanReq_avg_miss_latency::total 77358.231707 # average ReadCleanReq miss latency
850system.cpu.l2cache.ReadSharedReq_avg_miss_latency::cpu.data 81923.076923 # average ReadSharedReq miss latency
851system.cpu.l2cache.ReadSharedReq_avg_miss_latency::total 81923.076923 # average ReadSharedReq miss latency
852system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
853system.cpu.l2cache.demand_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
854system.cpu.l2cache.demand_avg_miss_latency::total 78541.577825 # average overall miss latency
855system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 77358.231707 # average overall miss latency
856system.cpu.l2cache.overall_avg_miss_latency::cpu.data 81294.326241 # average overall miss latency
857system.cpu.l2cache.overall_avg_miss_latency::total 78541.577825 # average overall miss latency
858system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
859system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
860system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
861system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
862system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
863system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
864system.cpu.l2cache.fast_writes 0 # number of fast writes performed
865system.cpu.l2cache.cache_copies 0 # number of cache copies performed
866system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 50 # number of ReadExReq MSHR misses
867system.cpu.l2cache.ReadExReq_mshr_misses::total 50 # number of ReadExReq MSHR misses
868system.cpu.l2cache.ReadCleanReq_mshr_misses::cpu.inst 328 # number of ReadCleanReq MSHR misses
869system.cpu.l2cache.ReadCleanReq_mshr_misses::total 328 # number of ReadCleanReq MSHR misses
870system.cpu.l2cache.ReadSharedReq_mshr_misses::cpu.data 91 # number of ReadSharedReq MSHR misses
871system.cpu.l2cache.ReadSharedReq_mshr_misses::total 91 # number of ReadSharedReq MSHR misses
872system.cpu.l2cache.demand_mshr_misses::cpu.inst 328 # number of demand (read+write) MSHR misses
873system.cpu.l2cache.demand_mshr_misses::cpu.data 141 # number of demand (read+write) MSHR misses
874system.cpu.l2cache.demand_mshr_misses::total 469 # number of demand (read+write) MSHR misses
875system.cpu.l2cache.overall_mshr_misses::cpu.inst 328 # number of overall MSHR misses
876system.cpu.l2cache.overall_mshr_misses::cpu.data 141 # number of overall MSHR misses
877system.cpu.l2cache.overall_mshr_misses::total 469 # number of overall MSHR misses
878system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3507500 # number of ReadExReq MSHR miss cycles
879system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3507500 # number of ReadExReq MSHR miss cycles
880system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::cpu.inst 22093500 # number of ReadCleanReq MSHR miss cycles
881system.cpu.l2cache.ReadCleanReq_mshr_miss_latency::total 22093500 # number of ReadCleanReq MSHR miss cycles
882system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::cpu.data 6545000 # number of ReadSharedReq MSHR miss cycles
883system.cpu.l2cache.ReadSharedReq_mshr_miss_latency::total 6545000 # number of ReadSharedReq MSHR miss cycles
884system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 22093500 # number of demand (read+write) MSHR miss cycles
885system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 10052500 # number of demand (read+write) MSHR miss cycles
886system.cpu.l2cache.demand_mshr_miss_latency::total 32146000 # number of demand (read+write) MSHR miss cycles
887system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 22093500 # number of overall MSHR miss cycles
888system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 10052500 # number of overall MSHR miss cycles
889system.cpu.l2cache.overall_mshr_miss_latency::total 32146000 # number of overall MSHR miss cycles
890system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
891system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
892system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for ReadCleanReq accesses
893system.cpu.l2cache.ReadCleanReq_mshr_miss_rate::total 0.990937 # mshr miss rate for ReadCleanReq accesses
894system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadSharedReq accesses
895system.cpu.l2cache.ReadSharedReq_mshr_miss_rate::total 1 # mshr miss rate for ReadSharedReq accesses
896system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for demand accesses
897system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
898system.cpu.l2cache.demand_mshr_miss_rate::total 0.993644 # mshr miss rate for demand accesses
899system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.990937 # mshr miss rate for overall accesses
900system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
901system.cpu.l2cache.overall_mshr_miss_rate::total 0.993644 # mshr miss rate for overall accesses
902system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 70150 # average ReadExReq mshr miss latency
903system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 70150 # average ReadExReq mshr miss latency
904system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::cpu.inst 67358.231707 # average ReadCleanReq mshr miss latency
905system.cpu.l2cache.ReadCleanReq_avg_mshr_miss_latency::total 67358.231707 # average ReadCleanReq mshr miss latency
906system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::cpu.data 71923.076923 # average ReadSharedReq mshr miss latency
907system.cpu.l2cache.ReadSharedReq_avg_mshr_miss_latency::total 71923.076923 # average ReadSharedReq mshr miss latency
908system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
909system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
910system.cpu.l2cache.demand_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
911system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 67358.231707 # average overall mshr miss latency
912system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 71294.326241 # average overall mshr miss latency
913system.cpu.l2cache.overall_avg_mshr_miss_latency::total 68541.577825 # average overall mshr miss latency
914system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
|
| 915system.cpu.toL2Bus.snoop_filter.tot_requests 489 # Total number of requests made to the snoop filter.
916system.cpu.toL2Bus.snoop_filter.hit_single_requests 17 # Number of requests hitting in the snoop filter with a single holder of the requested data.
917system.cpu.toL2Bus.snoop_filter.hit_multi_requests 0 # Number of requests hitting in the snoop filter with multiple (>1) holders of the requested data.
918system.cpu.toL2Bus.snoop_filter.tot_snoops 0 # Total number of snoops made to the snoop filter.
919system.cpu.toL2Bus.snoop_filter.hit_single_snoops 0 # Number of snoops hitting in the snoop filter with a single holder of the requested data.
920system.cpu.toL2Bus.snoop_filter.hit_multi_snoops 0 # Number of snoops hitting in the snoop filter with multiple (>1) holders of the requested data.
|
915system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
916system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution
917system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
918system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
919system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
920system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution
921system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
922system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
923system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
924system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes)
925system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
926system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
927system.cpu.toL2Bus.snoops 0 # Total snoops (count)
928system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram
| 921system.cpu.toL2Bus.trans_dist::ReadResp 422 # Transaction distribution
922system.cpu.toL2Bus.trans_dist::CleanEvict 17 # Transaction distribution
923system.cpu.toL2Bus.trans_dist::ReadExReq 50 # Transaction distribution
924system.cpu.toL2Bus.trans_dist::ReadExResp 50 # Transaction distribution
925system.cpu.toL2Bus.trans_dist::ReadCleanReq 331 # Transaction distribution
926system.cpu.toL2Bus.trans_dist::ReadSharedReq 91 # Transaction distribution
927system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 679 # Packet count per connected master and slave (bytes)
928system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 282 # Packet count per connected master and slave (bytes)
929system.cpu.toL2Bus.pkt_count::total 961 # Packet count per connected master and slave (bytes)
930system.cpu.toL2Bus.pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21184 # Cumulative packet size per connected master and slave (bytes)
931system.cpu.toL2Bus.pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9024 # Cumulative packet size per connected master and slave (bytes)
932system.cpu.toL2Bus.pkt_size::total 30208 # Cumulative packet size per connected master and slave (bytes)
933system.cpu.toL2Bus.snoops 0 # Total snoops (count)
934system.cpu.toL2Bus.snoop_fanout::samples 489 # Request fanout histogram
|
929system.cpu.toL2Bus.snoop_fanout::mean 1 # Request fanout histogram
| 935system.cpu.toL2Bus.snoop_fanout::mean 0 # Request fanout histogram
|
930system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
931system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
| 936system.cpu.toL2Bus.snoop_fanout::stdev 0 # Request fanout histogram
937system.cpu.toL2Bus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
|
932system.cpu.toL2Bus.snoop_fanout::0 0 0.00% 0.00% # Request fanout histogram
933system.cpu.toL2Bus.snoop_fanout::1 489 100.00% 100.00% # Request fanout histogram
| 938system.cpu.toL2Bus.snoop_fanout::0 489 100.00% 100.00% # Request fanout histogram
939system.cpu.toL2Bus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
|
934system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
935system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
| 940system.cpu.toL2Bus.snoop_fanout::2 0 0.00% 100.00% # Request fanout histogram
941system.cpu.toL2Bus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
|
936system.cpu.toL2Bus.snoop_fanout::min_value 1 # Request fanout histogram
937system.cpu.toL2Bus.snoop_fanout::max_value 1 # Request fanout histogram
| 942system.cpu.toL2Bus.snoop_fanout::min_value 0 # Request fanout histogram
943system.cpu.toL2Bus.snoop_fanout::max_value 0 # Request fanout histogram
|
938system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram
939system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
940system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
941system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
942system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
943system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
944system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
945system.membus.trans_dist::ReadResp 419 # Transaction distribution
946system.membus.trans_dist::ReadExReq 50 # Transaction distribution
947system.membus.trans_dist::ReadExResp 50 # Transaction distribution
948system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
949system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
950system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
951system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
952system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
953system.membus.snoops 0 # Total snoops (count)
954system.membus.snoop_fanout::samples 469 # Request fanout histogram
955system.membus.snoop_fanout::mean 0 # Request fanout histogram
956system.membus.snoop_fanout::stdev 0 # Request fanout histogram
957system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
958system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
959system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
960system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
961system.membus.snoop_fanout::min_value 0 # Request fanout histogram
962system.membus.snoop_fanout::max_value 0 # Request fanout histogram
963system.membus.snoop_fanout::total 469 # Request fanout histogram
964system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
965system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
966system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
967system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
968
969---------- End Simulation Statistics ----------
| 944system.cpu.toL2Bus.snoop_fanout::total 489 # Request fanout histogram
945system.cpu.toL2Bus.reqLayer0.occupancy 244500 # Layer occupancy (ticks)
946system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
947system.cpu.toL2Bus.respLayer0.occupancy 496500 # Layer occupancy (ticks)
948system.cpu.toL2Bus.respLayer0.utilization 2.2 # Layer utilization (%)
949system.cpu.toL2Bus.respLayer1.occupancy 211500 # Layer occupancy (ticks)
950system.cpu.toL2Bus.respLayer1.utilization 0.9 # Layer utilization (%)
951system.membus.trans_dist::ReadResp 419 # Transaction distribution
952system.membus.trans_dist::ReadExReq 50 # Transaction distribution
953system.membus.trans_dist::ReadExResp 50 # Transaction distribution
954system.membus.trans_dist::ReadSharedReq 419 # Transaction distribution
955system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 938 # Packet count per connected master and slave (bytes)
956system.membus.pkt_count::total 938 # Packet count per connected master and slave (bytes)
957system.membus.pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30016 # Cumulative packet size per connected master and slave (bytes)
958system.membus.pkt_size::total 30016 # Cumulative packet size per connected master and slave (bytes)
959system.membus.snoops 0 # Total snoops (count)
960system.membus.snoop_fanout::samples 469 # Request fanout histogram
961system.membus.snoop_fanout::mean 0 # Request fanout histogram
962system.membus.snoop_fanout::stdev 0 # Request fanout histogram
963system.membus.snoop_fanout::underflows 0 0.00% 0.00% # Request fanout histogram
964system.membus.snoop_fanout::0 469 100.00% 100.00% # Request fanout histogram
965system.membus.snoop_fanout::1 0 0.00% 100.00% # Request fanout histogram
966system.membus.snoop_fanout::overflows 0 0.00% 100.00% # Request fanout histogram
967system.membus.snoop_fanout::min_value 0 # Request fanout histogram
968system.membus.snoop_fanout::max_value 0 # Request fanout histogram
969system.membus.snoop_fanout::total 469 # Request fanout histogram
970system.membus.reqLayer0.occupancy 580000 # Layer occupancy (ticks)
971system.membus.reqLayer0.utilization 2.6 # Layer utilization (%)
972system.membus.respLayer1.occupancy 2493500 # Layer occupancy (ticks)
973system.membus.respLayer1.utilization 11.1 # Layer utilization (%)
974
975---------- End Simulation Statistics ----------
|