1
2---------- Begin Simulation Statistics ----------
3sim_seconds 0.000022 # Number of seconds simulated
4sim_ticks 21898500 # Number of ticks simulated
5final_tick 21898500 # Number of ticks from beginning of simulation (restored from checkpoints and never reset)
6sim_freq 1000000000000 # Frequency of simulated ticks
7host_inst_rate 64871 # Simulator instruction rate (inst/s)
8host_op_rate 64859 # Simulator op (including micro ops) rate (op/s)
9host_tick_rate 275425114 # Simulator tick rate (ticks/s)
10host_mem_usage 255508 # Number of bytes of host memory used
11host_seconds 0.08 # Real time elapsed on the host
12sim_insts 5156 # Number of instructions simulated
13sim_ops 5156 # Number of ops (including micro ops) simulated
14system.physmem.bytes_read::cpu.inst 21440 # Number of bytes read from this memory
15system.physmem.bytes_read::cpu.data 9088 # Number of bytes read from this memory
16system.physmem.bytes_read::total 30528 # Number of bytes read from this memory
17system.physmem.bytes_inst_read::cpu.inst 21440 # Number of instructions bytes read from this memory
18system.physmem.bytes_inst_read::total 21440 # Number of instructions bytes read from this memory
19system.physmem.num_reads::cpu.inst 335 # Number of read requests responded to by this memory
20system.physmem.num_reads::cpu.data 142 # Number of read requests responded to by this memory
21system.physmem.num_reads::total 477 # Number of read requests responded to by this memory
22system.physmem.bw_read::cpu.inst 979062493 # Total read bandwidth from this memory (bytes/s)
23system.physmem.bw_read::cpu.data 415005594 # Total read bandwidth from this memory (bytes/s)
24system.physmem.bw_read::total 1394068087 # Total read bandwidth from this memory (bytes/s)
25system.physmem.bw_inst_read::cpu.inst 979062493 # Instruction read bandwidth from this memory (bytes/s)
26system.physmem.bw_inst_read::total 979062493 # Instruction read bandwidth from this memory (bytes/s)
27system.physmem.bw_total::cpu.inst 979062493 # Total bandwidth to/from this memory (bytes/s)
28system.physmem.bw_total::cpu.data 415005594 # Total bandwidth to/from this memory (bytes/s)
29system.physmem.bw_total::total 1394068087 # Total bandwidth to/from this memory (bytes/s)
30system.physmem.readReqs 477 # Number of read requests accepted
31system.physmem.writeReqs 0 # Number of write requests accepted
32system.physmem.readBursts 477 # Number of DRAM read bursts, including those serviced by the write queue
33system.physmem.writeBursts 0 # Number of DRAM write bursts, including those merged in the write queue
34system.physmem.bytesReadDRAM 30528 # Total number of bytes read from DRAM
35system.physmem.bytesReadWrQ 0 # Total number of bytes read from write queue
36system.physmem.bytesWritten 0 # Total number of bytes written to DRAM
37system.physmem.bytesReadSys 30528 # Total read bytes from the system interface side
38system.physmem.bytesWrittenSys 0 # Total written bytes from the system interface side
39system.physmem.servicedByWrQ 0 # Number of DRAM read bursts serviced by the write queue
40system.physmem.mergedWrBursts 0 # Number of DRAM write bursts merged with an existing one
41system.physmem.neitherReadNorWriteReqs 0 # Number of requests that are neither read nor write
42system.physmem.perBankRdBursts::0 30 # Per bank write bursts
43system.physmem.perBankRdBursts::1 0 # Per bank write bursts
44system.physmem.perBankRdBursts::2 1 # Per bank write bursts
45system.physmem.perBankRdBursts::3 0 # Per bank write bursts
46system.physmem.perBankRdBursts::4 7 # Per bank write bursts
47system.physmem.perBankRdBursts::5 3 # Per bank write bursts
48system.physmem.perBankRdBursts::6 13 # Per bank write bursts
49system.physmem.perBankRdBursts::7 54 # Per bank write bursts
50system.physmem.perBankRdBursts::8 63 # Per bank write bursts
51system.physmem.perBankRdBursts::9 77 # Per bank write bursts
52system.physmem.perBankRdBursts::10 44 # Per bank write bursts
53system.physmem.perBankRdBursts::11 20 # Per bank write bursts
54system.physmem.perBankRdBursts::12 51 # Per bank write bursts
55system.physmem.perBankRdBursts::13 29 # Per bank write bursts
56system.physmem.perBankRdBursts::14 77 # Per bank write bursts
57system.physmem.perBankRdBursts::15 8 # Per bank write bursts
58system.physmem.perBankWrBursts::0 0 # Per bank write bursts
59system.physmem.perBankWrBursts::1 0 # Per bank write bursts
60system.physmem.perBankWrBursts::2 0 # Per bank write bursts
61system.physmem.perBankWrBursts::3 0 # Per bank write bursts
62system.physmem.perBankWrBursts::4 0 # Per bank write bursts
63system.physmem.perBankWrBursts::5 0 # Per bank write bursts
64system.physmem.perBankWrBursts::6 0 # Per bank write bursts
65system.physmem.perBankWrBursts::7 0 # Per bank write bursts
66system.physmem.perBankWrBursts::8 0 # Per bank write bursts
67system.physmem.perBankWrBursts::9 0 # Per bank write bursts
68system.physmem.perBankWrBursts::10 0 # Per bank write bursts
69system.physmem.perBankWrBursts::11 0 # Per bank write bursts
70system.physmem.perBankWrBursts::12 0 # Per bank write bursts
71system.physmem.perBankWrBursts::13 0 # Per bank write bursts
72system.physmem.perBankWrBursts::14 0 # Per bank write bursts
73system.physmem.perBankWrBursts::15 0 # Per bank write bursts
74system.physmem.numRdRetry 0 # Number of times read queue was full causing retry
75system.physmem.numWrRetry 0 # Number of times write queue was full causing retry
76system.physmem.totGap 21819000 # Total gap between requests
77system.physmem.readPktSize::0 0 # Read request sizes (log2)
78system.physmem.readPktSize::1 0 # Read request sizes (log2)
79system.physmem.readPktSize::2 0 # Read request sizes (log2)
80system.physmem.readPktSize::3 0 # Read request sizes (log2)
81system.physmem.readPktSize::4 0 # Read request sizes (log2)
82system.physmem.readPktSize::5 0 # Read request sizes (log2)
83system.physmem.readPktSize::6 477 # Read request sizes (log2)
84system.physmem.writePktSize::0 0 # Write request sizes (log2)
85system.physmem.writePktSize::1 0 # Write request sizes (log2)
86system.physmem.writePktSize::2 0 # Write request sizes (log2)
87system.physmem.writePktSize::3 0 # Write request sizes (log2)
88system.physmem.writePktSize::4 0 # Write request sizes (log2)
89system.physmem.writePktSize::5 0 # Write request sizes (log2)
90system.physmem.writePktSize::6 0 # Write request sizes (log2)
91system.physmem.rdQLenPdf::0 285 # What read queue length does an incoming req see
92system.physmem.rdQLenPdf::1 132 # What read queue length does an incoming req see
93system.physmem.rdQLenPdf::2 41 # What read queue length does an incoming req see
94system.physmem.rdQLenPdf::3 15 # What read queue length does an incoming req see
95system.physmem.rdQLenPdf::4 4 # What read queue length does an incoming req see
96system.physmem.rdQLenPdf::5 0 # What read queue length does an incoming req see
97system.physmem.rdQLenPdf::6 0 # What read queue length does an incoming req see
98system.physmem.rdQLenPdf::7 0 # What read queue length does an incoming req see
99system.physmem.rdQLenPdf::8 0 # What read queue length does an incoming req see
100system.physmem.rdQLenPdf::9 0 # What read queue length does an incoming req see
101system.physmem.rdQLenPdf::10 0 # What read queue length does an incoming req see
102system.physmem.rdQLenPdf::11 0 # What read queue length does an incoming req see
103system.physmem.rdQLenPdf::12 0 # What read queue length does an incoming req see

--- 43 unchanged lines hidden (view full) ---

147system.physmem.wrQLenPdf::24 0 # What write queue length does an incoming req see
148system.physmem.wrQLenPdf::25 0 # What write queue length does an incoming req see
149system.physmem.wrQLenPdf::26 0 # What write queue length does an incoming req see
150system.physmem.wrQLenPdf::27 0 # What write queue length does an incoming req see
151system.physmem.wrQLenPdf::28 0 # What write queue length does an incoming req see
152system.physmem.wrQLenPdf::29 0 # What write queue length does an incoming req see
153system.physmem.wrQLenPdf::30 0 # What write queue length does an incoming req see
154system.physmem.wrQLenPdf::31 0 # What write queue length does an incoming req see
155system.physmem.bytesPerActivate::samples 118 # Bytes accessed per row activation
156system.physmem.bytesPerActivate::mean 230.508475 # Bytes accessed per row activation
157system.physmem.bytesPerActivate::gmean 147.858901 # Bytes accessed per row activation
158system.physmem.bytesPerActivate::stdev 317.434070 # Bytes accessed per row activation
159system.physmem.bytesPerActivate::64 46 38.98% 38.98% # Bytes accessed per row activation
160system.physmem.bytesPerActivate::128 20 16.95% 55.93% # Bytes accessed per row activation
161system.physmem.bytesPerActivate::192 19 16.10% 72.03% # Bytes accessed per row activation
162system.physmem.bytesPerActivate::256 8 6.78% 78.81% # Bytes accessed per row activation
163system.physmem.bytesPerActivate::320 7 5.93% 84.75% # Bytes accessed per row activation
164system.physmem.bytesPerActivate::384 3 2.54% 87.29% # Bytes accessed per row activation
165system.physmem.bytesPerActivate::448 4 3.39% 90.68% # Bytes accessed per row activation
166system.physmem.bytesPerActivate::512 2 1.69% 92.37% # Bytes accessed per row activation
167system.physmem.bytesPerActivate::576 2 1.69% 94.07% # Bytes accessed per row activation
168system.physmem.bytesPerActivate::704 1 0.85% 94.92% # Bytes accessed per row activation
169system.physmem.bytesPerActivate::768 1 0.85% 95.76% # Bytes accessed per row activation
170system.physmem.bytesPerActivate::832 1 0.85% 96.61% # Bytes accessed per row activation
171system.physmem.bytesPerActivate::1024 2 1.69% 98.31% # Bytes accessed per row activation
172system.physmem.bytesPerActivate::1920 1 0.85% 99.15% # Bytes accessed per row activation
173system.physmem.bytesPerActivate::2368 1 0.85% 100.00% # Bytes accessed per row activation
174system.physmem.bytesPerActivate::total 118 # Bytes accessed per row activation
175system.physmem.totQLat 2620250 # Total ticks spent queuing
176system.physmem.totMemAccLat 13667750 # Total ticks spent from burst creation until serviced by the DRAM
177system.physmem.totBusLat 2385000 # Total ticks spent in databus transfers
178system.physmem.totBankLat 8662500 # Total ticks spent accessing banks
179system.physmem.avgQLat 5493.19 # Average queueing delay per DRAM burst
180system.physmem.avgBankLat 18160.38 # Average bank access latency per DRAM burst
181system.physmem.avgBusLat 5000.00 # Average bus latency per DRAM burst
182system.physmem.avgMemAccLat 28653.56 # Average memory access latency per DRAM burst
183system.physmem.avgRdBW 1394.07 # Average DRAM read bandwidth in MiByte/s
184system.physmem.avgWrBW 0.00 # Average achieved write bandwidth in MiByte/s
185system.physmem.avgRdBWSys 1394.07 # Average system read bandwidth in MiByte/s
186system.physmem.avgWrBWSys 0.00 # Average system write bandwidth in MiByte/s
187system.physmem.peakBW 12800.00 # Theoretical peak bandwidth in MiByte/s
188system.physmem.busUtil 10.89 # Data bus utilization in percentage
189system.physmem.busUtilRead 10.89 # Data bus utilization in percentage for reads
190system.physmem.busUtilWrite 0.00 # Data bus utilization in percentage for writes
191system.physmem.avgRdQLen 0.62 # Average read queue length when enqueuing
192system.physmem.avgWrQLen 0.00 # Average write queue length when enqueuing
193system.physmem.readRowHits 359 # Number of row buffer hits during reads
194system.physmem.writeRowHits 0 # Number of row buffer hits during writes
195system.physmem.readRowHitRate 75.26 # Row buffer hit rate for reads
196system.physmem.writeRowHitRate nan # Row buffer hit rate for writes
197system.physmem.avgGap 45742.14 # Average gap between requests
198system.physmem.pageHitRate 75.26 # Row buffer hit rate, read and write combined
199system.physmem.prechargeAllPercent 0.05 # Percentage of time for which DRAM has all the banks in precharge state
200system.membus.throughput 1394068087 # Throughput (bytes/s)
201system.membus.trans_dist::ReadReq 426 # Transaction distribution
202system.membus.trans_dist::ReadResp 426 # Transaction distribution
203system.membus.trans_dist::ReadExReq 51 # Transaction distribution
204system.membus.trans_dist::ReadExResp 51 # Transaction distribution
205system.membus.pkt_count_system.cpu.l2cache.mem_side::system.physmem.port 954 # Packet count per connected master and slave (bytes)
206system.membus.pkt_count::total 954 # Packet count per connected master and slave (bytes)
207system.membus.tot_pkt_size_system.cpu.l2cache.mem_side::system.physmem.port 30528 # Cumulative packet size per connected master and slave (bytes)
208system.membus.tot_pkt_size::total 30528 # Cumulative packet size per connected master and slave (bytes)
209system.membus.data_through_bus 30528 # Total data (bytes)
210system.membus.snoop_data_through_bus 0 # Total snoop data (bytes)
211system.membus.reqLayer0.occupancy 605500 # Layer occupancy (ticks)
212system.membus.reqLayer0.utilization 2.8 # Layer utilization (%)
213system.membus.respLayer1.occupancy 4475250 # Layer occupancy (ticks)
214system.membus.respLayer1.utilization 20.4 # Layer utilization (%)
215system.cpu.branchPred.lookups 2174 # Number of BP lookups
216system.cpu.branchPred.condPredicted 1490 # Number of conditional branches predicted
217system.cpu.branchPred.condIncorrect 438 # Number of conditional branches incorrect
218system.cpu.branchPred.BTBLookups 1651 # Number of BTB lookups
219system.cpu.branchPred.BTBHits 492 # Number of BTB hits
220system.cpu.branchPred.BTBCorrect 0 # Number of correct BTB predictions (this stat may not work properly.
221system.cpu.branchPred.BTBHitPct 29.800121 # BTB Hit Percentage
222system.cpu.branchPred.usedRAS 261 # Number of times the RAS was used to get a target.
223system.cpu.branchPred.RASInCorrect 67 # Number of incorrect RAS predictions.
224system.cpu.dtb.read_hits 0 # DTB read hits
225system.cpu.dtb.read_misses 0 # DTB read misses
226system.cpu.dtb.read_accesses 0 # DTB read accesses
227system.cpu.dtb.write_hits 0 # DTB write hits
228system.cpu.dtb.write_misses 0 # DTB write misses
229system.cpu.dtb.write_accesses 0 # DTB write accesses

--- 5 unchanged lines hidden (view full) ---

235system.cpu.itb.read_accesses 0 # DTB read accesses
236system.cpu.itb.write_hits 0 # DTB write hits
237system.cpu.itb.write_misses 0 # DTB write misses
238system.cpu.itb.write_accesses 0 # DTB write accesses
239system.cpu.itb.hits 0 # DTB hits
240system.cpu.itb.misses 0 # DTB misses
241system.cpu.itb.accesses 0 # DTB accesses
242system.cpu.workload.num_syscalls 8 # Number of system calls
243system.cpu.numCycles 43798 # number of cpu cycles simulated
244system.cpu.numWorkItemsStarted 0 # number of work items this cpu started
245system.cpu.numWorkItemsCompleted 0 # number of work items this cpu completed
246system.cpu.fetch.icacheStallCycles 8822 # Number of cycles fetch is stalled on an Icache miss
247system.cpu.fetch.Insts 13183 # Number of instructions fetch has processed
248system.cpu.fetch.Branches 2174 # Number of branches that fetch encountered
249system.cpu.fetch.predictedBranches 753 # Number of branches that fetch has predicted taken
250system.cpu.fetch.Cycles 3213 # Number of cycles fetch has run and was not squashing or blocked
251system.cpu.fetch.SquashCycles 1374 # Number of cycles fetch has spent squashing
252system.cpu.fetch.BlockedCycles 1344 # Number of cycles fetch has spent blocked
253system.cpu.fetch.PendingTrapStallCycles 143 # Number of stall cycles due to pending traps
254system.cpu.fetch.CacheLines 1965 # Number of cache lines fetched
255system.cpu.fetch.IcacheSquashes 277 # Number of outstanding Icache misses that were squashed
256system.cpu.fetch.rateDist::samples 14432 # Number of instructions fetched each cycle (Total)
257system.cpu.fetch.rateDist::mean 0.913456 # Number of instructions fetched each cycle (Total)
258system.cpu.fetch.rateDist::stdev 2.225567 # Number of instructions fetched each cycle (Total)
259system.cpu.fetch.rateDist::underflows 0 0.00% 0.00% # Number of instructions fetched each cycle (Total)
260system.cpu.fetch.rateDist::0 11219 77.74% 77.74% # Number of instructions fetched each cycle (Total)
261system.cpu.fetch.rateDist::1 1317 9.13% 86.86% # Number of instructions fetched each cycle (Total)
262system.cpu.fetch.rateDist::2 104 0.72% 87.58% # Number of instructions fetched each cycle (Total)
263system.cpu.fetch.rateDist::3 131 0.91% 88.49% # Number of instructions fetched each cycle (Total)
264system.cpu.fetch.rateDist::4 305 2.11% 90.60% # Number of instructions fetched each cycle (Total)
265system.cpu.fetch.rateDist::5 115 0.80% 91.40% # Number of instructions fetched each cycle (Total)
266system.cpu.fetch.rateDist::6 150 1.04% 92.44% # Number of instructions fetched each cycle (Total)
267system.cpu.fetch.rateDist::7 158 1.09% 93.54% # Number of instructions fetched each cycle (Total)
268system.cpu.fetch.rateDist::8 933 6.46% 100.00% # Number of instructions fetched each cycle (Total)
269system.cpu.fetch.rateDist::overflows 0 0.00% 100.00% # Number of instructions fetched each cycle (Total)
270system.cpu.fetch.rateDist::min_value 0 # Number of instructions fetched each cycle (Total)
271system.cpu.fetch.rateDist::max_value 8 # Number of instructions fetched each cycle (Total)
272system.cpu.fetch.rateDist::total 14432 # Number of instructions fetched each cycle (Total)
273system.cpu.fetch.branchRate 0.049637 # Number of branch fetches per cycle
274system.cpu.fetch.rate 0.300995 # Number of inst fetches per cycle
275system.cpu.decode.IdleCycles 8889 # Number of cycles decode is idle
276system.cpu.decode.BlockedCycles 1596 # Number of cycles decode is blocked
277system.cpu.decode.RunCycles 3026 # Number of cycles decode is running
278system.cpu.decode.UnblockCycles 53 # Number of cycles decode is unblocking
279system.cpu.decode.SquashCycles 868 # Number of cycles decode is squashing
280system.cpu.decode.BranchResolved 157 # Number of times decode resolved a branch
281system.cpu.decode.BranchMispred 43 # Number of times decode detected a branch misprediction
282system.cpu.decode.DecodedInsts 12300 # Number of instructions handled by decode
283system.cpu.decode.SquashedInsts 174 # Number of squashed instructions handled by decode
284system.cpu.rename.SquashCycles 868 # Number of cycles rename is squashing
285system.cpu.rename.IdleCycles 9071 # Number of cycles rename is idle
286system.cpu.rename.BlockCycles 527 # Number of cycles rename is blocking
287system.cpu.rename.serializeStallCycles 919 # count of cycles rename stalled for serializing inst
288system.cpu.rename.RunCycles 2899 # Number of cycles rename is running
289system.cpu.rename.UnblockCycles 148 # Number of cycles rename is unblocking
290system.cpu.rename.RenamedInsts 11870 # Number of instructions processed by rename
291system.cpu.rename.ROBFullEvents 7 # Number of times rename has blocked due to ROB full
292system.cpu.rename.IQFullEvents 6 # Number of times rename has blocked due to IQ full
293system.cpu.rename.LSQFullEvents 124 # Number of times rename has blocked due to LSQ full
294system.cpu.rename.RenamedOperands 7180 # Number of destination operands rename has renamed
295system.cpu.rename.RenameLookups 14110 # Number of register rename lookups that rename has made
296system.cpu.rename.int_rename_lookups 13881 # Number of integer rename lookups
297system.cpu.rename.fp_rename_lookups 3 # Number of floating rename lookups
298system.cpu.rename.CommittedMaps 3398 # Number of HB maps that are committed
299system.cpu.rename.UndoneMaps 3782 # Number of HB maps that are undone due to squashing
300system.cpu.rename.serializingInsts 16 # count of serializing insts renamed
301system.cpu.rename.tempSerializingInsts 10 # count of temporary serializing insts renamed
302system.cpu.rename.skidInsts 328 # count of insts added to the skid buffer
303system.cpu.memDep0.insertedLoads 2457 # Number of loads inserted to the mem dependence unit.
304system.cpu.memDep0.insertedStores 1193 # Number of stores inserted to the mem dependence unit.
305system.cpu.memDep0.conflictingLoads 1 # Number of conflicting loads.
306system.cpu.memDep0.conflictingStores 1 # Number of conflicting stores.
307system.cpu.iq.iqInstsAdded 9210 # Number of instructions added to the IQ (excludes non-spec)
308system.cpu.iq.iqNonSpecInstsAdded 12 # Number of non-speculative instructions added to the IQ
309system.cpu.iq.iqInstsIssued 8293 # Number of instructions issued
310system.cpu.iq.iqSquashedInstsIssued 39 # Number of squashed instructions issued
311system.cpu.iq.iqSquashedInstsExamined 3412 # Number of squashed instructions iterated over during squash; mainly for profiling
312system.cpu.iq.iqSquashedOperandsExamined 2076 # Number of squashed operands that are examined and possibly removed from graph
313system.cpu.iq.iqSquashedNonSpecRemoved 2 # Number of squashed non-spec instructions that were removed
314system.cpu.iq.issued_per_cycle::samples 14432 # Number of insts issued each cycle
315system.cpu.iq.issued_per_cycle::mean 0.574626 # Number of insts issued each cycle
316system.cpu.iq.issued_per_cycle::stdev 1.242806 # Number of insts issued each cycle
317system.cpu.iq.issued_per_cycle::underflows 0 0.00% 0.00% # Number of insts issued each cycle
318system.cpu.iq.issued_per_cycle::0 10849 75.17% 75.17% # Number of insts issued each cycle
319system.cpu.iq.issued_per_cycle::1 1422 9.85% 85.03% # Number of insts issued each cycle
320system.cpu.iq.issued_per_cycle::2 891 6.17% 91.20% # Number of insts issued each cycle
321system.cpu.iq.issued_per_cycle::3 553 3.83% 95.03% # Number of insts issued each cycle
322system.cpu.iq.issued_per_cycle::4 355 2.46% 97.49% # Number of insts issued each cycle
323system.cpu.iq.issued_per_cycle::5 226 1.57% 99.06% # Number of insts issued each cycle
324system.cpu.iq.issued_per_cycle::6 89 0.62% 99.67% # Number of insts issued each cycle
325system.cpu.iq.issued_per_cycle::7 30 0.21% 99.88% # Number of insts issued each cycle
326system.cpu.iq.issued_per_cycle::8 17 0.12% 100.00% # Number of insts issued each cycle
327system.cpu.iq.issued_per_cycle::overflows 0 0.00% 100.00% # Number of insts issued each cycle
328system.cpu.iq.issued_per_cycle::min_value 0 # Number of insts issued each cycle
329system.cpu.iq.issued_per_cycle::max_value 8 # Number of insts issued each cycle
330system.cpu.iq.issued_per_cycle::total 14432 # Number of insts issued each cycle
331system.cpu.iq.fu_full::No_OpClass 0 0.00% 0.00% # attempts to use FU when none available
332system.cpu.iq.fu_full::IntAlu 5 3.12% 3.12% # attempts to use FU when none available
333system.cpu.iq.fu_full::IntMult 0 0.00% 3.12% # attempts to use FU when none available
334system.cpu.iq.fu_full::IntDiv 0 0.00% 3.12% # attempts to use FU when none available
335system.cpu.iq.fu_full::FloatAdd 0 0.00% 3.12% # attempts to use FU when none available
336system.cpu.iq.fu_full::FloatCmp 0 0.00% 3.12% # attempts to use FU when none available
337system.cpu.iq.fu_full::FloatCvt 0 0.00% 3.12% # attempts to use FU when none available
338system.cpu.iq.fu_full::FloatMult 0 0.00% 3.12% # attempts to use FU when none available

--- 19 unchanged lines hidden (view full) ---

358system.cpu.iq.fu_full::SimdFloatMult 0 0.00% 3.12% # attempts to use FU when none available
359system.cpu.iq.fu_full::SimdFloatMultAcc 0 0.00% 3.12% # attempts to use FU when none available
360system.cpu.iq.fu_full::SimdFloatSqrt 0 0.00% 3.12% # attempts to use FU when none available
361system.cpu.iq.fu_full::MemRead 101 63.12% 66.25% # attempts to use FU when none available
362system.cpu.iq.fu_full::MemWrite 54 33.75% 100.00% # attempts to use FU when none available
363system.cpu.iq.fu_full::IprAccess 0 0.00% 100.00% # attempts to use FU when none available
364system.cpu.iq.fu_full::InstPrefetch 0 0.00% 100.00% # attempts to use FU when none available
365system.cpu.iq.FU_type_0::No_OpClass 0 0.00% 0.00% # Type of FU issued
366system.cpu.iq.FU_type_0::IntAlu 4933 59.48% 59.48% # Type of FU issued
367system.cpu.iq.FU_type_0::IntMult 5 0.06% 59.54% # Type of FU issued
368system.cpu.iq.FU_type_0::IntDiv 2 0.02% 59.57% # Type of FU issued
369system.cpu.iq.FU_type_0::FloatAdd 2 0.02% 59.59% # Type of FU issued
370system.cpu.iq.FU_type_0::FloatCmp 0 0.00% 59.59% # Type of FU issued
371system.cpu.iq.FU_type_0::FloatCvt 0 0.00% 59.59% # Type of FU issued
372system.cpu.iq.FU_type_0::FloatMult 0 0.00% 59.59% # Type of FU issued
373system.cpu.iq.FU_type_0::FloatDiv 0 0.00% 59.59% # Type of FU issued
374system.cpu.iq.FU_type_0::FloatSqrt 0 0.00% 59.59% # Type of FU issued
375system.cpu.iq.FU_type_0::SimdAdd 0 0.00% 59.59% # Type of FU issued
376system.cpu.iq.FU_type_0::SimdAddAcc 0 0.00% 59.59% # Type of FU issued
377system.cpu.iq.FU_type_0::SimdAlu 0 0.00% 59.59% # Type of FU issued
378system.cpu.iq.FU_type_0::SimdCmp 0 0.00% 59.59% # Type of FU issued
379system.cpu.iq.FU_type_0::SimdCvt 0 0.00% 59.59% # Type of FU issued
380system.cpu.iq.FU_type_0::SimdMisc 0 0.00% 59.59% # Type of FU issued
381system.cpu.iq.FU_type_0::SimdMult 0 0.00% 59.59% # Type of FU issued
382system.cpu.iq.FU_type_0::SimdMultAcc 0 0.00% 59.59% # Type of FU issued
383system.cpu.iq.FU_type_0::SimdShift 0 0.00% 59.59% # Type of FU issued
384system.cpu.iq.FU_type_0::SimdShiftAcc 0 0.00% 59.59% # Type of FU issued
385system.cpu.iq.FU_type_0::SimdSqrt 0 0.00% 59.59% # Type of FU issued
386system.cpu.iq.FU_type_0::SimdFloatAdd 0 0.00% 59.59% # Type of FU issued
387system.cpu.iq.FU_type_0::SimdFloatAlu 0 0.00% 59.59% # Type of FU issued
388system.cpu.iq.FU_type_0::SimdFloatCmp 0 0.00% 59.59% # Type of FU issued
389system.cpu.iq.FU_type_0::SimdFloatCvt 0 0.00% 59.59% # Type of FU issued
390system.cpu.iq.FU_type_0::SimdFloatDiv 0 0.00% 59.59% # Type of FU issued
391system.cpu.iq.FU_type_0::SimdFloatMisc 0 0.00% 59.59% # Type of FU issued
392system.cpu.iq.FU_type_0::SimdFloatMult 0 0.00% 59.59% # Type of FU issued
393system.cpu.iq.FU_type_0::SimdFloatMultAcc 0 0.00% 59.59% # Type of FU issued
394system.cpu.iq.FU_type_0::SimdFloatSqrt 0 0.00% 59.59% # Type of FU issued
395system.cpu.iq.FU_type_0::MemRead 2247 27.10% 86.69% # Type of FU issued
396system.cpu.iq.FU_type_0::MemWrite 1104 13.31% 100.00% # Type of FU issued
397system.cpu.iq.FU_type_0::IprAccess 0 0.00% 100.00% # Type of FU issued
398system.cpu.iq.FU_type_0::InstPrefetch 0 0.00% 100.00% # Type of FU issued
399system.cpu.iq.FU_type_0::total 8293 # Type of FU issued
400system.cpu.iq.rate 0.189347 # Inst issue rate
401system.cpu.iq.fu_busy_cnt 160 # FU busy when requested
402system.cpu.iq.fu_busy_rate 0.019293 # FU busy rate (busy events/executed inst)
403system.cpu.iq.int_inst_queue_reads 31213 # Number of integer instruction queue reads
404system.cpu.iq.int_inst_queue_writes 12643 # Number of integer instruction queue writes
405system.cpu.iq.int_inst_queue_wakeup_accesses 7453 # Number of integer instruction queue wakeup accesses
406system.cpu.iq.fp_inst_queue_reads 4 # Number of floating instruction queue reads
407system.cpu.iq.fp_inst_queue_writes 2 # Number of floating instruction queue writes
408system.cpu.iq.fp_inst_queue_wakeup_accesses 2 # Number of floating instruction queue wakeup accesses
409system.cpu.iq.int_alu_accesses 8451 # Number of integer alu accesses
410system.cpu.iq.fp_alu_accesses 2 # Number of floating point alu accesses
411system.cpu.iew.lsq.thread0.forwLoads 69 # Number of loads that had data forwarded from stores
412system.cpu.iew.lsq.thread0.invAddrLoads 0 # Number of loads ignored due to an invalid address
413system.cpu.iew.lsq.thread0.squashedLoads 1294 # Number of loads squashed
414system.cpu.iew.lsq.thread0.ignoredResponses 5 # Number of memory responses ignored because the instruction is squashed
415system.cpu.iew.lsq.thread0.memOrderViolation 12 # Number of memory ordering violations
416system.cpu.iew.lsq.thread0.squashedStores 268 # Number of stores squashed
417system.cpu.iew.lsq.thread0.invAddrSwpfs 0 # Number of software prefetches ignored due to an invalid address
418system.cpu.iew.lsq.thread0.blockedLoads 0 # Number of blocked loads due to partial load-store forwarding
419system.cpu.iew.lsq.thread0.rescheduledLoads 0 # Number of loads that were rescheduled
420system.cpu.iew.lsq.thread0.cacheBlocked 32 # Number of times an access to memory failed due to the cache being blocked
421system.cpu.iew.iewIdleCycles 0 # Number of cycles IEW is idle
422system.cpu.iew.iewSquashCycles 868 # Number of cycles IEW is squashing
423system.cpu.iew.iewBlockCycles 349 # Number of cycles IEW is blocking
424system.cpu.iew.iewUnblockCycles 16 # Number of cycles IEW is unblocking
425system.cpu.iew.iewDispatchedInsts 10734 # Number of instructions dispatched to IQ
426system.cpu.iew.iewDispSquashedInsts 93 # Number of squashed instructions skipped by dispatch
427system.cpu.iew.iewDispLoadInsts 2457 # Number of dispatched load instructions
428system.cpu.iew.iewDispStoreInsts 1193 # Number of dispatched store instructions
429system.cpu.iew.iewDispNonSpecInsts 12 # Number of dispatched non-speculative instructions
430system.cpu.iew.iewIQFullEvents 1 # Number of times the IQ has become full, causing a stall
431system.cpu.iew.iewLSQFullEvents 0 # Number of times the LSQ has become full, causing a stall
432system.cpu.iew.memOrderViolationEvents 12 # Number of memory order violations
433system.cpu.iew.predictedTakenIncorrect 101 # Number of branches that were predicted taken incorrectly
434system.cpu.iew.predictedNotTakenIncorrect 362 # Number of branches that were predicted not taken incorrectly
435system.cpu.iew.branchMispredicts 463 # Number of branch mispredicts detected at execute
436system.cpu.iew.iewExecutedInsts 7912 # Number of executed instructions
437system.cpu.iew.iewExecLoadInsts 2107 # Number of load instructions executed
438system.cpu.iew.iewExecSquashedInsts 381 # Number of squashed instructions skipped in execute
439system.cpu.iew.exec_swp 0 # number of swp insts executed
440system.cpu.iew.exec_nop 1512 # number of nop insts executed
441system.cpu.iew.exec_refs 3186 # number of memory reference insts executed
442system.cpu.iew.exec_branches 1344 # Number of branches executed
443system.cpu.iew.exec_stores 1079 # Number of stores executed
444system.cpu.iew.exec_rate 0.180648 # Inst execution rate
445system.cpu.iew.wb_sent 7546 # cumulative count of insts sent to commit
446system.cpu.iew.wb_count 7455 # cumulative count of insts written-back
447system.cpu.iew.wb_producers 2921 # num instructions producing a value
448system.cpu.iew.wb_consumers 4197 # num instructions consuming a value
449system.cpu.iew.wb_penalized 0 # number of instrctions required to write to 'other' IQ
450system.cpu.iew.wb_rate 0.170213 # insts written-back per cycle
451system.cpu.iew.wb_fanout 0.695973 # average fanout of values written-back
452system.cpu.iew.wb_penalized_rate 0 # fraction of instructions written-back that wrote to 'other' IQ
453system.cpu.commit.commitSquashedInsts 4914 # The number of squashed insts skipped by commit
454system.cpu.commit.commitNonSpecStalls 10 # The number of times commit has been forced to stall to communicate backwards
455system.cpu.commit.branchMispredicts 396 # The number of times a branch was mispredicted
456system.cpu.commit.committed_per_cycle::samples 13564 # Number of insts commited each cycle
457system.cpu.commit.committed_per_cycle::mean 0.428561 # Number of insts commited each cycle
458system.cpu.commit.committed_per_cycle::stdev 1.209396 # Number of insts commited each cycle
459system.cpu.commit.committed_per_cycle::underflows 0 0.00% 0.00% # Number of insts commited each cycle
460system.cpu.commit.committed_per_cycle::0 11162 82.29% 82.29% # Number of insts commited each cycle
461system.cpu.commit.committed_per_cycle::1 999 7.37% 89.66% # Number of insts commited each cycle
462system.cpu.commit.committed_per_cycle::2 630 4.64% 94.30% # Number of insts commited each cycle
463system.cpu.commit.committed_per_cycle::3 315 2.32% 96.62% # Number of insts commited each cycle
464system.cpu.commit.committed_per_cycle::4 149 1.10% 97.72% # Number of insts commited each cycle
465system.cpu.commit.committed_per_cycle::5 94 0.69% 98.41% # Number of insts commited each cycle
466system.cpu.commit.committed_per_cycle::6 68 0.50% 98.92% # Number of insts commited each cycle
467system.cpu.commit.committed_per_cycle::7 41 0.30% 99.22% # Number of insts commited each cycle
468system.cpu.commit.committed_per_cycle::8 106 0.78% 100.00% # Number of insts commited each cycle
469system.cpu.commit.committed_per_cycle::overflows 0 0.00% 100.00% # Number of insts commited each cycle
470system.cpu.commit.committed_per_cycle::min_value 0 # Number of insts commited each cycle
471system.cpu.commit.committed_per_cycle::max_value 8 # Number of insts commited each cycle
472system.cpu.commit.committed_per_cycle::total 13564 # Number of insts commited each cycle
473system.cpu.commit.committedInsts 5813 # Number of instructions committed
474system.cpu.commit.committedOps 5813 # Number of ops (including micro ops) committed
475system.cpu.commit.swp_count 0 # Number of s/w prefetches committed
476system.cpu.commit.refs 2088 # Number of memory references committed
477system.cpu.commit.loads 1163 # Number of loads committed
478system.cpu.commit.membars 0 # Number of memory barriers committed
479system.cpu.commit.branches 915 # Number of branches committed
480system.cpu.commit.fp_insts 2 # Number of committed floating point instructions.
481system.cpu.commit.int_insts 5111 # Number of committed integer instructions.
482system.cpu.commit.function_calls 87 # Number of function calls committed.
483system.cpu.commit.bw_lim_events 106 # number cycles where commit BW limit reached
484system.cpu.commit.bw_limited 0 # number of insts not committed due to BW limits
485system.cpu.rob.rob_reads 24172 # The number of ROB reads
486system.cpu.rob.rob_writes 22333 # The number of ROB writes
487system.cpu.timesIdled 285 # Number of times that the entire CPU went into an idle state and unscheduled itself
488system.cpu.idleCycles 29366 # Total number of cycles that the CPU has spent unscheduled due to idling
489system.cpu.committedInsts 5156 # Number of Instructions Simulated
490system.cpu.committedOps 5156 # Number of Ops (including micro ops) Simulated
491system.cpu.committedInsts_total 5156 # Number of Instructions Simulated
492system.cpu.cpi 8.494569 # CPI: Cycles Per Instruction
493system.cpu.cpi_total 8.494569 # CPI: Total CPI of All Threads
494system.cpu.ipc 0.117722 # IPC: Instructions Per Cycle
495system.cpu.ipc_total 0.117722 # IPC: Total IPC of All Threads
496system.cpu.int_regfile_reads 10743 # number of integer regfile reads
497system.cpu.int_regfile_writes 5234 # number of integer regfile writes
498system.cpu.fp_regfile_reads 3 # number of floating regfile reads
499system.cpu.fp_regfile_writes 1 # number of floating regfile writes
500system.cpu.misc_regfile_reads 148 # number of misc regfile reads
501system.cpu.toL2Bus.throughput 1402835811 # Throughput (bytes/s)
502system.cpu.toL2Bus.trans_dist::ReadReq 429 # Transaction distribution
503system.cpu.toL2Bus.trans_dist::ReadResp 429 # Transaction distribution
504system.cpu.toL2Bus.trans_dist::ReadExReq 51 # Transaction distribution
505system.cpu.toL2Bus.trans_dist::ReadExResp 51 # Transaction distribution
506system.cpu.toL2Bus.pkt_count_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 676 # Packet count per connected master and slave (bytes)
507system.cpu.toL2Bus.pkt_count_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 284 # Packet count per connected master and slave (bytes)
508system.cpu.toL2Bus.pkt_count::total 960 # Packet count per connected master and slave (bytes)
509system.cpu.toL2Bus.tot_pkt_size_system.cpu.icache.mem_side::system.cpu.l2cache.cpu_side 21632 # Cumulative packet size per connected master and slave (bytes)
510system.cpu.toL2Bus.tot_pkt_size_system.cpu.dcache.mem_side::system.cpu.l2cache.cpu_side 9088 # Cumulative packet size per connected master and slave (bytes)
511system.cpu.toL2Bus.tot_pkt_size::total 30720 # Cumulative packet size per connected master and slave (bytes)
512system.cpu.toL2Bus.data_through_bus 30720 # Total data (bytes)
513system.cpu.toL2Bus.snoop_data_through_bus 0 # Total snoop data (bytes)
514system.cpu.toL2Bus.reqLayer0.occupancy 240000 # Layer occupancy (ticks)
515system.cpu.toL2Bus.reqLayer0.utilization 1.1 # Layer utilization (%)
516system.cpu.toL2Bus.respLayer0.occupancy 570750 # Layer occupancy (ticks)
517system.cpu.toL2Bus.respLayer0.utilization 2.6 # Layer utilization (%)
518system.cpu.toL2Bus.respLayer1.occupancy 227500 # Layer occupancy (ticks)
519system.cpu.toL2Bus.respLayer1.utilization 1.0 # Layer utilization (%)
520system.cpu.icache.tags.replacements 17 # number of replacements
521system.cpu.icache.tags.tagsinuse 161.632436 # Cycle average of tags in use
522system.cpu.icache.tags.total_refs 1514 # Total number of references to valid blocks.
523system.cpu.icache.tags.sampled_refs 338 # Sample count of references to valid blocks.
524system.cpu.icache.tags.avg_refs 4.479290 # Average number of references to valid blocks.
525system.cpu.icache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
526system.cpu.icache.tags.occ_blocks::cpu.inst 161.632436 # Average occupied blocks per requestor
527system.cpu.icache.tags.occ_percent::cpu.inst 0.078922 # Average percentage of cache occupancy
528system.cpu.icache.tags.occ_percent::total 0.078922 # Average percentage of cache occupancy
529system.cpu.icache.ReadReq_hits::cpu.inst 1514 # number of ReadReq hits
530system.cpu.icache.ReadReq_hits::total 1514 # number of ReadReq hits
531system.cpu.icache.demand_hits::cpu.inst 1514 # number of demand (read+write) hits
532system.cpu.icache.demand_hits::total 1514 # number of demand (read+write) hits
533system.cpu.icache.overall_hits::cpu.inst 1514 # number of overall hits
534system.cpu.icache.overall_hits::total 1514 # number of overall hits
535system.cpu.icache.ReadReq_misses::cpu.inst 451 # number of ReadReq misses
536system.cpu.icache.ReadReq_misses::total 451 # number of ReadReq misses
537system.cpu.icache.demand_misses::cpu.inst 451 # number of demand (read+write) misses
538system.cpu.icache.demand_misses::total 451 # number of demand (read+write) misses
539system.cpu.icache.overall_misses::cpu.inst 451 # number of overall misses
540system.cpu.icache.overall_misses::total 451 # number of overall misses
541system.cpu.icache.ReadReq_miss_latency::cpu.inst 31197000 # number of ReadReq miss cycles
542system.cpu.icache.ReadReq_miss_latency::total 31197000 # number of ReadReq miss cycles
543system.cpu.icache.demand_miss_latency::cpu.inst 31197000 # number of demand (read+write) miss cycles
544system.cpu.icache.demand_miss_latency::total 31197000 # number of demand (read+write) miss cycles
545system.cpu.icache.overall_miss_latency::cpu.inst 31197000 # number of overall miss cycles
546system.cpu.icache.overall_miss_latency::total 31197000 # number of overall miss cycles
547system.cpu.icache.ReadReq_accesses::cpu.inst 1965 # number of ReadReq accesses(hits+misses)
548system.cpu.icache.ReadReq_accesses::total 1965 # number of ReadReq accesses(hits+misses)
549system.cpu.icache.demand_accesses::cpu.inst 1965 # number of demand (read+write) accesses
550system.cpu.icache.demand_accesses::total 1965 # number of demand (read+write) accesses
551system.cpu.icache.overall_accesses::cpu.inst 1965 # number of overall (read+write) accesses
552system.cpu.icache.overall_accesses::total 1965 # number of overall (read+write) accesses
553system.cpu.icache.ReadReq_miss_rate::cpu.inst 0.229517 # miss rate for ReadReq accesses
554system.cpu.icache.ReadReq_miss_rate::total 0.229517 # miss rate for ReadReq accesses
555system.cpu.icache.demand_miss_rate::cpu.inst 0.229517 # miss rate for demand accesses
556system.cpu.icache.demand_miss_rate::total 0.229517 # miss rate for demand accesses
557system.cpu.icache.overall_miss_rate::cpu.inst 0.229517 # miss rate for overall accesses
558system.cpu.icache.overall_miss_rate::total 0.229517 # miss rate for overall accesses
559system.cpu.icache.ReadReq_avg_miss_latency::cpu.inst 69172.949002 # average ReadReq miss latency
560system.cpu.icache.ReadReq_avg_miss_latency::total 69172.949002 # average ReadReq miss latency
561system.cpu.icache.demand_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
562system.cpu.icache.demand_avg_miss_latency::total 69172.949002 # average overall miss latency
563system.cpu.icache.overall_avg_miss_latency::cpu.inst 69172.949002 # average overall miss latency
564system.cpu.icache.overall_avg_miss_latency::total 69172.949002 # average overall miss latency
565system.cpu.icache.blocked_cycles::no_mshrs 47 # number of cycles access was blocked
566system.cpu.icache.blocked_cycles::no_targets 0 # number of cycles access was blocked
567system.cpu.icache.blocked::no_mshrs 1 # number of cycles access was blocked
568system.cpu.icache.blocked::no_targets 0 # number of cycles access was blocked
569system.cpu.icache.avg_blocked_cycles::no_mshrs 47 # average number of cycles each access was blocked
570system.cpu.icache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
571system.cpu.icache.fast_writes 0 # number of fast writes performed
572system.cpu.icache.cache_copies 0 # number of cache copies performed
573system.cpu.icache.ReadReq_mshr_hits::cpu.inst 113 # number of ReadReq MSHR hits
574system.cpu.icache.ReadReq_mshr_hits::total 113 # number of ReadReq MSHR hits
575system.cpu.icache.demand_mshr_hits::cpu.inst 113 # number of demand (read+write) MSHR hits
576system.cpu.icache.demand_mshr_hits::total 113 # number of demand (read+write) MSHR hits
577system.cpu.icache.overall_mshr_hits::cpu.inst 113 # number of overall MSHR hits
578system.cpu.icache.overall_mshr_hits::total 113 # number of overall MSHR hits
579system.cpu.icache.ReadReq_mshr_misses::cpu.inst 338 # number of ReadReq MSHR misses
580system.cpu.icache.ReadReq_mshr_misses::total 338 # number of ReadReq MSHR misses
581system.cpu.icache.demand_mshr_misses::cpu.inst 338 # number of demand (read+write) MSHR misses
582system.cpu.icache.demand_mshr_misses::total 338 # number of demand (read+write) MSHR misses
583system.cpu.icache.overall_mshr_misses::cpu.inst 338 # number of overall MSHR misses
584system.cpu.icache.overall_mshr_misses::total 338 # number of overall MSHR misses
585system.cpu.icache.ReadReq_mshr_miss_latency::cpu.inst 24202250 # number of ReadReq MSHR miss cycles
586system.cpu.icache.ReadReq_mshr_miss_latency::total 24202250 # number of ReadReq MSHR miss cycles
587system.cpu.icache.demand_mshr_miss_latency::cpu.inst 24202250 # number of demand (read+write) MSHR miss cycles
588system.cpu.icache.demand_mshr_miss_latency::total 24202250 # number of demand (read+write) MSHR miss cycles
589system.cpu.icache.overall_mshr_miss_latency::cpu.inst 24202250 # number of overall MSHR miss cycles
590system.cpu.icache.overall_mshr_miss_latency::total 24202250 # number of overall MSHR miss cycles
591system.cpu.icache.ReadReq_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for ReadReq accesses
592system.cpu.icache.ReadReq_mshr_miss_rate::total 0.172010 # mshr miss rate for ReadReq accesses
593system.cpu.icache.demand_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for demand accesses
594system.cpu.icache.demand_mshr_miss_rate::total 0.172010 # mshr miss rate for demand accesses
595system.cpu.icache.overall_mshr_miss_rate::cpu.inst 0.172010 # mshr miss rate for overall accesses
596system.cpu.icache.overall_mshr_miss_rate::total 0.172010 # mshr miss rate for overall accesses
597system.cpu.icache.ReadReq_avg_mshr_miss_latency::cpu.inst 71604.289941 # average ReadReq mshr miss latency
598system.cpu.icache.ReadReq_avg_mshr_miss_latency::total 71604.289941 # average ReadReq mshr miss latency
599system.cpu.icache.demand_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
600system.cpu.icache.demand_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
601system.cpu.icache.overall_avg_mshr_miss_latency::cpu.inst 71604.289941 # average overall mshr miss latency
602system.cpu.icache.overall_avg_mshr_miss_latency::total 71604.289941 # average overall mshr miss latency
603system.cpu.icache.no_allocate_misses 0 # Number of misses that were no-allocate
604system.cpu.l2cache.tags.replacements 0 # number of replacements
605system.cpu.l2cache.tags.tagsinuse 221.801046 # Cycle average of tags in use
606system.cpu.l2cache.tags.total_refs 3 # Total number of references to valid blocks.
607system.cpu.l2cache.tags.sampled_refs 426 # Sample count of references to valid blocks.
608system.cpu.l2cache.tags.avg_refs 0.007042 # Average number of references to valid blocks.
609system.cpu.l2cache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
610system.cpu.l2cache.tags.occ_blocks::cpu.inst 163.923758 # Average occupied blocks per requestor
611system.cpu.l2cache.tags.occ_blocks::cpu.data 57.877288 # Average occupied blocks per requestor
612system.cpu.l2cache.tags.occ_percent::cpu.inst 0.005003 # Average percentage of cache occupancy
613system.cpu.l2cache.tags.occ_percent::cpu.data 0.001766 # Average percentage of cache occupancy
614system.cpu.l2cache.tags.occ_percent::total 0.006769 # Average percentage of cache occupancy
615system.cpu.l2cache.ReadReq_hits::cpu.inst 3 # number of ReadReq hits
616system.cpu.l2cache.ReadReq_hits::total 3 # number of ReadReq hits
617system.cpu.l2cache.demand_hits::cpu.inst 3 # number of demand (read+write) hits
618system.cpu.l2cache.demand_hits::total 3 # number of demand (read+write) hits
619system.cpu.l2cache.overall_hits::cpu.inst 3 # number of overall hits
620system.cpu.l2cache.overall_hits::total 3 # number of overall hits
621system.cpu.l2cache.ReadReq_misses::cpu.inst 335 # number of ReadReq misses
622system.cpu.l2cache.ReadReq_misses::cpu.data 91 # number of ReadReq misses
623system.cpu.l2cache.ReadReq_misses::total 426 # number of ReadReq misses
624system.cpu.l2cache.ReadExReq_misses::cpu.data 51 # number of ReadExReq misses
625system.cpu.l2cache.ReadExReq_misses::total 51 # number of ReadExReq misses
626system.cpu.l2cache.demand_misses::cpu.inst 335 # number of demand (read+write) misses
627system.cpu.l2cache.demand_misses::cpu.data 142 # number of demand (read+write) misses
628system.cpu.l2cache.demand_misses::total 477 # number of demand (read+write) misses
629system.cpu.l2cache.overall_misses::cpu.inst 335 # number of overall misses
630system.cpu.l2cache.overall_misses::cpu.data 142 # number of overall misses
631system.cpu.l2cache.overall_misses::total 477 # number of overall misses
632system.cpu.l2cache.ReadReq_miss_latency::cpu.inst 23834250 # number of ReadReq miss cycles
633system.cpu.l2cache.ReadReq_miss_latency::cpu.data 7026750 # number of ReadReq miss cycles
634system.cpu.l2cache.ReadReq_miss_latency::total 30861000 # number of ReadReq miss cycles
635system.cpu.l2cache.ReadExReq_miss_latency::cpu.data 3814250 # number of ReadExReq miss cycles
636system.cpu.l2cache.ReadExReq_miss_latency::total 3814250 # number of ReadExReq miss cycles
637system.cpu.l2cache.demand_miss_latency::cpu.inst 23834250 # number of demand (read+write) miss cycles
638system.cpu.l2cache.demand_miss_latency::cpu.data 10841000 # number of demand (read+write) miss cycles
639system.cpu.l2cache.demand_miss_latency::total 34675250 # number of demand (read+write) miss cycles
640system.cpu.l2cache.overall_miss_latency::cpu.inst 23834250 # number of overall miss cycles
641system.cpu.l2cache.overall_miss_latency::cpu.data 10841000 # number of overall miss cycles
642system.cpu.l2cache.overall_miss_latency::total 34675250 # number of overall miss cycles
643system.cpu.l2cache.ReadReq_accesses::cpu.inst 338 # number of ReadReq accesses(hits+misses)
644system.cpu.l2cache.ReadReq_accesses::cpu.data 91 # number of ReadReq accesses(hits+misses)
645system.cpu.l2cache.ReadReq_accesses::total 429 # number of ReadReq accesses(hits+misses)
646system.cpu.l2cache.ReadExReq_accesses::cpu.data 51 # number of ReadExReq accesses(hits+misses)
647system.cpu.l2cache.ReadExReq_accesses::total 51 # number of ReadExReq accesses(hits+misses)
648system.cpu.l2cache.demand_accesses::cpu.inst 338 # number of demand (read+write) accesses
649system.cpu.l2cache.demand_accesses::cpu.data 142 # number of demand (read+write) accesses
650system.cpu.l2cache.demand_accesses::total 480 # number of demand (read+write) accesses

--- 6 unchanged lines hidden (view full) ---

657system.cpu.l2cache.ReadExReq_miss_rate::cpu.data 1 # miss rate for ReadExReq accesses
658system.cpu.l2cache.ReadExReq_miss_rate::total 1 # miss rate for ReadExReq accesses
659system.cpu.l2cache.demand_miss_rate::cpu.inst 0.991124 # miss rate for demand accesses
660system.cpu.l2cache.demand_miss_rate::cpu.data 1 # miss rate for demand accesses
661system.cpu.l2cache.demand_miss_rate::total 0.993750 # miss rate for demand accesses
662system.cpu.l2cache.overall_miss_rate::cpu.inst 0.991124 # miss rate for overall accesses
663system.cpu.l2cache.overall_miss_rate::cpu.data 1 # miss rate for overall accesses
664system.cpu.l2cache.overall_miss_rate::total 0.993750 # miss rate for overall accesses
665system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.inst 71147.014925 # average ReadReq miss latency
666system.cpu.l2cache.ReadReq_avg_miss_latency::cpu.data 77217.032967 # average ReadReq miss latency
667system.cpu.l2cache.ReadReq_avg_miss_latency::total 72443.661972 # average ReadReq miss latency
668system.cpu.l2cache.ReadExReq_avg_miss_latency::cpu.data 74789.215686 # average ReadExReq miss latency
669system.cpu.l2cache.ReadExReq_avg_miss_latency::total 74789.215686 # average ReadExReq miss latency
670system.cpu.l2cache.demand_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
671system.cpu.l2cache.demand_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
672system.cpu.l2cache.demand_avg_miss_latency::total 72694.444444 # average overall miss latency
673system.cpu.l2cache.overall_avg_miss_latency::cpu.inst 71147.014925 # average overall miss latency
674system.cpu.l2cache.overall_avg_miss_latency::cpu.data 76345.070423 # average overall miss latency
675system.cpu.l2cache.overall_avg_miss_latency::total 72694.444444 # average overall miss latency
676system.cpu.l2cache.blocked_cycles::no_mshrs 0 # number of cycles access was blocked
677system.cpu.l2cache.blocked_cycles::no_targets 0 # number of cycles access was blocked
678system.cpu.l2cache.blocked::no_mshrs 0 # number of cycles access was blocked
679system.cpu.l2cache.blocked::no_targets 0 # number of cycles access was blocked
680system.cpu.l2cache.avg_blocked_cycles::no_mshrs nan # average number of cycles each access was blocked
681system.cpu.l2cache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
682system.cpu.l2cache.fast_writes 0 # number of fast writes performed
683system.cpu.l2cache.cache_copies 0 # number of cache copies performed
684system.cpu.l2cache.ReadReq_mshr_misses::cpu.inst 335 # number of ReadReq MSHR misses
685system.cpu.l2cache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
686system.cpu.l2cache.ReadReq_mshr_misses::total 426 # number of ReadReq MSHR misses
687system.cpu.l2cache.ReadExReq_mshr_misses::cpu.data 51 # number of ReadExReq MSHR misses
688system.cpu.l2cache.ReadExReq_mshr_misses::total 51 # number of ReadExReq MSHR misses
689system.cpu.l2cache.demand_mshr_misses::cpu.inst 335 # number of demand (read+write) MSHR misses
690system.cpu.l2cache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
691system.cpu.l2cache.demand_mshr_misses::total 477 # number of demand (read+write) MSHR misses
692system.cpu.l2cache.overall_mshr_misses::cpu.inst 335 # number of overall MSHR misses
693system.cpu.l2cache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
694system.cpu.l2cache.overall_mshr_misses::total 477 # number of overall MSHR misses
695system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.inst 19597750 # number of ReadReq MSHR miss cycles
696system.cpu.l2cache.ReadReq_mshr_miss_latency::cpu.data 5909750 # number of ReadReq MSHR miss cycles
697system.cpu.l2cache.ReadReq_mshr_miss_latency::total 25507500 # number of ReadReq MSHR miss cycles
698system.cpu.l2cache.ReadExReq_mshr_miss_latency::cpu.data 3183250 # number of ReadExReq MSHR miss cycles
699system.cpu.l2cache.ReadExReq_mshr_miss_latency::total 3183250 # number of ReadExReq MSHR miss cycles
700system.cpu.l2cache.demand_mshr_miss_latency::cpu.inst 19597750 # number of demand (read+write) MSHR miss cycles
701system.cpu.l2cache.demand_mshr_miss_latency::cpu.data 9093000 # number of demand (read+write) MSHR miss cycles
702system.cpu.l2cache.demand_mshr_miss_latency::total 28690750 # number of demand (read+write) MSHR miss cycles
703system.cpu.l2cache.overall_mshr_miss_latency::cpu.inst 19597750 # number of overall MSHR miss cycles
704system.cpu.l2cache.overall_mshr_miss_latency::cpu.data 9093000 # number of overall MSHR miss cycles
705system.cpu.l2cache.overall_mshr_miss_latency::total 28690750 # number of overall MSHR miss cycles
706system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for ReadReq accesses
707system.cpu.l2cache.ReadReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadReq accesses
708system.cpu.l2cache.ReadReq_mshr_miss_rate::total 0.993007 # mshr miss rate for ReadReq accesses
709system.cpu.l2cache.ReadExReq_mshr_miss_rate::cpu.data 1 # mshr miss rate for ReadExReq accesses
710system.cpu.l2cache.ReadExReq_mshr_miss_rate::total 1 # mshr miss rate for ReadExReq accesses
711system.cpu.l2cache.demand_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for demand accesses
712system.cpu.l2cache.demand_mshr_miss_rate::cpu.data 1 # mshr miss rate for demand accesses
713system.cpu.l2cache.demand_mshr_miss_rate::total 0.993750 # mshr miss rate for demand accesses
714system.cpu.l2cache.overall_mshr_miss_rate::cpu.inst 0.991124 # mshr miss rate for overall accesses
715system.cpu.l2cache.overall_mshr_miss_rate::cpu.data 1 # mshr miss rate for overall accesses
716system.cpu.l2cache.overall_mshr_miss_rate::total 0.993750 # mshr miss rate for overall accesses
717system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.inst 58500.746269 # average ReadReq mshr miss latency
718system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::cpu.data 64942.307692 # average ReadReq mshr miss latency
719system.cpu.l2cache.ReadReq_avg_mshr_miss_latency::total 59876.760563 # average ReadReq mshr miss latency
720system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::cpu.data 62416.666667 # average ReadExReq mshr miss latency
721system.cpu.l2cache.ReadExReq_avg_mshr_miss_latency::total 62416.666667 # average ReadExReq mshr miss latency
722system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency
723system.cpu.l2cache.demand_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency
724system.cpu.l2cache.demand_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency
725system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.inst 58500.746269 # average overall mshr miss latency
726system.cpu.l2cache.overall_avg_mshr_miss_latency::cpu.data 64035.211268 # average overall mshr miss latency
727system.cpu.l2cache.overall_avg_mshr_miss_latency::total 60148.322851 # average overall mshr miss latency
728system.cpu.l2cache.no_allocate_misses 0 # Number of misses that were no-allocate
729system.cpu.dcache.tags.replacements 0 # number of replacements
730system.cpu.dcache.tags.tagsinuse 91.712882 # Cycle average of tags in use
731system.cpu.dcache.tags.total_refs 2395 # Total number of references to valid blocks.
732system.cpu.dcache.tags.sampled_refs 142 # Sample count of references to valid blocks.
733system.cpu.dcache.tags.avg_refs 16.866197 # Average number of references to valid blocks.
734system.cpu.dcache.tags.warmup_cycle 0 # Cycle when the warmup percentage was hit.
735system.cpu.dcache.tags.occ_blocks::cpu.data 91.712882 # Average occupied blocks per requestor
736system.cpu.dcache.tags.occ_percent::cpu.data 0.022391 # Average percentage of cache occupancy
737system.cpu.dcache.tags.occ_percent::total 0.022391 # Average percentage of cache occupancy
738system.cpu.dcache.ReadReq_hits::cpu.data 1832 # number of ReadReq hits
739system.cpu.dcache.ReadReq_hits::total 1832 # number of ReadReq hits
740system.cpu.dcache.WriteReq_hits::cpu.data 563 # number of WriteReq hits
741system.cpu.dcache.WriteReq_hits::total 563 # number of WriteReq hits
742system.cpu.dcache.demand_hits::cpu.data 2395 # number of demand (read+write) hits
743system.cpu.dcache.demand_hits::total 2395 # number of demand (read+write) hits
744system.cpu.dcache.overall_hits::cpu.data 2395 # number of overall hits
745system.cpu.dcache.overall_hits::total 2395 # number of overall hits
746system.cpu.dcache.ReadReq_misses::cpu.data 148 # number of ReadReq misses
747system.cpu.dcache.ReadReq_misses::total 148 # number of ReadReq misses
748system.cpu.dcache.WriteReq_misses::cpu.data 362 # number of WriteReq misses
749system.cpu.dcache.WriteReq_misses::total 362 # number of WriteReq misses
750system.cpu.dcache.demand_misses::cpu.data 510 # number of demand (read+write) misses
751system.cpu.dcache.demand_misses::total 510 # number of demand (read+write) misses
752system.cpu.dcache.overall_misses::cpu.data 510 # number of overall misses
753system.cpu.dcache.overall_misses::total 510 # number of overall misses
754system.cpu.dcache.ReadReq_miss_latency::cpu.data 10190250 # number of ReadReq miss cycles
755system.cpu.dcache.ReadReq_miss_latency::total 10190250 # number of ReadReq miss cycles
756system.cpu.dcache.WriteReq_miss_latency::cpu.data 22575249 # number of WriteReq miss cycles
757system.cpu.dcache.WriteReq_miss_latency::total 22575249 # number of WriteReq miss cycles
758system.cpu.dcache.demand_miss_latency::cpu.data 32765499 # number of demand (read+write) miss cycles
759system.cpu.dcache.demand_miss_latency::total 32765499 # number of demand (read+write) miss cycles
760system.cpu.dcache.overall_miss_latency::cpu.data 32765499 # number of overall miss cycles
761system.cpu.dcache.overall_miss_latency::total 32765499 # number of overall miss cycles
762system.cpu.dcache.ReadReq_accesses::cpu.data 1980 # number of ReadReq accesses(hits+misses)
763system.cpu.dcache.ReadReq_accesses::total 1980 # number of ReadReq accesses(hits+misses)
764system.cpu.dcache.WriteReq_accesses::cpu.data 925 # number of WriteReq accesses(hits+misses)
765system.cpu.dcache.WriteReq_accesses::total 925 # number of WriteReq accesses(hits+misses)
766system.cpu.dcache.demand_accesses::cpu.data 2905 # number of demand (read+write) accesses
767system.cpu.dcache.demand_accesses::total 2905 # number of demand (read+write) accesses
768system.cpu.dcache.overall_accesses::cpu.data 2905 # number of overall (read+write) accesses
769system.cpu.dcache.overall_accesses::total 2905 # number of overall (read+write) accesses
770system.cpu.dcache.ReadReq_miss_rate::cpu.data 0.074747 # miss rate for ReadReq accesses
771system.cpu.dcache.ReadReq_miss_rate::total 0.074747 # miss rate for ReadReq accesses
772system.cpu.dcache.WriteReq_miss_rate::cpu.data 0.391351 # miss rate for WriteReq accesses
773system.cpu.dcache.WriteReq_miss_rate::total 0.391351 # miss rate for WriteReq accesses
774system.cpu.dcache.demand_miss_rate::cpu.data 0.175559 # miss rate for demand accesses
775system.cpu.dcache.demand_miss_rate::total 0.175559 # miss rate for demand accesses
776system.cpu.dcache.overall_miss_rate::cpu.data 0.175559 # miss rate for overall accesses
777system.cpu.dcache.overall_miss_rate::total 0.175559 # miss rate for overall accesses
778system.cpu.dcache.ReadReq_avg_miss_latency::cpu.data 68853.040541 # average ReadReq miss latency
779system.cpu.dcache.ReadReq_avg_miss_latency::total 68853.040541 # average ReadReq miss latency
780system.cpu.dcache.WriteReq_avg_miss_latency::cpu.data 62362.566298 # average WriteReq miss latency
781system.cpu.dcache.WriteReq_avg_miss_latency::total 62362.566298 # average WriteReq miss latency
782system.cpu.dcache.demand_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency
783system.cpu.dcache.demand_avg_miss_latency::total 64246.076471 # average overall miss latency
784system.cpu.dcache.overall_avg_miss_latency::cpu.data 64246.076471 # average overall miss latency
785system.cpu.dcache.overall_avg_miss_latency::total 64246.076471 # average overall miss latency
786system.cpu.dcache.blocked_cycles::no_mshrs 605 # number of cycles access was blocked
787system.cpu.dcache.blocked_cycles::no_targets 0 # number of cycles access was blocked
788system.cpu.dcache.blocked::no_mshrs 11 # number of cycles access was blocked
789system.cpu.dcache.blocked::no_targets 0 # number of cycles access was blocked
790system.cpu.dcache.avg_blocked_cycles::no_mshrs 55 # average number of cycles each access was blocked
791system.cpu.dcache.avg_blocked_cycles::no_targets nan # average number of cycles each access was blocked
792system.cpu.dcache.fast_writes 0 # number of fast writes performed
793system.cpu.dcache.cache_copies 0 # number of cache copies performed
794system.cpu.dcache.ReadReq_mshr_hits::cpu.data 57 # number of ReadReq MSHR hits
795system.cpu.dcache.ReadReq_mshr_hits::total 57 # number of ReadReq MSHR hits
796system.cpu.dcache.WriteReq_mshr_hits::cpu.data 311 # number of WriteReq MSHR hits
797system.cpu.dcache.WriteReq_mshr_hits::total 311 # number of WriteReq MSHR hits
798system.cpu.dcache.demand_mshr_hits::cpu.data 368 # number of demand (read+write) MSHR hits
799system.cpu.dcache.demand_mshr_hits::total 368 # number of demand (read+write) MSHR hits
800system.cpu.dcache.overall_mshr_hits::cpu.data 368 # number of overall MSHR hits
801system.cpu.dcache.overall_mshr_hits::total 368 # number of overall MSHR hits
802system.cpu.dcache.ReadReq_mshr_misses::cpu.data 91 # number of ReadReq MSHR misses
803system.cpu.dcache.ReadReq_mshr_misses::total 91 # number of ReadReq MSHR misses
804system.cpu.dcache.WriteReq_mshr_misses::cpu.data 51 # number of WriteReq MSHR misses
805system.cpu.dcache.WriteReq_mshr_misses::total 51 # number of WriteReq MSHR misses
806system.cpu.dcache.demand_mshr_misses::cpu.data 142 # number of demand (read+write) MSHR misses
807system.cpu.dcache.demand_mshr_misses::total 142 # number of demand (read+write) MSHR misses
808system.cpu.dcache.overall_mshr_misses::cpu.data 142 # number of overall MSHR misses
809system.cpu.dcache.overall_mshr_misses::total 142 # number of overall MSHR misses
810system.cpu.dcache.ReadReq_mshr_miss_latency::cpu.data 7121250 # number of ReadReq MSHR miss cycles
811system.cpu.dcache.ReadReq_mshr_miss_latency::total 7121250 # number of ReadReq MSHR miss cycles
812system.cpu.dcache.WriteReq_mshr_miss_latency::cpu.data 3866249 # number of WriteReq MSHR miss cycles
813system.cpu.dcache.WriteReq_mshr_miss_latency::total 3866249 # number of WriteReq MSHR miss cycles
814system.cpu.dcache.demand_mshr_miss_latency::cpu.data 10987499 # number of demand (read+write) MSHR miss cycles
815system.cpu.dcache.demand_mshr_miss_latency::total 10987499 # number of demand (read+write) MSHR miss cycles
816system.cpu.dcache.overall_mshr_miss_latency::cpu.data 10987499 # number of overall MSHR miss cycles
817system.cpu.dcache.overall_mshr_miss_latency::total 10987499 # number of overall MSHR miss cycles
818system.cpu.dcache.ReadReq_mshr_miss_rate::cpu.data 0.045960 # mshr miss rate for ReadReq accesses
819system.cpu.dcache.ReadReq_mshr_miss_rate::total 0.045960 # mshr miss rate for ReadReq accesses
820system.cpu.dcache.WriteReq_mshr_miss_rate::cpu.data 0.055135 # mshr miss rate for WriteReq accesses
821system.cpu.dcache.WriteReq_mshr_miss_rate::total 0.055135 # mshr miss rate for WriteReq accesses
822system.cpu.dcache.demand_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for demand accesses
823system.cpu.dcache.demand_mshr_miss_rate::total 0.048881 # mshr miss rate for demand accesses
824system.cpu.dcache.overall_mshr_miss_rate::cpu.data 0.048881 # mshr miss rate for overall accesses
825system.cpu.dcache.overall_mshr_miss_rate::total 0.048881 # mshr miss rate for overall accesses
826system.cpu.dcache.ReadReq_avg_mshr_miss_latency::cpu.data 78255.494505 # average ReadReq mshr miss latency
827system.cpu.dcache.ReadReq_avg_mshr_miss_latency::total 78255.494505 # average ReadReq mshr miss latency
828system.cpu.dcache.WriteReq_avg_mshr_miss_latency::cpu.data 75808.803922 # average WriteReq mshr miss latency
829system.cpu.dcache.WriteReq_avg_mshr_miss_latency::total 75808.803922 # average WriteReq mshr miss latency
830system.cpu.dcache.demand_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency
831system.cpu.dcache.demand_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency
832system.cpu.dcache.overall_avg_mshr_miss_latency::cpu.data 77376.753521 # average overall mshr miss latency
833system.cpu.dcache.overall_avg_mshr_miss_latency::total 77376.753521 # average overall mshr miss latency
834system.cpu.dcache.no_allocate_misses 0 # Number of misses that were no-allocate
835
836---------- End Simulation Statistics ----------