| config.ini (9276:a5ede748a1d9) | config.ini (9348:44d31345e360) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a |
| 13clock=1 | 13clock=1000 |
| 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU | 14init_param=0 15kernel= 16load_addr_mask=1099511627775 17mem_mode=atomic 18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU |
| 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload | 33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload |
| 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 --- 31 unchanged lines hidden (view full) --- 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts | 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 --- 31 unchanged lines hidden (view full) --- 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts |
| 81isa=system.cpu.isa |
|
| 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 --- 35 unchanged lines hidden (view full) --- 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache 129addr_ranges=0:18446744073709551615 130assoc=2 131block_size=64 | 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 --- 35 unchanged lines hidden (view full) --- 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 |
| 132clock=1 | 133clock=500 |
| 133forward_snoops=true 134hash_delay=1 | 134forward_snoops=true 135hash_delay=1 |
| 135hit_latency=1000 | 136hit_latency=2 |
| 136is_top_level=true 137max_miss_count=0 | 137is_top_level=true 138max_miss_count=0 |
| 138mshrs=10 | 139mshrs=4 |
| 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null | 140prefetch_on_access=false 141prefetcher=Null 142prioritizeRequests=false 143repl=Null |
| 143response_latency=1000 | 144response_latency=2 |
| 144size=262144 145subblock_size=0 146system=system 147tgts_per_mshr=20 148trace_addr=0 149two_queue=false 150write_buffers=8 151cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 418opClass=IprAccess 419opLat=3 420 421[system.cpu.icache] 422type=BaseCache 423addr_ranges=0:18446744073709551615 424assoc=2 425block_size=64 | 145size=262144 146subblock_size=0 147system=system 148tgts_per_mshr=20 149trace_addr=0 150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port --- 266 unchanged lines hidden (view full) --- 419opClass=IprAccess 420opLat=3 421 422[system.cpu.icache] 423type=BaseCache 424addr_ranges=0:18446744073709551615 425assoc=2 426block_size=64 |
| 426clock=1 | 427clock=500 |
| 427forward_snoops=true 428hash_delay=1 | 428forward_snoops=true 429hash_delay=1 |
| 429hit_latency=1000 | 430hit_latency=2 |
| 430is_top_level=true 431max_miss_count=0 | 431is_top_level=true 432max_miss_count=0 |
| 432mshrs=10 | 433mshrs=4 |
| 433prefetch_on_access=false 434prefetcher=Null 435prioritizeRequests=false 436repl=Null | 434prefetch_on_access=false 435prefetcher=Null 436prioritizeRequests=false 437repl=Null |
| 437response_latency=1000 | 438response_latency=2 |
| 438size=131072 439subblock_size=0 440system=system 441tgts_per_mshr=20 442trace_addr=0 443two_queue=false 444write_buffers=8 445cpu_side=system.cpu.icache_port 446mem_side=system.cpu.toL2Bus.slave[0] 447 448[system.cpu.interrupts] 449type=MipsInterrupts 450 | 439size=131072 440subblock_size=0 441system=system 442tgts_per_mshr=20 443trace_addr=0 444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.slave[0] 448 449[system.cpu.interrupts] 450type=MipsInterrupts 451 |
| 452[system.cpu.isa] 453type=MipsISA 454num_threads=1 455num_vpes=1 456 |
|
| 451[system.cpu.itb] 452type=MipsTLB 453size=64 454 455[system.cpu.l2cache] 456type=BaseCache 457addr_ranges=0:18446744073709551615 | 457[system.cpu.itb] 458type=MipsTLB 459size=64 460 461[system.cpu.l2cache] 462type=BaseCache 463addr_ranges=0:18446744073709551615 |
| 458assoc=2 | 464assoc=8 |
| 459block_size=64 | 465block_size=64 |
| 460clock=1 | 466clock=500 |
| 461forward_snoops=true 462hash_delay=1 | 467forward_snoops=true 468hash_delay=1 |
| 463hit_latency=1000 | 469hit_latency=20 |
| 464is_top_level=false 465max_miss_count=0 | 470is_top_level=false 471max_miss_count=0 |
| 466mshrs=10 | 472mshrs=20 |
| 467prefetch_on_access=false 468prefetcher=Null 469prioritizeRequests=false 470repl=Null | 473prefetch_on_access=false 474prefetcher=Null 475prioritizeRequests=false 476repl=Null |
| 471response_latency=1000 | 477response_latency=20 |
| 472size=2097152 473subblock_size=0 474system=system | 478size=2097152 479subblock_size=0 480system=system |
| 475tgts_per_mshr=5 | 481tgts_per_mshr=12 |
| 476trace_addr=0 477two_queue=false 478write_buffers=8 479cpu_side=system.cpu.toL2Bus.master[0] 480mem_side=system.membus.slave[1] 481 482[system.cpu.toL2Bus] 483type=CoherentBus 484block_size=64 | 482trace_addr=0 483two_queue=false 484write_buffers=8 485cpu_side=system.cpu.toL2Bus.master[0] 486mem_side=system.membus.slave[1] 487 488[system.cpu.toL2Bus] 489type=CoherentBus 490block_size=64 |
| 485clock=1000 | 491clock=500 |
| 486header_cycles=1 487use_default_range=false | 492header_cycles=1 493use_default_range=false |
| 488width=8 | 494width=32 |
| 489master=system.cpu.l2cache.cpu_side 490slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 491 492[system.cpu.tracer] 493type=ExeTracer 494 495[system.cpu.workload] 496type=LiveProcess 497cmd=hello 498cwd= 499egid=100 500env= 501errout=cerr 502euid=100 | 495master=system.cpu.l2cache.cpu_side 496slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 497 498[system.cpu.tracer] 499type=ExeTracer 500 501[system.cpu.workload] 502type=LiveProcess 503cmd=hello 504cwd= 505egid=100 506env= 507errout=cerr 508euid=100 |
| 503executable=tests/test-progs/hello/bin/mips/linux/hello | 509executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello |
| 504gid=100 505input=cin 506max_stack_size=67108864 507output=cout 508pid=100 509ppid=99 510simpoint=0 511system=system --- 5 unchanged lines hidden (view full) --- 517clock=1000 518header_cycles=1 519use_default_range=false 520width=8 521master=system.physmem.port 522slave=system.system_port system.cpu.l2cache.mem_side 523 524[system.physmem] | 510gid=100 511input=cin 512max_stack_size=67108864 513output=cout 514pid=100 515ppid=99 516simpoint=0 517system=system --- 5 unchanged lines hidden (view full) --- 523clock=1000 524header_cycles=1 525use_default_range=false 526width=8 527master=system.physmem.port 528slave=system.system_port system.cpu.l2cache.mem_side 529 530[system.physmem] |
| 525type=SimpleMemory 526bandwidth=73.000000 527clock=1 | 531type=SimpleDRAM 532addr_mapping=openmap 533banks_per_rank=8 534clock=1000 |
| 528conf_table_reported=false 529in_addr_map=true | 535conf_table_reported=false 536in_addr_map=true |
| 530latency=30000 531latency_var=0 | 537lines_per_rowbuffer=64 538mem_sched_policy=fcfs |
| 532null=false | 539null=false |
| 540page_policy=open |
|
| 533range=0:134217727 | 541range=0:134217727 |
| 542ranks_per_channel=2 543read_buffer_size=32 544tBURST=4000 545tCL=14000 546tRCD=14000 547tREFI=7800000 548tRFC=300000 549tRP=14000 550tWTR=1000 551write_buffer_size=32 552write_thresh_perc=70 |
|
| 534zero=false 535port=system.membus.master[0] 536 | 553zero=false 554port=system.membus.master[0] 555 |