| config.ini (8983:8800b05e1cb3) | config.ini (9055:38f1926fb599) |
|---|---|
| 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 460 unchanged lines hidden (view full) --- 469tgts_per_mshr=5 470trace_addr=0 471two_queue=false 472write_buffers=8 473cpu_side=system.cpu.toL2Bus.master[0] 474mem_side=system.membus.slave[1] 475 476[system.cpu.toL2Bus] | 1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 --- 460 unchanged lines hidden (view full) --- 469tgts_per_mshr=5 470trace_addr=0 471two_queue=false 472write_buffers=8 473cpu_side=system.cpu.toL2Bus.master[0] 474mem_side=system.membus.slave[1] 475 476[system.cpu.toL2Bus] |
| 477type=Bus | 477type=CoherentBus |
| 478block_size=64 | 478block_size=64 |
| 479bus_id=0 | |
| 480clock=1000 481header_cycles=1 482use_default_range=false 483width=64 484master=system.cpu.l2cache.cpu_side 485slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 486 487[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.membus] | 479clock=1000 480header_cycles=1 481use_default_range=false 482width=64 483master=system.cpu.l2cache.cpu_side 484slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 485 486[system.cpu.tracer] --- 14 unchanged lines hidden (view full) --- 501output=cout 502pid=100 503ppid=99 504simpoint=0 505system=system 506uid=100 507 508[system.membus] |
| 510type=Bus | 509type=CoherentBus |
| 511block_size=64 | 510block_size=64 |
| 512bus_id=0 | |
| 513clock=1000 514header_cycles=1 515use_default_range=false 516width=64 517master=system.physmem.port[0] 518slave=system.system_port system.cpu.l2cache.mem_side 519 520[system.physmem] 521type=SimpleMemory 522conf_table_reported=false 523file= 524in_addr_map=true 525latency=30000 526latency_var=0 527null=false 528range=0:134217727 529zero=false 530port=system.membus.master[0] 531 | 511clock=1000 512header_cycles=1 513use_default_range=false 514width=64 515master=system.physmem.port[0] 516slave=system.system_port system.cpu.l2cache.mem_side 517 518[system.physmem] 519type=SimpleMemory 520conf_table_reported=false 521file= 522in_addr_map=true 523latency=30000 524latency_var=0 525null=false 526range=0:134217727 527zero=false 528port=system.membus.master[0] 529 |