| config.ini (11680:b4d943429dc6) | config.ini (11731:c473ca7cc650) |
|---|---|
| 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 163 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 163 unchanged lines hidden (view full) --- 172 173[system.cpu.dcache] 174type=Cache 175children=tags 176addr_ranges=0:18446744073709551615:0:0:0:0 177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl |
| 180data_latency=2 |
|
| 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 | 181default_p_state=UNDEFINED 182demand_mshr_reserve=1 183eventq_index=0 |
| 183hit_latency=2 | |
| 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system | 184is_read_only=false 185max_miss_count=0 186mshrs=4 187p_state_clk_gate_bins=20 188p_state_clk_gate_max=1000000000000 189p_state_clk_gate_min=1000 190power_model=Null 191prefetch_on_access=false 192prefetcher=Null 193response_latency=2 194sequential_access=false 195size=262144 196system=system |
| 197tag_latency=2 |
|
| 197tags=system.cpu.dcache.tags 198tgts_per_mshr=20 199write_buffers=8 200writeback_clean=false 201cpu_side=system.cpu.dcache_port 202mem_side=system.cpu.toL2Bus.slave[1] 203 204[system.cpu.dcache.tags] 205type=LRU 206assoc=2 207block_size=64 208clk_domain=system.cpu_clk_domain | 198tags=system.cpu.dcache.tags 199tgts_per_mshr=20 200write_buffers=8 201writeback_clean=false 202cpu_side=system.cpu.dcache_port 203mem_side=system.cpu.toL2Bus.slave[1] 204 205[system.cpu.dcache.tags] 206type=LRU 207assoc=2 208block_size=64 209clk_domain=system.cpu_clk_domain |
| 210data_latency=2 |
|
| 209default_p_state=UNDEFINED 210eventq_index=0 | 211default_p_state=UNDEFINED 212eventq_index=0 |
| 211hit_latency=2 | |
| 212p_state_clk_gate_bins=20 213p_state_clk_gate_max=1000000000000 214p_state_clk_gate_min=1000 215power_model=Null 216sequential_access=false 217size=262144 | 213p_state_clk_gate_bins=20 214p_state_clk_gate_max=1000000000000 215p_state_clk_gate_min=1000 216power_model=Null 217sequential_access=false 218size=262144 |
| 219tag_latency=2 |
|
| 218 219[system.cpu.dtb] 220type=MipsTLB 221eventq_index=0 222size=64 223 224[system.cpu.fuPool] 225type=FUPool --- 61 unchanged lines hidden (view full) --- 287type=OpDesc 288eventq_index=0 289opClass=FloatCvt 290opLat=2 291pipelined=true 292 293[system.cpu.fuPool.FUList3] 294type=FUDesc | 220 221[system.cpu.dtb] 222type=MipsTLB 223eventq_index=0 224size=64 225 226[system.cpu.fuPool] 227type=FUPool --- 61 unchanged lines hidden (view full) --- 289type=OpDesc 290eventq_index=0 291opClass=FloatCvt 292opLat=2 293pipelined=true 294 295[system.cpu.fuPool.FUList3] 296type=FUDesc |
| 295children=opList0 opList1 opList2 | 297children=opList0 opList1 opList2 opList3 opList4 |
| 296count=2 297eventq_index=0 | 298count=2 299eventq_index=0 |
| 298opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 | 300opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 system.cpu.fuPool.FUList3.opList3 system.cpu.fuPool.FUList3.opList4 |
| 299 300[system.cpu.fuPool.FUList3.opList0] 301type=OpDesc 302eventq_index=0 303opClass=FloatMult 304opLat=4 305pipelined=true 306 307[system.cpu.fuPool.FUList3.opList1] 308type=OpDesc 309eventq_index=0 | 301 302[system.cpu.fuPool.FUList3.opList0] 303type=OpDesc 304eventq_index=0 305opClass=FloatMult 306opLat=4 307pipelined=true 308 309[system.cpu.fuPool.FUList3.opList1] 310type=OpDesc 311eventq_index=0 |
| 312opClass=FloatMultAcc 313opLat=5 314pipelined=true 315 316[system.cpu.fuPool.FUList3.opList2] 317type=OpDesc 318eventq_index=0 319opClass=FloatMisc 320opLat=3 321pipelined=true 322 323[system.cpu.fuPool.FUList3.opList3] 324type=OpDesc 325eventq_index=0 |
|
| 310opClass=FloatDiv 311opLat=12 312pipelined=false 313 | 326opClass=FloatDiv 327opLat=12 328pipelined=false 329 |
| 314[system.cpu.fuPool.FUList3.opList2] | 330[system.cpu.fuPool.FUList3.opList4] |
| 315type=OpDesc 316eventq_index=0 317opClass=FloatSqrt 318opLat=24 319pipelined=false 320 321[system.cpu.fuPool.FUList4] 322type=FUDesc | 331type=OpDesc 332eventq_index=0 333opClass=FloatSqrt 334opLat=24 335pipelined=false 336 337[system.cpu.fuPool.FUList4] 338type=FUDesc |
| 323children=opList | 339children=opList0 opList1 |
| 324count=0 325eventq_index=0 | 340count=0 341eventq_index=0 |
| 326opList=system.cpu.fuPool.FUList4.opList | 342opList=system.cpu.fuPool.FUList4.opList0 system.cpu.fuPool.FUList4.opList1 |
| 327 | 343 |
| 328[system.cpu.fuPool.FUList4.opList] | 344[system.cpu.fuPool.FUList4.opList0] |
| 329type=OpDesc 330eventq_index=0 331opClass=MemRead 332opLat=1 333pipelined=true 334 | 345type=OpDesc 346eventq_index=0 347opClass=MemRead 348opLat=1 349pipelined=true 350 |
| 351[system.cpu.fuPool.FUList4.opList1] 352type=OpDesc 353eventq_index=0 354opClass=FloatMemRead 355opLat=1 356pipelined=true 357 |
|
| 335[system.cpu.fuPool.FUList5] 336type=FUDesc 337children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 338count=4 339eventq_index=0 340opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 341 342[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 476type=OpDesc 477eventq_index=0 478opClass=SimdFloatSqrt 479opLat=1 480pipelined=true 481 482[system.cpu.fuPool.FUList6] 483type=FUDesc | 358[system.cpu.fuPool.FUList5] 359type=FUDesc 360children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 361count=4 362eventq_index=0 363opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 364 365[system.cpu.fuPool.FUList5.opList00] --- 133 unchanged lines hidden (view full) --- 499type=OpDesc 500eventq_index=0 501opClass=SimdFloatSqrt 502opLat=1 503pipelined=true 504 505[system.cpu.fuPool.FUList6] 506type=FUDesc |
| 484children=opList | 507children=opList0 opList1 |
| 485count=0 486eventq_index=0 | 508count=0 509eventq_index=0 |
| 487opList=system.cpu.fuPool.FUList6.opList | 510opList=system.cpu.fuPool.FUList6.opList0 system.cpu.fuPool.FUList6.opList1 |
| 488 | 511 |
| 489[system.cpu.fuPool.FUList6.opList] | 512[system.cpu.fuPool.FUList6.opList0] |
| 490type=OpDesc 491eventq_index=0 492opClass=MemWrite 493opLat=1 494pipelined=true 495 | 513type=OpDesc 514eventq_index=0 515opClass=MemWrite 516opLat=1 517pipelined=true 518 |
| 519[system.cpu.fuPool.FUList6.opList1] 520type=OpDesc 521eventq_index=0 522opClass=FloatMemWrite 523opLat=1 524pipelined=true 525 |
|
| 496[system.cpu.fuPool.FUList7] 497type=FUDesc | 526[system.cpu.fuPool.FUList7] 527type=FUDesc |
| 498children=opList0 opList1 | 528children=opList0 opList1 opList2 opList3 |
| 499count=4 500eventq_index=0 | 529count=4 530eventq_index=0 |
| 501opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 | 531opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 system.cpu.fuPool.FUList7.opList2 system.cpu.fuPool.FUList7.opList3 |
| 502 503[system.cpu.fuPool.FUList7.opList0] 504type=OpDesc 505eventq_index=0 506opClass=MemRead 507opLat=1 508pipelined=true 509 510[system.cpu.fuPool.FUList7.opList1] 511type=OpDesc 512eventq_index=0 513opClass=MemWrite 514opLat=1 515pipelined=true 516 | 532 533[system.cpu.fuPool.FUList7.opList0] 534type=OpDesc 535eventq_index=0 536opClass=MemRead 537opLat=1 538pipelined=true 539 540[system.cpu.fuPool.FUList7.opList1] 541type=OpDesc 542eventq_index=0 543opClass=MemWrite 544opLat=1 545pipelined=true 546 |
| 547[system.cpu.fuPool.FUList7.opList2] 548type=OpDesc 549eventq_index=0 550opClass=FloatMemRead 551opLat=1 552pipelined=true 553 554[system.cpu.fuPool.FUList7.opList3] 555type=OpDesc 556eventq_index=0 557opClass=FloatMemWrite 558opLat=1 559pipelined=true 560 |
|
| 517[system.cpu.fuPool.FUList8] 518type=FUDesc 519children=opList 520count=1 521eventq_index=0 522opList=system.cpu.fuPool.FUList8.opList 523 524[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 530 531[system.cpu.icache] 532type=Cache 533children=tags 534addr_ranges=0:18446744073709551615:0:0:0:0 535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl | 561[system.cpu.fuPool.FUList8] 562type=FUDesc 563children=opList 564count=1 565eventq_index=0 566opList=system.cpu.fuPool.FUList8.opList 567 568[system.cpu.fuPool.FUList8.opList] --- 5 unchanged lines hidden (view full) --- 574 575[system.cpu.icache] 576type=Cache 577children=tags 578addr_ranges=0:18446744073709551615:0:0:0:0 579assoc=2 580clk_domain=system.cpu_clk_domain 581clusivity=mostly_incl |
| 582data_latency=2 |
|
| 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 | 583default_p_state=UNDEFINED 584demand_mshr_reserve=1 585eventq_index=0 |
| 541hit_latency=2 | |
| 542is_read_only=true 543max_miss_count=0 544mshrs=4 545p_state_clk_gate_bins=20 546p_state_clk_gate_max=1000000000000 547p_state_clk_gate_min=1000 548power_model=Null 549prefetch_on_access=false 550prefetcher=Null 551response_latency=2 552sequential_access=false 553size=131072 554system=system | 586is_read_only=true 587max_miss_count=0 588mshrs=4 589p_state_clk_gate_bins=20 590p_state_clk_gate_max=1000000000000 591p_state_clk_gate_min=1000 592power_model=Null 593prefetch_on_access=false 594prefetcher=Null 595response_latency=2 596sequential_access=false 597size=131072 598system=system |
| 599tag_latency=2 |
|
| 555tags=system.cpu.icache.tags 556tgts_per_mshr=20 557write_buffers=8 558writeback_clean=true 559cpu_side=system.cpu.icache_port 560mem_side=system.cpu.toL2Bus.slave[0] 561 562[system.cpu.icache.tags] 563type=LRU 564assoc=2 565block_size=64 566clk_domain=system.cpu_clk_domain | 600tags=system.cpu.icache.tags 601tgts_per_mshr=20 602write_buffers=8 603writeback_clean=true 604cpu_side=system.cpu.icache_port 605mem_side=system.cpu.toL2Bus.slave[0] 606 607[system.cpu.icache.tags] 608type=LRU 609assoc=2 610block_size=64 611clk_domain=system.cpu_clk_domain |
| 612data_latency=2 |
|
| 567default_p_state=UNDEFINED 568eventq_index=0 | 613default_p_state=UNDEFINED 614eventq_index=0 |
| 569hit_latency=2 | |
| 570p_state_clk_gate_bins=20 571p_state_clk_gate_max=1000000000000 572p_state_clk_gate_min=1000 573power_model=Null 574sequential_access=false 575size=131072 | 615p_state_clk_gate_bins=20 616p_state_clk_gate_max=1000000000000 617p_state_clk_gate_min=1000 618power_model=Null 619sequential_access=false 620size=131072 |
| 621tag_latency=2 |
|
| 576 577[system.cpu.interrupts] 578type=MipsInterrupts 579eventq_index=0 580 581[system.cpu.isa] 582type=MipsISA 583eventq_index=0 --- 8 unchanged lines hidden (view full) --- 592 593[system.cpu.l2cache] 594type=Cache 595children=tags 596addr_ranges=0:18446744073709551615:0:0:0:0 597assoc=8 598clk_domain=system.cpu_clk_domain 599clusivity=mostly_incl | 622 623[system.cpu.interrupts] 624type=MipsInterrupts 625eventq_index=0 626 627[system.cpu.isa] 628type=MipsISA 629eventq_index=0 --- 8 unchanged lines hidden (view full) --- 638 639[system.cpu.l2cache] 640type=Cache 641children=tags 642addr_ranges=0:18446744073709551615:0:0:0:0 643assoc=8 644clk_domain=system.cpu_clk_domain 645clusivity=mostly_incl |
| 646data_latency=20 |
|
| 600default_p_state=UNDEFINED 601demand_mshr_reserve=1 602eventq_index=0 | 647default_p_state=UNDEFINED 648demand_mshr_reserve=1 649eventq_index=0 |
| 603hit_latency=20 | |
| 604is_read_only=false 605max_miss_count=0 606mshrs=20 607p_state_clk_gate_bins=20 608p_state_clk_gate_max=1000000000000 609p_state_clk_gate_min=1000 610power_model=Null 611prefetch_on_access=false 612prefetcher=Null 613response_latency=20 614sequential_access=false 615size=2097152 616system=system | 650is_read_only=false 651max_miss_count=0 652mshrs=20 653p_state_clk_gate_bins=20 654p_state_clk_gate_max=1000000000000 655p_state_clk_gate_min=1000 656power_model=Null 657prefetch_on_access=false 658prefetcher=Null 659response_latency=20 660sequential_access=false 661size=2097152 662system=system |
| 663tag_latency=20 |
|
| 617tags=system.cpu.l2cache.tags 618tgts_per_mshr=12 619write_buffers=8 620writeback_clean=false 621cpu_side=system.cpu.toL2Bus.master[0] 622mem_side=system.membus.slave[1] 623 624[system.cpu.l2cache.tags] 625type=LRU 626assoc=8 627block_size=64 628clk_domain=system.cpu_clk_domain | 664tags=system.cpu.l2cache.tags 665tgts_per_mshr=12 666write_buffers=8 667writeback_clean=false 668cpu_side=system.cpu.toL2Bus.master[0] 669mem_side=system.membus.slave[1] 670 671[system.cpu.l2cache.tags] 672type=LRU 673assoc=8 674block_size=64 675clk_domain=system.cpu_clk_domain |
| 676data_latency=20 |
|
| 629default_p_state=UNDEFINED 630eventq_index=0 | 677default_p_state=UNDEFINED 678eventq_index=0 |
| 631hit_latency=20 | |
| 632p_state_clk_gate_bins=20 633p_state_clk_gate_max=1000000000000 634p_state_clk_gate_min=1000 635power_model=Null 636sequential_access=false 637size=2097152 | 679p_state_clk_gate_bins=20 680p_state_clk_gate_max=1000000000000 681p_state_clk_gate_min=1000 682power_model=Null 683sequential_access=false 684size=2097152 |
| 685tag_latency=20 |
|
| 638 639[system.cpu.toL2Bus] 640type=CoherentXBar 641children=snoop_filter 642clk_domain=system.cpu_clk_domain 643default_p_state=UNDEFINED 644eventq_index=0 645forward_latency=0 --- 28 unchanged lines hidden (view full) --- 674cmd=hello 675cwd= 676drivers= 677egid=100 678env= 679errout=cerr 680euid=100 681eventq_index=0 | 686 687[system.cpu.toL2Bus] 688type=CoherentXBar 689children=snoop_filter 690clk_domain=system.cpu_clk_domain 691default_p_state=UNDEFINED 692eventq_index=0 693forward_latency=0 --- 28 unchanged lines hidden (view full) --- 722cmd=hello 723cwd= 724drivers= 725egid=100 726env= 727errout=cerr 728euid=100 729eventq_index=0 |
| 682executable=/arm/projectscratch/randd/systems/dist/test-progs/hello/bin/mips/linux/hello | 730executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello |
| 683gid=100 684input=cin 685kvmInSE=false 686max_stack_size=67108864 687output=cout 688pid=100 689ppid=99 690simpoint=0 --- 137 unchanged lines hidden --- | 731gid=100 732input=cin 733kvmInSE=false 734max_stack_size=67108864 735output=cout 736pid=100 737ppid=99 738simpoint=0 --- 137 unchanged lines hidden --- |