config.ini (10036:80e84beef3bb) | config.ini (10242:cb4e86c17767) |
---|---|
1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 4 unchanged lines hidden (view full) --- 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 | 1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 4 unchanged lines hidden (view full) --- 13children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain 14boot_osflags=a 15cache_line_size=64 16clk_domain=system.clk_domain 17eventq_index=0 18init_param=0 19kernel= 20load_addr_mask=1099511627775 |
21load_offset=0 |
|
21mem_mode=timing 22mem_ranges= 23memories=system.physmem 24num_work_ids=16 25readfile= 26symbolfile= 27work_begin_ckpt_count=0 28work_begin_cpu_id_exit=-1 --- 81 unchanged lines hidden (view full) --- 110smtFetchPolicy=SingleThread 111smtIQPolicy=Partitioned 112smtIQThreshold=100 113smtLSQPolicy=Partitioned 114smtLSQThreshold=100 115smtNumFetchingThreads=1 116smtROBPolicy=Partitioned 117smtROBThreshold=100 | 22mem_mode=timing 23mem_ranges= 24memories=system.physmem 25num_work_ids=16 26readfile= 27symbolfile= 28work_begin_ckpt_count=0 29work_begin_cpu_id_exit=-1 --- 81 unchanged lines hidden (view full) --- 111smtFetchPolicy=SingleThread 112smtIQPolicy=Partitioned 113smtIQThreshold=100 114smtLSQPolicy=Partitioned 115smtLSQThreshold=100 116smtNumFetchingThreads=1 117smtROBPolicy=Partitioned 118smtROBThreshold=100 |
119socket_id=0 |
|
118squashWidth=8 119store_set_clear_period=250000 120switched_out=false 121system=system 122tracer=system.cpu.tracer 123trapLatency=13 124wbDepth=1 125wbWidth=8 --- 470 unchanged lines hidden (view full) --- 596type=LiveProcess 597cmd=hello 598cwd= 599egid=100 600env= 601errout=cerr 602euid=100 603eventq_index=0 | 120squashWidth=8 121store_set_clear_period=250000 122switched_out=false 123system=system 124tracer=system.cpu.tracer 125trapLatency=13 126wbDepth=1 127wbWidth=8 --- 470 unchanged lines hidden (view full) --- 598type=LiveProcess 599cmd=hello 600cwd= 601egid=100 602env= 603errout=cerr 604euid=100 605eventq_index=0 |
604executable=/dist/test-progs/hello/bin/mips/linux/hello | 606executable=/home/stever/hg/m5sim.org/gem5/tests/test-progs/hello/bin/mips/linux/hello |
605gid=100 606input=cin 607max_stack_size=67108864 608output=cout 609pid=100 610ppid=99 611simpoint=0 612system=system --- 12 unchanged lines hidden (view full) --- 625header_cycles=1 626system=system 627use_default_range=false 628width=8 629master=system.physmem.port 630slave=system.system_port system.cpu.l2cache.mem_side 631 632[system.physmem] | 607gid=100 608input=cin 609max_stack_size=67108864 610output=cout 611pid=100 612ppid=99 613simpoint=0 614system=system --- 12 unchanged lines hidden (view full) --- 627header_cycles=1 628system=system 629use_default_range=false 630width=8 631master=system.physmem.port 632slave=system.system_port system.cpu.l2cache.mem_side 633 634[system.physmem] |
633type=SimpleDRAM | 635type=DRAMCtrl |
634activation_limit=4 | 636activation_limit=4 |
635addr_mapping=RaBaChCo | 637addr_mapping=RoRaBaChCo |
636banks_per_rank=8 637burst_length=8 638channels=1 639clk_domain=system.clk_domain 640conf_table_reported=true 641device_bus_width=8 642device_rowbuffer_size=1024 643devices_per_rank=8 644eventq_index=0 645in_addr_map=true | 638banks_per_rank=8 639burst_length=8 640channels=1 641clk_domain=system.clk_domain 642conf_table_reported=true 643device_bus_width=8 644device_rowbuffer_size=1024 645devices_per_rank=8 646eventq_index=0 647in_addr_map=true |
648max_accesses_per_row=16 |
|
646mem_sched_policy=frfcfs | 649mem_sched_policy=frfcfs |
650min_writes_per_switch=16 |
|
647null=false | 651null=false |
648page_policy=open | 652page_policy=open_adaptive |
649range=0:134217727 650ranks_per_channel=2 651read_buffer_size=32 652static_backend_latency=10000 653static_frontend_latency=10000 654tBURST=5000 | 653range=0:134217727 654ranks_per_channel=2 655read_buffer_size=32 656static_backend_latency=10000 657static_frontend_latency=10000 658tBURST=5000 |
659tCK=1250 |
|
655tCL=13750 656tRAS=35000 657tRCD=13750 658tREFI=7800000 | 660tCL=13750 661tRAS=35000 662tRCD=13750 663tREFI=7800000 |
659tRFC=300000 | 664tRFC=260000 |
660tRP=13750 | 665tRP=13750 |
661tRRD=6250 | 666tRRD=6000 667tRTP=7500 668tRTW=2500 669tWR=15000 |
662tWTR=7500 | 670tWTR=7500 |
663tXAW=40000 664write_buffer_size=32 665write_high_thresh_perc=70 666write_low_thresh_perc=0 | 671tXAW=30000 672write_buffer_size=64 673write_high_thresh_perc=85 674write_low_thresh_perc=50 |
667port=system.membus.master[0] 668 669[system.voltage_domain] 670type=VoltageDomain 671eventq_index=0 672voltage=1.000000 673 | 675port=system.membus.master[0] 676 677[system.voltage_domain] 678type=VoltageDomain 679eventq_index=0 680voltage=1.000000 681 |