1[root]
2type=Root
3children=system
4full_system=false
5time_sync_enable=false
6time_sync_period=100000000000
7time_sync_spin_threshold=100000000
8
9[system]
10type=System
11children=clk_domain cpu cpu_clk_domain membus physmem voltage_domain
12boot_osflags=a
13cache_line_size=64
14clk_domain=system.clk_domain
15init_param=0
16kernel=
17load_addr_mask=1099511627775
18mem_mode=timing
19mem_ranges=
20memories=system.physmem
21num_work_ids=16
22readfile=
23symbolfile=
24work_begin_ckpt_count=0
25work_begin_cpu_id_exit=-1
26work_begin_exit_count=0
27work_cpus_ckpt_count=0
28work_end_ckpt_count=0
29work_end_exit_count=0
30work_item_id=-1
31system_port=system.membus.slave[0]
32
33[system.clk_domain]
34type=SrcClockDomain
35clock=1000
36voltage_domain=system.voltage_domain
37
38[system.cpu]
39type=DerivO3CPU
40children=branchPred dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload
41LFSTSize=1024
42LQEntries=32
43LSQCheckLoads=true
44LSQDepCheckShift=4
45SQEntries=32
46SSITSize=1024
47activity=0
48backComSize=5
49branchPred=system.cpu.branchPred
50cachePorts=200
51checker=Null
52clk_domain=system.cpu_clk_domain
53commitToDecodeDelay=1
54commitToFetchDelay=1
55commitToIEWDelay=1
56commitToRenameDelay=1
57commitWidth=8
58cpu_id=0
59decodeToFetchDelay=1
60decodeToRenameDelay=1
61decodeWidth=8
62dispatchWidth=8
63do_checkpoint_insts=true
64do_quiesce=true
65do_statistics_insts=true
66dtb=system.cpu.dtb
67fetchToDecodeDelay=1
68fetchTrapLatency=1
69fetchWidth=8
70forwardComSize=5
71fuPool=system.cpu.fuPool
72function_trace=false
73function_trace_start=0
74iewToCommitDelay=1
75iewToDecodeDelay=1
76iewToFetchDelay=1
77iewToRenameDelay=1
78interrupts=system.cpu.interrupts
79isa=system.cpu.isa
80issueToExecuteDelay=1
81issueWidth=8
82itb=system.cpu.itb
83max_insts_all_threads=0
84max_insts_any_thread=0
85max_loads_all_threads=0
86max_loads_any_thread=0
87needsTSO=false
88numIQEntries=64
89numPhysCCRegs=0
90numPhysFloatRegs=256
91numPhysIntRegs=256
92numROBEntries=192
93numRobs=1
94numThreads=1
95profile=0
96progress_interval=0
97renameToDecodeDelay=1
98renameToFetchDelay=1
99renameToIEWDelay=2
100renameToROBDelay=1
101renameWidth=8
102simpoint_start_insts=
103smtCommitPolicy=RoundRobin
104smtFetchPolicy=SingleThread
105smtIQPolicy=Partitioned
106smtIQThreshold=100
107smtLSQPolicy=Partitioned
108smtLSQThreshold=100
109smtNumFetchingThreads=1
110smtROBPolicy=Partitioned
111smtROBThreshold=100
112squashWidth=8
113store_set_clear_period=250000
114switched_out=false
115system=system
116tracer=system.cpu.tracer
117trapLatency=13
118wbDepth=1
119wbWidth=8
120workload=system.cpu.workload
121dcache_port=system.cpu.dcache.cpu_side
122icache_port=system.cpu.icache.cpu_side
123
124[system.cpu.branchPred]
125type=BranchPredictor
126BTBEntries=4096
127BTBTagSize=16
128RASSize=16
129choiceCtrBits=2
130choicePredictorSize=8192
131globalCtrBits=2
132globalPredictorSize=8192
133instShiftAmt=2
134localCtrBits=2
135localHistoryTableSize=2048
136localPredictorSize=2048
137numThreads=1
138predType=tournament
139
140[system.cpu.dcache]
141type=BaseCache
142children=tags
143addr_ranges=0:18446744073709551615
144assoc=2
145clk_domain=system.cpu_clk_domain
146forward_snoops=true
147hit_latency=2
148is_top_level=true
149max_miss_count=0
150mshrs=4
151prefetch_on_access=false
152prefetcher=Null
153response_latency=2
154size=262144
155system=system
156tags=system.cpu.dcache.tags
157tgts_per_mshr=20
158two_queue=false
159write_buffers=8
160cpu_side=system.cpu.dcache_port
161mem_side=system.cpu.toL2Bus.slave[1]
162
163[system.cpu.dcache.tags]
164type=LRU
165assoc=2
166block_size=64
167clk_domain=system.cpu_clk_domain
168hit_latency=2
169size=262144
170
171[system.cpu.dtb]
172type=MipsTLB
173size=64
174
175[system.cpu.fuPool]
176type=FUPool
177children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8
178FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8
179
180[system.cpu.fuPool.FUList0]
181type=FUDesc
182children=opList
183count=6
184opList=system.cpu.fuPool.FUList0.opList
185
186[system.cpu.fuPool.FUList0.opList]
187type=OpDesc
188issueLat=1
189opClass=IntAlu
190opLat=1
191
192[system.cpu.fuPool.FUList1]
193type=FUDesc
194children=opList0 opList1
195count=2
196opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1
197
198[system.cpu.fuPool.FUList1.opList0]
199type=OpDesc
200issueLat=1
201opClass=IntMult
202opLat=3
203
204[system.cpu.fuPool.FUList1.opList1]
205type=OpDesc
206issueLat=19
207opClass=IntDiv
208opLat=20
209
210[system.cpu.fuPool.FUList2]
211type=FUDesc
212children=opList0 opList1 opList2
213count=4
214opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2
215
216[system.cpu.fuPool.FUList2.opList0]
217type=OpDesc
218issueLat=1
219opClass=FloatAdd
220opLat=2
221
222[system.cpu.fuPool.FUList2.opList1]
223type=OpDesc
224issueLat=1
225opClass=FloatCmp
226opLat=2
227
228[system.cpu.fuPool.FUList2.opList2]
229type=OpDesc
230issueLat=1
231opClass=FloatCvt
232opLat=2
233
234[system.cpu.fuPool.FUList3]
235type=FUDesc
236children=opList0 opList1 opList2
237count=2
238opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2
239
240[system.cpu.fuPool.FUList3.opList0]
241type=OpDesc
242issueLat=1
243opClass=FloatMult
244opLat=4
245
246[system.cpu.fuPool.FUList3.opList1]
247type=OpDesc
248issueLat=12
249opClass=FloatDiv
250opLat=12
251
252[system.cpu.fuPool.FUList3.opList2]
253type=OpDesc
254issueLat=24
255opClass=FloatSqrt
256opLat=24
257
258[system.cpu.fuPool.FUList4]
259type=FUDesc
260children=opList
261count=0
262opList=system.cpu.fuPool.FUList4.opList
263
264[system.cpu.fuPool.FUList4.opList]
265type=OpDesc
266issueLat=1
267opClass=MemRead
268opLat=1
269
270[system.cpu.fuPool.FUList5]
271type=FUDesc
272children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19
273count=4
274opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19
275
276[system.cpu.fuPool.FUList5.opList00]
277type=OpDesc
278issueLat=1
279opClass=SimdAdd
280opLat=1
281
282[system.cpu.fuPool.FUList5.opList01]
283type=OpDesc
284issueLat=1
285opClass=SimdAddAcc
286opLat=1
287
288[system.cpu.fuPool.FUList5.opList02]
289type=OpDesc
290issueLat=1
291opClass=SimdAlu
292opLat=1
293
294[system.cpu.fuPool.FUList5.opList03]
295type=OpDesc
296issueLat=1
297opClass=SimdCmp
298opLat=1
299
300[system.cpu.fuPool.FUList5.opList04]
301type=OpDesc
302issueLat=1
303opClass=SimdCvt
304opLat=1
305
306[system.cpu.fuPool.FUList5.opList05]
307type=OpDesc
308issueLat=1
309opClass=SimdMisc
310opLat=1
311
312[system.cpu.fuPool.FUList5.opList06]
313type=OpDesc
314issueLat=1
315opClass=SimdMult
316opLat=1
317
318[system.cpu.fuPool.FUList5.opList07]
319type=OpDesc
320issueLat=1
321opClass=SimdMultAcc
322opLat=1
323
324[system.cpu.fuPool.FUList5.opList08]
325type=OpDesc
326issueLat=1
327opClass=SimdShift
328opLat=1
329
330[system.cpu.fuPool.FUList5.opList09]
331type=OpDesc
332issueLat=1
333opClass=SimdShiftAcc
334opLat=1
335
336[system.cpu.fuPool.FUList5.opList10]
337type=OpDesc
338issueLat=1
339opClass=SimdSqrt
340opLat=1
341
342[system.cpu.fuPool.FUList5.opList11]
343type=OpDesc
344issueLat=1
345opClass=SimdFloatAdd
346opLat=1
347
348[system.cpu.fuPool.FUList5.opList12]
349type=OpDesc
350issueLat=1
351opClass=SimdFloatAlu
352opLat=1
353
354[system.cpu.fuPool.FUList5.opList13]
355type=OpDesc
356issueLat=1
357opClass=SimdFloatCmp
358opLat=1
359
360[system.cpu.fuPool.FUList5.opList14]
361type=OpDesc
362issueLat=1
363opClass=SimdFloatCvt
364opLat=1
365
366[system.cpu.fuPool.FUList5.opList15]
367type=OpDesc
368issueLat=1
369opClass=SimdFloatDiv
370opLat=1
371
372[system.cpu.fuPool.FUList5.opList16]
373type=OpDesc
374issueLat=1
375opClass=SimdFloatMisc
376opLat=1
377
378[system.cpu.fuPool.FUList5.opList17]
379type=OpDesc
380issueLat=1
381opClass=SimdFloatMult
382opLat=1
383
384[system.cpu.fuPool.FUList5.opList18]
385type=OpDesc
386issueLat=1
387opClass=SimdFloatMultAcc
388opLat=1
389
390[system.cpu.fuPool.FUList5.opList19]
391type=OpDesc
392issueLat=1
393opClass=SimdFloatSqrt
394opLat=1
395
396[system.cpu.fuPool.FUList6]
397type=FUDesc
398children=opList
399count=0
400opList=system.cpu.fuPool.FUList6.opList
401
402[system.cpu.fuPool.FUList6.opList]
403type=OpDesc
404issueLat=1
405opClass=MemWrite
406opLat=1
407
408[system.cpu.fuPool.FUList7]
409type=FUDesc
410children=opList0 opList1
411count=4
412opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1
413
414[system.cpu.fuPool.FUList7.opList0]
415type=OpDesc
416issueLat=1
417opClass=MemRead
418opLat=1
419
420[system.cpu.fuPool.FUList7.opList1]
421type=OpDesc
422issueLat=1
423opClass=MemWrite
424opLat=1
425
426[system.cpu.fuPool.FUList8]
427type=FUDesc
428children=opList
429count=1
430opList=system.cpu.fuPool.FUList8.opList
431
432[system.cpu.fuPool.FUList8.opList]
433type=OpDesc
434issueLat=3
435opClass=IprAccess
436opLat=3
437
438[system.cpu.icache]
439type=BaseCache
440children=tags
441addr_ranges=0:18446744073709551615
442assoc=2
443clk_domain=system.cpu_clk_domain
444forward_snoops=true
445hit_latency=2
446is_top_level=true
447max_miss_count=0
448mshrs=4
449prefetch_on_access=false
450prefetcher=Null
451response_latency=2
452size=131072
453system=system
454tags=system.cpu.icache.tags
455tgts_per_mshr=20
456two_queue=false
457write_buffers=8
458cpu_side=system.cpu.icache_port
459mem_side=system.cpu.toL2Bus.slave[0]
460
461[system.cpu.icache.tags]
462type=LRU
463assoc=2
464block_size=64
465clk_domain=system.cpu_clk_domain
466hit_latency=2
467size=131072
468
469[system.cpu.interrupts]
470type=MipsInterrupts
471
472[system.cpu.isa]
473type=MipsISA
474num_threads=1
475num_vpes=1
476
477[system.cpu.itb]
478type=MipsTLB
479size=64
480
481[system.cpu.l2cache]
482type=BaseCache
483children=tags
484addr_ranges=0:18446744073709551615
485assoc=8
486clk_domain=system.cpu_clk_domain
487forward_snoops=true
488hit_latency=20
489is_top_level=false
490max_miss_count=0
491mshrs=20
492prefetch_on_access=false
493prefetcher=Null
494response_latency=20
495size=2097152
496system=system
497tags=system.cpu.l2cache.tags
498tgts_per_mshr=12
499two_queue=false
500write_buffers=8
501cpu_side=system.cpu.toL2Bus.master[0]
502mem_side=system.membus.slave[1]
503
504[system.cpu.l2cache.tags]
505type=LRU
506assoc=8
507block_size=64
508clk_domain=system.cpu_clk_domain
509hit_latency=20
510size=2097152
511
512[system.cpu.toL2Bus]
513type=CoherentBus
514clk_domain=system.cpu_clk_domain
515header_cycles=1
516system=system
517use_default_range=false
518width=32
519master=system.cpu.l2cache.cpu_side
520slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
521
522[system.cpu.tracer]
523type=ExeTracer
524
525[system.cpu.workload]
526type=LiveProcess
527cmd=hello
528cwd=
529egid=100
530env=
531errout=cerr
532euid=100
533executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello
534gid=100
535input=cin
536max_stack_size=67108864
537output=cout
538pid=100
539ppid=99
540simpoint=0
541system=system
542uid=100
543
544[system.cpu_clk_domain]
545type=SrcClockDomain
546clock=500
547voltage_domain=system.voltage_domain
548
549[system.membus]
550type=CoherentBus
551clk_domain=system.clk_domain
552header_cycles=1
553system=system
554use_default_range=false
555width=8
556master=system.physmem.port
557slave=system.system_port system.cpu.l2cache.mem_side
558
559[system.physmem]
560type=SimpleDRAM
561activation_limit=4
562addr_mapping=RaBaChCo
563banks_per_rank=8
564burst_length=8
565channels=1
566clk_domain=system.clk_domain
567conf_table_reported=true
568device_bus_width=8
569device_rowbuffer_size=1024
570devices_per_rank=8
571in_addr_map=true
572mem_sched_policy=frfcfs
573null=false
574page_policy=open
575range=0:134217727
576ranks_per_channel=2
577read_buffer_size=32
578static_backend_latency=10000
579static_frontend_latency=10000
580tBURST=5000
581tCL=13750
582tRCD=13750
583tREFI=7800000
584tRFC=300000
585tRP=13750
586tWTR=7500
587tXAW=40000
588write_buffer_size=32
589write_thresh_perc=70
590port=system.membus.master[0]
591
592[system.voltage_domain]
593type=VoltageDomain
594voltage=1.000000
595