1[root] 2type=Root 3children=system 4eventq_index=0 5full_system=false 6sim_quantum=0 7time_sync_enable=false 8time_sync_period=100000000000 --- 159 unchanged lines hidden (view full) --- 168localHistoryTableSize=2048 169localPredictorSize=2048 170numThreads=1 171useIndirect=true 172 173[system.cpu.dcache] 174type=Cache 175children=tags |
176addr_ranges=0:18446744073709551615:0:0:0:0 |
177assoc=2 178clk_domain=system.cpu_clk_domain 179clusivity=mostly_incl 180default_p_state=UNDEFINED 181demand_mshr_reserve=1 182eventq_index=0 183hit_latency=2 184is_read_only=false --- 341 unchanged lines hidden (view full) --- 526eventq_index=0 527opClass=IprAccess 528opLat=3 529pipelined=false 530 531[system.cpu.icache] 532type=Cache 533children=tags |
534addr_ranges=0:18446744073709551615:0:0:0:0 |
535assoc=2 536clk_domain=system.cpu_clk_domain 537clusivity=mostly_incl 538default_p_state=UNDEFINED 539demand_mshr_reserve=1 540eventq_index=0 541hit_latency=2 542is_read_only=true --- 45 unchanged lines hidden (view full) --- 588[system.cpu.itb] 589type=MipsTLB 590eventq_index=0 591size=64 592 593[system.cpu.l2cache] 594type=Cache 595children=tags |
596addr_ranges=0:18446744073709551615:0:0:0:0 |
597assoc=8 598clk_domain=system.cpu_clk_domain 599clusivity=mostly_incl 600default_p_state=UNDEFINED 601demand_mshr_reserve=1 602eventq_index=0 603hit_latency=20 604is_read_only=false --- 100 unchanged lines hidden (view full) --- 705domains= 706enable=false 707eventq_index=0 708sys_clk_domain=system.clk_domain 709transition_latency=100000000 710 711[system.membus] 712type=CoherentXBar |
713children=snoop_filter |
714clk_domain=system.clk_domain 715default_p_state=UNDEFINED 716eventq_index=0 717forward_latency=4 718frontend_latency=3 719p_state_clk_gate_bins=20 720p_state_clk_gate_max=1000000000000 721p_state_clk_gate_min=1000 722point_of_coherency=true 723power_model=Null 724response_latency=2 |
725snoop_filter=system.membus.snoop_filter |
726snoop_response_latency=4 727system=system 728use_default_range=false 729width=16 730master=system.physmem.port 731slave=system.system_port system.cpu.l2cache.mem_side 732 |
733[system.membus.snoop_filter] 734type=SnoopFilter 735eventq_index=0 736lookup_latency=1 737max_capacity=8388608 738system=system 739 |
740[system.physmem] 741type=DRAMCtrl |
742IDD0=0.055000 |
743IDD02=0.000000 |
744IDD2N=0.032000 |
745IDD2N2=0.000000 746IDD2P0=0.000000 747IDD2P02=0.000000 |
748IDD2P1=0.032000 |
749IDD2P12=0.000000 |
750IDD3N=0.038000 |
751IDD3N2=0.000000 752IDD3P0=0.000000 753IDD3P02=0.000000 |
754IDD3P1=0.038000 |
755IDD3P12=0.000000 |
756IDD4R=0.157000 |
757IDD4R2=0.000000 |
758IDD4W=0.125000 |
759IDD4W2=0.000000 |
760IDD5=0.235000 |
761IDD52=0.000000 |
762IDD6=0.020000 |
763IDD62=0.000000 764VDD=1.500000 765VDD2=0.000000 766activation_limit=4 767addr_mapping=RoRaBaCoCh 768bank_groups_per_rank=0 769banks_per_rank=8 770burst_length=8 771channels=1 772clk_domain=system.clk_domain 773conf_table_reported=true 774default_p_state=UNDEFINED 775device_bus_width=8 776device_rowbuffer_size=1024 777device_size=536870912 778devices_per_rank=8 779dll=true 780eventq_index=0 781in_addr_map=true |
782kvm_map=true |
783max_accesses_per_row=16 784mem_sched_policy=frfcfs 785min_writes_per_switch=16 786null=false 787p_state_clk_gate_bins=20 788p_state_clk_gate_max=1000000000000 789p_state_clk_gate_min=1000 790page_policy=open_adaptive 791power_model=Null |
792range=0:134217727:0:0:0:0 |
793ranks_per_channel=2 794read_buffer_size=32 795static_backend_latency=10000 796static_frontend_latency=10000 797tBURST=5000 798tCCD_L=0 799tCK=1250 800tCL=13750 --- 5 unchanged lines hidden (view full) --- 806tRP=13750 807tRRD=6000 808tRRD_L=0 809tRTP=7500 810tRTW=2500 811tWR=15000 812tWTR=7500 813tXAW=30000 |
814tXP=6000 |
815tXPDLL=0 |
816tXS=270000 |
817tXSDLL=0 818write_buffer_size=64 819write_high_thresh_perc=85 820write_low_thresh_perc=50 821port=system.membus.master[0] 822 823[system.voltage_domain] 824type=VoltageDomain 825eventq_index=0 826voltage=1.000000 827 |