Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

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config.ini (9348:44d31345e360)	config.ini (9449:56610ab73040)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13clock=1000 14init_param=0 15kernel= 16load_addr_mask=1099511627775
17mem_mode=atomic	17mem_mode=timing 18mem_ranges=
18memories=system.physmem 19num_work_ids=16 20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1 29system_port=system.membus.slave[0] 30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8	19memories=system.physmem 20num_work_ids=16 21readfile= 22symbolfile= 23work_begin_ckpt_count=0 24work_begin_cpu_id_exit=-1 25work_begin_exit_count=0 26work_cpus_ckpt_count=0 27work_end_ckpt_count=0 28work_end_exit_count=0 29work_item_id=-1 30system_port=system.membus.slave[0] 31 32[system.cpu] 33type=DerivO3CPU 34children=dcache dtb fuPool icache interrupts isa itb l2cache toL2Bus tracer workload 35BTBEntries=4096 36BTBTagSize=16 37LFSTSize=1024 38LQEntries=32 39LSQCheckLoads=true 40LSQDepCheckShift=4 41RASSize=16 42SQEntries=32 43SSITSize=1024 44activity=0 45backComSize=5 46cachePorts=200 47checker=Null 48choiceCtrBits=2 49choicePredictorSize=8192 50clock=500 51commitToDecodeDelay=1 52commitToFetchDelay=1 53commitToIEWDelay=1 54commitToRenameDelay=1 55commitWidth=8 56cpu_id=0 57decodeToFetchDelay=1 58decodeToRenameDelay=1 59decodeWidth=8
59defer_registration=false
60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81isa=system.cpu.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000	60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81isa=system.cpu.isa 82issueToExecuteDelay=1 83issueWidth=8 84itb=system.cpu.itb 85localCtrBits=2 86localHistoryBits=11 87localHistoryTableSize=2048 88localPredictorSize=2048 89max_insts_all_threads=0 90max_insts_any_thread=0 91max_loads_all_threads=0 92max_loads_any_thread=0 93needsTSO=false 94numIQEntries=64 95numPhysFloatRegs=256 96numPhysIntRegs=256 97numROBEntries=192 98numRobs=1 99numThreads=1 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000
	119switched_out=false
119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache 130addr_ranges=0:18446744073709551615 131assoc=2 132block_size=64 133clock=500 134forward_snoops=true	120system=system 121tracer=system.cpu.tracer 122trapLatency=13 123wbDepth=1 124wbWidth=8 125workload=system.cpu.workload 126dcache_port=system.cpu.dcache.cpu_side 127icache_port=system.cpu.icache.cpu_side 128 129[system.cpu.dcache] 130type=BaseCache 131addr_ranges=0:18446744073709551615 132assoc=2 133block_size=64 134clock=500 135forward_snoops=true
135hash_delay=1
136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null	136hit_latency=2 137is_top_level=true 138max_miss_count=0 139mshrs=4 140prefetch_on_access=false 141prefetcher=Null
142prioritizeRequests=false 143repl=Null
144response_latency=2 145size=262144	142response_latency=2 143size=262144
146subblock_size=0
147system=system 148tgts_per_mshr=20	144system=system 145tgts_per_mshr=20
149trace_addr=0
150two_queue=false 151write_buffers=8 152cpu_side=system.cpu.dcache_port 153mem_side=system.cpu.toL2Bus.slave[1] 154 155[system.cpu.dtb] 156type=MipsTLB 157size=64 158 159[system.cpu.fuPool] 160type=FUPool 161children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 162FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 163 164[system.cpu.fuPool.FUList0] 165type=FUDesc 166children=opList 167count=6 168opList=system.cpu.fuPool.FUList0.opList 169 170[system.cpu.fuPool.FUList0.opList] 171type=OpDesc 172issueLat=1 173opClass=IntAlu 174opLat=1 175 176[system.cpu.fuPool.FUList1] 177type=FUDesc 178children=opList0 opList1 179count=2 180opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 181 182[system.cpu.fuPool.FUList1.opList0] 183type=OpDesc 184issueLat=1 185opClass=IntMult 186opLat=3 187 188[system.cpu.fuPool.FUList1.opList1] 189type=OpDesc 190issueLat=19 191opClass=IntDiv 192opLat=20 193 194[system.cpu.fuPool.FUList2] 195type=FUDesc 196children=opList0 opList1 opList2 197count=4 198opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 199 200[system.cpu.fuPool.FUList2.opList0] 201type=OpDesc 202issueLat=1 203opClass=FloatAdd 204opLat=2 205 206[system.cpu.fuPool.FUList2.opList1] 207type=OpDesc 208issueLat=1 209opClass=FloatCmp 210opLat=2 211 212[system.cpu.fuPool.FUList2.opList2] 213type=OpDesc 214issueLat=1 215opClass=FloatCvt 216opLat=2 217 218[system.cpu.fuPool.FUList3] 219type=FUDesc 220children=opList0 opList1 opList2 221count=2 222opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 223 224[system.cpu.fuPool.FUList3.opList0] 225type=OpDesc 226issueLat=1 227opClass=FloatMult 228opLat=4 229 230[system.cpu.fuPool.FUList3.opList1] 231type=OpDesc 232issueLat=12 233opClass=FloatDiv 234opLat=12 235 236[system.cpu.fuPool.FUList3.opList2] 237type=OpDesc 238issueLat=24 239opClass=FloatSqrt 240opLat=24 241 242[system.cpu.fuPool.FUList4] 243type=FUDesc 244children=opList 245count=0 246opList=system.cpu.fuPool.FUList4.opList 247 248[system.cpu.fuPool.FUList4.opList] 249type=OpDesc 250issueLat=1 251opClass=MemRead 252opLat=1 253 254[system.cpu.fuPool.FUList5] 255type=FUDesc 256children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 257count=4 258opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 259 260[system.cpu.fuPool.FUList5.opList00] 261type=OpDesc 262issueLat=1 263opClass=SimdAdd 264opLat=1 265 266[system.cpu.fuPool.FUList5.opList01] 267type=OpDesc 268issueLat=1 269opClass=SimdAddAcc 270opLat=1 271 272[system.cpu.fuPool.FUList5.opList02] 273type=OpDesc 274issueLat=1 275opClass=SimdAlu 276opLat=1 277 278[system.cpu.fuPool.FUList5.opList03] 279type=OpDesc 280issueLat=1 281opClass=SimdCmp 282opLat=1 283 284[system.cpu.fuPool.FUList5.opList04] 285type=OpDesc 286issueLat=1 287opClass=SimdCvt 288opLat=1 289 290[system.cpu.fuPool.FUList5.opList05] 291type=OpDesc 292issueLat=1 293opClass=SimdMisc 294opLat=1 295 296[system.cpu.fuPool.FUList5.opList06] 297type=OpDesc 298issueLat=1 299opClass=SimdMult 300opLat=1 301 302[system.cpu.fuPool.FUList5.opList07] 303type=OpDesc 304issueLat=1 305opClass=SimdMultAcc 306opLat=1 307 308[system.cpu.fuPool.FUList5.opList08] 309type=OpDesc 310issueLat=1 311opClass=SimdShift 312opLat=1 313 314[system.cpu.fuPool.FUList5.opList09] 315type=OpDesc 316issueLat=1 317opClass=SimdShiftAcc 318opLat=1 319 320[system.cpu.fuPool.FUList5.opList10] 321type=OpDesc 322issueLat=1 323opClass=SimdSqrt 324opLat=1 325 326[system.cpu.fuPool.FUList5.opList11] 327type=OpDesc 328issueLat=1 329opClass=SimdFloatAdd 330opLat=1 331 332[system.cpu.fuPool.FUList5.opList12] 333type=OpDesc 334issueLat=1 335opClass=SimdFloatAlu 336opLat=1 337 338[system.cpu.fuPool.FUList5.opList13] 339type=OpDesc 340issueLat=1 341opClass=SimdFloatCmp 342opLat=1 343 344[system.cpu.fuPool.FUList5.opList14] 345type=OpDesc 346issueLat=1 347opClass=SimdFloatCvt 348opLat=1 349 350[system.cpu.fuPool.FUList5.opList15] 351type=OpDesc 352issueLat=1 353opClass=SimdFloatDiv 354opLat=1 355 356[system.cpu.fuPool.FUList5.opList16] 357type=OpDesc 358issueLat=1 359opClass=SimdFloatMisc 360opLat=1 361 362[system.cpu.fuPool.FUList5.opList17] 363type=OpDesc 364issueLat=1 365opClass=SimdFloatMult 366opLat=1 367 368[system.cpu.fuPool.FUList5.opList18] 369type=OpDesc 370issueLat=1 371opClass=SimdFloatMultAcc 372opLat=1 373 374[system.cpu.fuPool.FUList5.opList19] 375type=OpDesc 376issueLat=1 377opClass=SimdFloatSqrt 378opLat=1 379 380[system.cpu.fuPool.FUList6] 381type=FUDesc 382children=opList 383count=0 384opList=system.cpu.fuPool.FUList6.opList 385 386[system.cpu.fuPool.FUList6.opList] 387type=OpDesc 388issueLat=1 389opClass=MemWrite 390opLat=1 391 392[system.cpu.fuPool.FUList7] 393type=FUDesc 394children=opList0 opList1 395count=4 396opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 397 398[system.cpu.fuPool.FUList7.opList0] 399type=OpDesc 400issueLat=1 401opClass=MemRead 402opLat=1 403 404[system.cpu.fuPool.FUList7.opList1] 405type=OpDesc 406issueLat=1 407opClass=MemWrite 408opLat=1 409 410[system.cpu.fuPool.FUList8] 411type=FUDesc 412children=opList 413count=1 414opList=system.cpu.fuPool.FUList8.opList 415 416[system.cpu.fuPool.FUList8.opList] 417type=OpDesc 418issueLat=3 419opClass=IprAccess 420opLat=3 421 422[system.cpu.icache] 423type=BaseCache 424addr_ranges=0:18446744073709551615 425assoc=2 426block_size=64 427clock=500 428forward_snoops=true	146two_queue=false 147write_buffers=8 148cpu_side=system.cpu.dcache_port 149mem_side=system.cpu.toL2Bus.slave[1] 150 151[system.cpu.dtb] 152type=MipsTLB 153size=64 154 155[system.cpu.fuPool] 156type=FUPool 157children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 158FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 159 160[system.cpu.fuPool.FUList0] 161type=FUDesc 162children=opList 163count=6 164opList=system.cpu.fuPool.FUList0.opList 165 166[system.cpu.fuPool.FUList0.opList] 167type=OpDesc 168issueLat=1 169opClass=IntAlu 170opLat=1 171 172[system.cpu.fuPool.FUList1] 173type=FUDesc 174children=opList0 opList1 175count=2 176opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 177 178[system.cpu.fuPool.FUList1.opList0] 179type=OpDesc 180issueLat=1 181opClass=IntMult 182opLat=3 183 184[system.cpu.fuPool.FUList1.opList1] 185type=OpDesc 186issueLat=19 187opClass=IntDiv 188opLat=20 189 190[system.cpu.fuPool.FUList2] 191type=FUDesc 192children=opList0 opList1 opList2 193count=4 194opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 195 196[system.cpu.fuPool.FUList2.opList0] 197type=OpDesc 198issueLat=1 199opClass=FloatAdd 200opLat=2 201 202[system.cpu.fuPool.FUList2.opList1] 203type=OpDesc 204issueLat=1 205opClass=FloatCmp 206opLat=2 207 208[system.cpu.fuPool.FUList2.opList2] 209type=OpDesc 210issueLat=1 211opClass=FloatCvt 212opLat=2 213 214[system.cpu.fuPool.FUList3] 215type=FUDesc 216children=opList0 opList1 opList2 217count=2 218opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 219 220[system.cpu.fuPool.FUList3.opList0] 221type=OpDesc 222issueLat=1 223opClass=FloatMult 224opLat=4 225 226[system.cpu.fuPool.FUList3.opList1] 227type=OpDesc 228issueLat=12 229opClass=FloatDiv 230opLat=12 231 232[system.cpu.fuPool.FUList3.opList2] 233type=OpDesc 234issueLat=24 235opClass=FloatSqrt 236opLat=24 237 238[system.cpu.fuPool.FUList4] 239type=FUDesc 240children=opList 241count=0 242opList=system.cpu.fuPool.FUList4.opList 243 244[system.cpu.fuPool.FUList4.opList] 245type=OpDesc 246issueLat=1 247opClass=MemRead 248opLat=1 249 250[system.cpu.fuPool.FUList5] 251type=FUDesc 252children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 253count=4 254opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 255 256[system.cpu.fuPool.FUList5.opList00] 257type=OpDesc 258issueLat=1 259opClass=SimdAdd 260opLat=1 261 262[system.cpu.fuPool.FUList5.opList01] 263type=OpDesc 264issueLat=1 265opClass=SimdAddAcc 266opLat=1 267 268[system.cpu.fuPool.FUList5.opList02] 269type=OpDesc 270issueLat=1 271opClass=SimdAlu 272opLat=1 273 274[system.cpu.fuPool.FUList5.opList03] 275type=OpDesc 276issueLat=1 277opClass=SimdCmp 278opLat=1 279 280[system.cpu.fuPool.FUList5.opList04] 281type=OpDesc 282issueLat=1 283opClass=SimdCvt 284opLat=1 285 286[system.cpu.fuPool.FUList5.opList05] 287type=OpDesc 288issueLat=1 289opClass=SimdMisc 290opLat=1 291 292[system.cpu.fuPool.FUList5.opList06] 293type=OpDesc 294issueLat=1 295opClass=SimdMult 296opLat=1 297 298[system.cpu.fuPool.FUList5.opList07] 299type=OpDesc 300issueLat=1 301opClass=SimdMultAcc 302opLat=1 303 304[system.cpu.fuPool.FUList5.opList08] 305type=OpDesc 306issueLat=1 307opClass=SimdShift 308opLat=1 309 310[system.cpu.fuPool.FUList5.opList09] 311type=OpDesc 312issueLat=1 313opClass=SimdShiftAcc 314opLat=1 315 316[system.cpu.fuPool.FUList5.opList10] 317type=OpDesc 318issueLat=1 319opClass=SimdSqrt 320opLat=1 321 322[system.cpu.fuPool.FUList5.opList11] 323type=OpDesc 324issueLat=1 325opClass=SimdFloatAdd 326opLat=1 327 328[system.cpu.fuPool.FUList5.opList12] 329type=OpDesc 330issueLat=1 331opClass=SimdFloatAlu 332opLat=1 333 334[system.cpu.fuPool.FUList5.opList13] 335type=OpDesc 336issueLat=1 337opClass=SimdFloatCmp 338opLat=1 339 340[system.cpu.fuPool.FUList5.opList14] 341type=OpDesc 342issueLat=1 343opClass=SimdFloatCvt 344opLat=1 345 346[system.cpu.fuPool.FUList5.opList15] 347type=OpDesc 348issueLat=1 349opClass=SimdFloatDiv 350opLat=1 351 352[system.cpu.fuPool.FUList5.opList16] 353type=OpDesc 354issueLat=1 355opClass=SimdFloatMisc 356opLat=1 357 358[system.cpu.fuPool.FUList5.opList17] 359type=OpDesc 360issueLat=1 361opClass=SimdFloatMult 362opLat=1 363 364[system.cpu.fuPool.FUList5.opList18] 365type=OpDesc 366issueLat=1 367opClass=SimdFloatMultAcc 368opLat=1 369 370[system.cpu.fuPool.FUList5.opList19] 371type=OpDesc 372issueLat=1 373opClass=SimdFloatSqrt 374opLat=1 375 376[system.cpu.fuPool.FUList6] 377type=FUDesc 378children=opList 379count=0 380opList=system.cpu.fuPool.FUList6.opList 381 382[system.cpu.fuPool.FUList6.opList] 383type=OpDesc 384issueLat=1 385opClass=MemWrite 386opLat=1 387 388[system.cpu.fuPool.FUList7] 389type=FUDesc 390children=opList0 opList1 391count=4 392opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 393 394[system.cpu.fuPool.FUList7.opList0] 395type=OpDesc 396issueLat=1 397opClass=MemRead 398opLat=1 399 400[system.cpu.fuPool.FUList7.opList1] 401type=OpDesc 402issueLat=1 403opClass=MemWrite 404opLat=1 405 406[system.cpu.fuPool.FUList8] 407type=FUDesc 408children=opList 409count=1 410opList=system.cpu.fuPool.FUList8.opList 411 412[system.cpu.fuPool.FUList8.opList] 413type=OpDesc 414issueLat=3 415opClass=IprAccess 416opLat=3 417 418[system.cpu.icache] 419type=BaseCache 420addr_ranges=0:18446744073709551615 421assoc=2 422block_size=64 423clock=500 424forward_snoops=true
429hash_delay=1
430hit_latency=2 431is_top_level=true 432max_miss_count=0 433mshrs=4 434prefetch_on_access=false 435prefetcher=Null	425hit_latency=2 426is_top_level=true 427max_miss_count=0 428mshrs=4 429prefetch_on_access=false 430prefetcher=Null
436prioritizeRequests=false 437repl=Null
438response_latency=2 439size=131072	431response_latency=2 432size=131072
440subblock_size=0
441system=system 442tgts_per_mshr=20	433system=system 434tgts_per_mshr=20
443trace_addr=0
444two_queue=false 445write_buffers=8 446cpu_side=system.cpu.icache_port 447mem_side=system.cpu.toL2Bus.slave[0] 448 449[system.cpu.interrupts] 450type=MipsInterrupts 451 452[system.cpu.isa] 453type=MipsISA 454num_threads=1 455num_vpes=1 456 457[system.cpu.itb] 458type=MipsTLB 459size=64 460 461[system.cpu.l2cache] 462type=BaseCache 463addr_ranges=0:18446744073709551615 464assoc=8 465block_size=64 466clock=500 467forward_snoops=true	435two_queue=false 436write_buffers=8 437cpu_side=system.cpu.icache_port 438mem_side=system.cpu.toL2Bus.slave[0] 439 440[system.cpu.interrupts] 441type=MipsInterrupts 442 443[system.cpu.isa] 444type=MipsISA 445num_threads=1 446num_vpes=1 447 448[system.cpu.itb] 449type=MipsTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache 454addr_ranges=0:18446744073709551615 455assoc=8 456block_size=64 457clock=500 458forward_snoops=true
468hash_delay=1
469hit_latency=20 470is_top_level=false 471max_miss_count=0 472mshrs=20 473prefetch_on_access=false 474prefetcher=Null	459hit_latency=20 460is_top_level=false 461max_miss_count=0 462mshrs=20 463prefetch_on_access=false 464prefetcher=Null
475prioritizeRequests=false 476repl=Null
477response_latency=20 478size=2097152	465response_latency=20 466size=2097152
479subblock_size=0
480system=system 481tgts_per_mshr=12	467system=system 468tgts_per_mshr=12
482trace_addr=0
483two_queue=false 484write_buffers=8 485cpu_side=system.cpu.toL2Bus.master[0] 486mem_side=system.membus.slave[1] 487 488[system.cpu.toL2Bus] 489type=CoherentBus 490block_size=64 491clock=500 492header_cycles=1 493use_default_range=false 494width=32 495master=system.cpu.l2cache.cpu_side 496slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 497 498[system.cpu.tracer] 499type=ExeTracer 500 501[system.cpu.workload] 502type=LiveProcess 503cmd=hello 504cwd= 505egid=100 506env= 507errout=cerr 508euid=100	469two_queue=false 470write_buffers=8 471cpu_side=system.cpu.toL2Bus.master[0] 472mem_side=system.membus.slave[1] 473 474[system.cpu.toL2Bus] 475type=CoherentBus 476block_size=64 477clock=500 478header_cycles=1 479use_default_range=false 480width=32 481master=system.cpu.l2cache.cpu_side 482slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side 483 484[system.cpu.tracer] 485type=ExeTracer 486 487[system.cpu.workload] 488type=LiveProcess 489cmd=hello 490cwd= 491egid=100 492env= 493errout=cerr 494euid=100
509executable=/projects/pd/randd/dist/test-progs/hello/bin/mips/linux/hello	495executable=/gem5/dist/test-progs/hello/bin/mips/linux/hello
510gid=100 511input=cin 512max_stack_size=67108864 513output=cout 514pid=100 515ppid=99 516simpoint=0 517system=system 518uid=100 519 520[system.membus] 521type=CoherentBus 522block_size=64 523clock=1000 524header_cycles=1 525use_default_range=false 526width=8 527master=system.physmem.port 528slave=system.system_port system.cpu.l2cache.mem_side 529 530[system.physmem] 531type=SimpleDRAM 532addr_mapping=openmap 533banks_per_rank=8 534clock=1000 535conf_table_reported=false 536in_addr_map=true 537lines_per_rowbuffer=64 538mem_sched_policy=fcfs 539null=false 540page_policy=open 541range=0:134217727 542ranks_per_channel=2 543read_buffer_size=32 544tBURST=4000 545tCL=14000 546tRCD=14000 547tREFI=7800000 548tRFC=300000 549tRP=14000 550tWTR=1000 551write_buffer_size=32 552write_thresh_perc=70 553zero=false 554port=system.membus.master[0] 555	496gid=100 497input=cin 498max_stack_size=67108864 499output=cout 500pid=100 501ppid=99 502simpoint=0 503system=system 504uid=100 505 506[system.membus] 507type=CoherentBus 508block_size=64 509clock=1000 510header_cycles=1 511use_default_range=false 512width=8 513master=system.physmem.port 514slave=system.system_port system.cpu.l2cache.mem_side 515 516[system.physmem] 517type=SimpleDRAM 518addr_mapping=openmap 519banks_per_rank=8 520clock=1000 521conf_table_reported=false 522in_addr_map=true 523lines_per_rowbuffer=64 524mem_sched_policy=fcfs 525null=false 526page_policy=open 527range=0:134217727 528ranks_per_channel=2 529read_buffer_size=32 530tBURST=4000 531tCL=14000 532tRCD=14000 533tREFI=7800000 534tRFC=300000 535tRP=14000 536tWTR=1000 537write_buffer_size=32 538write_thresh_perc=70 539zero=false 540port=system.membus.master[0] 541