Cross Reference: /gem5/tests/quick/se/00.hello/ref/mips/linux/o3-timing/config.ini

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config.ini (8835:7c68f84d7c4e)	config.ini (8983:8800b05e1cb3)
1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16	1[root] 2type=Root 3children=system 4full_system=false 5time_sync_enable=false 6time_sync_period=100000000000 7time_sync_spin_threshold=100000000 8 9[system] 10type=System 11children=cpu membus physmem 12boot_osflags=a 13init_param=0 14kernel= 15load_addr_mask=1099511627775 16mem_mode=atomic 17memories=system.physmem 18num_work_ids=16
19physmem=system.physmem
20readfile= 21symbolfile= 22work_begin_ckpt_count=0 23work_begin_cpu_id_exit=-1 24work_begin_exit_count=0 25work_cpus_ckpt_count=0 26work_end_ckpt_count=0 27work_end_exit_count=0 28work_item_id=-1	19readfile= 20symbolfile= 21work_begin_ckpt_count=0 22work_begin_cpu_id_exit=-1 23work_begin_exit_count=0 24work_cpus_ckpt_count=0 25work_end_ckpt_count=0 26work_end_exit_count=0 27work_item_id=-1
29system_port=system.membus.port[0]	28system_port=system.membus.slave[0]
30 31[system.cpu] 32type=DerivO3CPU 33children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 34BTBEntries=4096 35BTBTagSize=16 36LFSTSize=1024 37LQEntries=32 38LSQCheckLoads=true 39LSQDepCheckShift=4 40RASSize=16 41SQEntries=32 42SSITSize=1024 43activity=0 44backComSize=5 45cachePorts=200 46checker=Null 47choiceCtrBits=2 48choicePredictorSize=8192 49clock=500 50commitToDecodeDelay=1 51commitToFetchDelay=1 52commitToIEWDelay=1 53commitToRenameDelay=1 54commitWidth=8 55cpu_id=0 56decodeToFetchDelay=1 57decodeToRenameDelay=1 58decodeWidth=8 59defer_registration=false 60dispatchWidth=8 61do_checkpoint_insts=true 62do_quiesce=true 63do_statistics_insts=true 64dtb=system.cpu.dtb 65fetchToDecodeDelay=1 66fetchTrapLatency=1 67fetchWidth=8 68forwardComSize=5 69fuPool=system.cpu.fuPool 70function_trace=false 71function_trace_start=0 72globalCtrBits=2 73globalHistoryBits=13 74globalPredictorSize=8192 75iewToCommitDelay=1 76iewToDecodeDelay=1 77iewToFetchDelay=1 78iewToRenameDelay=1 79instShiftAmt=2 80interrupts=system.cpu.interrupts 81issueToExecuteDelay=1 82issueWidth=8 83itb=system.cpu.itb 84localCtrBits=2 85localHistoryBits=11 86localHistoryTableSize=2048 87localPredictorSize=2048 88max_insts_all_threads=0 89max_insts_any_thread=0 90max_loads_all_threads=0 91max_loads_any_thread=0 92needsTSO=false 93numIQEntries=64 94numPhysFloatRegs=256 95numPhysIntRegs=256 96numROBEntries=192 97numRobs=1 98numThreads=1 99phase=0 100predType=tournament 101profile=0 102progress_interval=0 103renameToDecodeDelay=1 104renameToFetchDelay=1 105renameToIEWDelay=2 106renameToROBDelay=1 107renameWidth=8 108smtCommitPolicy=RoundRobin 109smtFetchPolicy=SingleThread 110smtIQPolicy=Partitioned 111smtIQThreshold=100 112smtLSQPolicy=Partitioned 113smtLSQThreshold=100 114smtNumFetchingThreads=1 115smtROBPolicy=Partitioned 116smtROBThreshold=100 117squashWidth=8 118store_set_clear_period=250000 119system=system 120tracer=system.cpu.tracer 121trapLatency=13 122wbDepth=1 123wbWidth=8 124workload=system.cpu.workload 125dcache_port=system.cpu.dcache.cpu_side 126icache_port=system.cpu.icache.cpu_side 127 128[system.cpu.dcache] 129type=BaseCache	29 30[system.cpu] 31type=DerivO3CPU 32children=dcache dtb fuPool icache interrupts itb l2cache toL2Bus tracer workload 33BTBEntries=4096 34BTBTagSize=16 35LFSTSize=1024 36LQEntries=32 37LSQCheckLoads=true 38LSQDepCheckShift=4 39RASSize=16 40SQEntries=32 41SSITSize=1024 42activity=0 43backComSize=5 44cachePorts=200 45checker=Null 46choiceCtrBits=2 47choicePredictorSize=8192 48clock=500 49commitToDecodeDelay=1 50commitToFetchDelay=1 51commitToIEWDelay=1 52commitToRenameDelay=1 53commitWidth=8 54cpu_id=0 55decodeToFetchDelay=1 56decodeToRenameDelay=1 57decodeWidth=8 58defer_registration=false 59dispatchWidth=8 60do_checkpoint_insts=true 61do_quiesce=true 62do_statistics_insts=true 63dtb=system.cpu.dtb 64fetchToDecodeDelay=1 65fetchTrapLatency=1 66fetchWidth=8 67forwardComSize=5 68fuPool=system.cpu.fuPool 69function_trace=false 70function_trace_start=0 71globalCtrBits=2 72globalHistoryBits=13 73globalPredictorSize=8192 74iewToCommitDelay=1 75iewToDecodeDelay=1 76iewToFetchDelay=1 77iewToRenameDelay=1 78instShiftAmt=2 79interrupts=system.cpu.interrupts 80issueToExecuteDelay=1 81issueWidth=8 82itb=system.cpu.itb 83localCtrBits=2 84localHistoryBits=11 85localHistoryTableSize=2048 86localPredictorSize=2048 87max_insts_all_threads=0 88max_insts_any_thread=0 89max_loads_all_threads=0 90max_loads_any_thread=0 91needsTSO=false 92numIQEntries=64 93numPhysFloatRegs=256 94numPhysIntRegs=256 95numROBEntries=192 96numRobs=1 97numThreads=1 98phase=0 99predType=tournament 100profile=0 101progress_interval=0 102renameToDecodeDelay=1 103renameToFetchDelay=1 104renameToIEWDelay=2 105renameToROBDelay=1 106renameWidth=8 107smtCommitPolicy=RoundRobin 108smtFetchPolicy=SingleThread 109smtIQPolicy=Partitioned 110smtIQThreshold=100 111smtLSQPolicy=Partitioned 112smtLSQThreshold=100 113smtNumFetchingThreads=1 114smtROBPolicy=Partitioned 115smtROBThreshold=100 116squashWidth=8 117store_set_clear_period=250000 118system=system 119tracer=system.cpu.tracer 120trapLatency=13 121wbDepth=1 122wbWidth=8 123workload=system.cpu.workload 124dcache_port=system.cpu.dcache.cpu_side 125icache_port=system.cpu.icache.cpu_side 126 127[system.cpu.dcache] 128type=BaseCache
130addr_range=0:18446744073709551615	129addr_ranges=0:18446744073709551615
131assoc=2 132block_size=64 133forward_snoops=true 134hash_delay=1 135is_top_level=true 136latency=1000 137max_miss_count=0 138mshrs=10 139prefetch_on_access=false 140prefetcher=Null 141prioritizeRequests=false 142repl=Null 143size=262144 144subblock_size=0 145system=system 146tgts_per_mshr=20 147trace_addr=0 148two_queue=false 149write_buffers=8 150cpu_side=system.cpu.dcache_port	130assoc=2 131block_size=64 132forward_snoops=true 133hash_delay=1 134is_top_level=true 135latency=1000 136max_miss_count=0 137mshrs=10 138prefetch_on_access=false 139prefetcher=Null 140prioritizeRequests=false 141repl=Null 142size=262144 143subblock_size=0 144system=system 145tgts_per_mshr=20 146trace_addr=0 147two_queue=false 148write_buffers=8 149cpu_side=system.cpu.dcache_port
151mem_side=system.cpu.toL2Bus.port[1]	150mem_side=system.cpu.toL2Bus.slave[1]
152 153[system.cpu.dtb] 154type=MipsTLB 155size=64 156 157[system.cpu.fuPool] 158type=FUPool 159children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 160FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 161 162[system.cpu.fuPool.FUList0] 163type=FUDesc 164children=opList 165count=6 166opList=system.cpu.fuPool.FUList0.opList 167 168[system.cpu.fuPool.FUList0.opList] 169type=OpDesc 170issueLat=1 171opClass=IntAlu 172opLat=1 173 174[system.cpu.fuPool.FUList1] 175type=FUDesc 176children=opList0 opList1 177count=2 178opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 179 180[system.cpu.fuPool.FUList1.opList0] 181type=OpDesc 182issueLat=1 183opClass=IntMult 184opLat=3 185 186[system.cpu.fuPool.FUList1.opList1] 187type=OpDesc 188issueLat=19 189opClass=IntDiv 190opLat=20 191 192[system.cpu.fuPool.FUList2] 193type=FUDesc 194children=opList0 opList1 opList2 195count=4 196opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 197 198[system.cpu.fuPool.FUList2.opList0] 199type=OpDesc 200issueLat=1 201opClass=FloatAdd 202opLat=2 203 204[system.cpu.fuPool.FUList2.opList1] 205type=OpDesc 206issueLat=1 207opClass=FloatCmp 208opLat=2 209 210[system.cpu.fuPool.FUList2.opList2] 211type=OpDesc 212issueLat=1 213opClass=FloatCvt 214opLat=2 215 216[system.cpu.fuPool.FUList3] 217type=FUDesc 218children=opList0 opList1 opList2 219count=2 220opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 221 222[system.cpu.fuPool.FUList3.opList0] 223type=OpDesc 224issueLat=1 225opClass=FloatMult 226opLat=4 227 228[system.cpu.fuPool.FUList3.opList1] 229type=OpDesc 230issueLat=12 231opClass=FloatDiv 232opLat=12 233 234[system.cpu.fuPool.FUList3.opList2] 235type=OpDesc 236issueLat=24 237opClass=FloatSqrt 238opLat=24 239 240[system.cpu.fuPool.FUList4] 241type=FUDesc 242children=opList 243count=0 244opList=system.cpu.fuPool.FUList4.opList 245 246[system.cpu.fuPool.FUList4.opList] 247type=OpDesc 248issueLat=1 249opClass=MemRead 250opLat=1 251 252[system.cpu.fuPool.FUList5] 253type=FUDesc 254children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 255count=4 256opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 257 258[system.cpu.fuPool.FUList5.opList00] 259type=OpDesc 260issueLat=1 261opClass=SimdAdd 262opLat=1 263 264[system.cpu.fuPool.FUList5.opList01] 265type=OpDesc 266issueLat=1 267opClass=SimdAddAcc 268opLat=1 269 270[system.cpu.fuPool.FUList5.opList02] 271type=OpDesc 272issueLat=1 273opClass=SimdAlu 274opLat=1 275 276[system.cpu.fuPool.FUList5.opList03] 277type=OpDesc 278issueLat=1 279opClass=SimdCmp 280opLat=1 281 282[system.cpu.fuPool.FUList5.opList04] 283type=OpDesc 284issueLat=1 285opClass=SimdCvt 286opLat=1 287 288[system.cpu.fuPool.FUList5.opList05] 289type=OpDesc 290issueLat=1 291opClass=SimdMisc 292opLat=1 293 294[system.cpu.fuPool.FUList5.opList06] 295type=OpDesc 296issueLat=1 297opClass=SimdMult 298opLat=1 299 300[system.cpu.fuPool.FUList5.opList07] 301type=OpDesc 302issueLat=1 303opClass=SimdMultAcc 304opLat=1 305 306[system.cpu.fuPool.FUList5.opList08] 307type=OpDesc 308issueLat=1 309opClass=SimdShift 310opLat=1 311 312[system.cpu.fuPool.FUList5.opList09] 313type=OpDesc 314issueLat=1 315opClass=SimdShiftAcc 316opLat=1 317 318[system.cpu.fuPool.FUList5.opList10] 319type=OpDesc 320issueLat=1 321opClass=SimdSqrt 322opLat=1 323 324[system.cpu.fuPool.FUList5.opList11] 325type=OpDesc 326issueLat=1 327opClass=SimdFloatAdd 328opLat=1 329 330[system.cpu.fuPool.FUList5.opList12] 331type=OpDesc 332issueLat=1 333opClass=SimdFloatAlu 334opLat=1 335 336[system.cpu.fuPool.FUList5.opList13] 337type=OpDesc 338issueLat=1 339opClass=SimdFloatCmp 340opLat=1 341 342[system.cpu.fuPool.FUList5.opList14] 343type=OpDesc 344issueLat=1 345opClass=SimdFloatCvt 346opLat=1 347 348[system.cpu.fuPool.FUList5.opList15] 349type=OpDesc 350issueLat=1 351opClass=SimdFloatDiv 352opLat=1 353 354[system.cpu.fuPool.FUList5.opList16] 355type=OpDesc 356issueLat=1 357opClass=SimdFloatMisc 358opLat=1 359 360[system.cpu.fuPool.FUList5.opList17] 361type=OpDesc 362issueLat=1 363opClass=SimdFloatMult 364opLat=1 365 366[system.cpu.fuPool.FUList5.opList18] 367type=OpDesc 368issueLat=1 369opClass=SimdFloatMultAcc 370opLat=1 371 372[system.cpu.fuPool.FUList5.opList19] 373type=OpDesc 374issueLat=1 375opClass=SimdFloatSqrt 376opLat=1 377 378[system.cpu.fuPool.FUList6] 379type=FUDesc 380children=opList 381count=0 382opList=system.cpu.fuPool.FUList6.opList 383 384[system.cpu.fuPool.FUList6.opList] 385type=OpDesc 386issueLat=1 387opClass=MemWrite 388opLat=1 389 390[system.cpu.fuPool.FUList7] 391type=FUDesc 392children=opList0 opList1 393count=4 394opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 395 396[system.cpu.fuPool.FUList7.opList0] 397type=OpDesc 398issueLat=1 399opClass=MemRead 400opLat=1 401 402[system.cpu.fuPool.FUList7.opList1] 403type=OpDesc 404issueLat=1 405opClass=MemWrite 406opLat=1 407 408[system.cpu.fuPool.FUList8] 409type=FUDesc 410children=opList 411count=1 412opList=system.cpu.fuPool.FUList8.opList 413 414[system.cpu.fuPool.FUList8.opList] 415type=OpDesc 416issueLat=3 417opClass=IprAccess 418opLat=3 419 420[system.cpu.icache] 421type=BaseCache	151 152[system.cpu.dtb] 153type=MipsTLB 154size=64 155 156[system.cpu.fuPool] 157type=FUPool 158children=FUList0 FUList1 FUList2 FUList3 FUList4 FUList5 FUList6 FUList7 FUList8 159FUList=system.cpu.fuPool.FUList0 system.cpu.fuPool.FUList1 system.cpu.fuPool.FUList2 system.cpu.fuPool.FUList3 system.cpu.fuPool.FUList4 system.cpu.fuPool.FUList5 system.cpu.fuPool.FUList6 system.cpu.fuPool.FUList7 system.cpu.fuPool.FUList8 160 161[system.cpu.fuPool.FUList0] 162type=FUDesc 163children=opList 164count=6 165opList=system.cpu.fuPool.FUList0.opList 166 167[system.cpu.fuPool.FUList0.opList] 168type=OpDesc 169issueLat=1 170opClass=IntAlu 171opLat=1 172 173[system.cpu.fuPool.FUList1] 174type=FUDesc 175children=opList0 opList1 176count=2 177opList=system.cpu.fuPool.FUList1.opList0 system.cpu.fuPool.FUList1.opList1 178 179[system.cpu.fuPool.FUList1.opList0] 180type=OpDesc 181issueLat=1 182opClass=IntMult 183opLat=3 184 185[system.cpu.fuPool.FUList1.opList1] 186type=OpDesc 187issueLat=19 188opClass=IntDiv 189opLat=20 190 191[system.cpu.fuPool.FUList2] 192type=FUDesc 193children=opList0 opList1 opList2 194count=4 195opList=system.cpu.fuPool.FUList2.opList0 system.cpu.fuPool.FUList2.opList1 system.cpu.fuPool.FUList2.opList2 196 197[system.cpu.fuPool.FUList2.opList0] 198type=OpDesc 199issueLat=1 200opClass=FloatAdd 201opLat=2 202 203[system.cpu.fuPool.FUList2.opList1] 204type=OpDesc 205issueLat=1 206opClass=FloatCmp 207opLat=2 208 209[system.cpu.fuPool.FUList2.opList2] 210type=OpDesc 211issueLat=1 212opClass=FloatCvt 213opLat=2 214 215[system.cpu.fuPool.FUList3] 216type=FUDesc 217children=opList0 opList1 opList2 218count=2 219opList=system.cpu.fuPool.FUList3.opList0 system.cpu.fuPool.FUList3.opList1 system.cpu.fuPool.FUList3.opList2 220 221[system.cpu.fuPool.FUList3.opList0] 222type=OpDesc 223issueLat=1 224opClass=FloatMult 225opLat=4 226 227[system.cpu.fuPool.FUList3.opList1] 228type=OpDesc 229issueLat=12 230opClass=FloatDiv 231opLat=12 232 233[system.cpu.fuPool.FUList3.opList2] 234type=OpDesc 235issueLat=24 236opClass=FloatSqrt 237opLat=24 238 239[system.cpu.fuPool.FUList4] 240type=FUDesc 241children=opList 242count=0 243opList=system.cpu.fuPool.FUList4.opList 244 245[system.cpu.fuPool.FUList4.opList] 246type=OpDesc 247issueLat=1 248opClass=MemRead 249opLat=1 250 251[system.cpu.fuPool.FUList5] 252type=FUDesc 253children=opList00 opList01 opList02 opList03 opList04 opList05 opList06 opList07 opList08 opList09 opList10 opList11 opList12 opList13 opList14 opList15 opList16 opList17 opList18 opList19 254count=4 255opList=system.cpu.fuPool.FUList5.opList00 system.cpu.fuPool.FUList5.opList01 system.cpu.fuPool.FUList5.opList02 system.cpu.fuPool.FUList5.opList03 system.cpu.fuPool.FUList5.opList04 system.cpu.fuPool.FUList5.opList05 system.cpu.fuPool.FUList5.opList06 system.cpu.fuPool.FUList5.opList07 system.cpu.fuPool.FUList5.opList08 system.cpu.fuPool.FUList5.opList09 system.cpu.fuPool.FUList5.opList10 system.cpu.fuPool.FUList5.opList11 system.cpu.fuPool.FUList5.opList12 system.cpu.fuPool.FUList5.opList13 system.cpu.fuPool.FUList5.opList14 system.cpu.fuPool.FUList5.opList15 system.cpu.fuPool.FUList5.opList16 system.cpu.fuPool.FUList5.opList17 system.cpu.fuPool.FUList5.opList18 system.cpu.fuPool.FUList5.opList19 256 257[system.cpu.fuPool.FUList5.opList00] 258type=OpDesc 259issueLat=1 260opClass=SimdAdd 261opLat=1 262 263[system.cpu.fuPool.FUList5.opList01] 264type=OpDesc 265issueLat=1 266opClass=SimdAddAcc 267opLat=1 268 269[system.cpu.fuPool.FUList5.opList02] 270type=OpDesc 271issueLat=1 272opClass=SimdAlu 273opLat=1 274 275[system.cpu.fuPool.FUList5.opList03] 276type=OpDesc 277issueLat=1 278opClass=SimdCmp 279opLat=1 280 281[system.cpu.fuPool.FUList5.opList04] 282type=OpDesc 283issueLat=1 284opClass=SimdCvt 285opLat=1 286 287[system.cpu.fuPool.FUList5.opList05] 288type=OpDesc 289issueLat=1 290opClass=SimdMisc 291opLat=1 292 293[system.cpu.fuPool.FUList5.opList06] 294type=OpDesc 295issueLat=1 296opClass=SimdMult 297opLat=1 298 299[system.cpu.fuPool.FUList5.opList07] 300type=OpDesc 301issueLat=1 302opClass=SimdMultAcc 303opLat=1 304 305[system.cpu.fuPool.FUList5.opList08] 306type=OpDesc 307issueLat=1 308opClass=SimdShift 309opLat=1 310 311[system.cpu.fuPool.FUList5.opList09] 312type=OpDesc 313issueLat=1 314opClass=SimdShiftAcc 315opLat=1 316 317[system.cpu.fuPool.FUList5.opList10] 318type=OpDesc 319issueLat=1 320opClass=SimdSqrt 321opLat=1 322 323[system.cpu.fuPool.FUList5.opList11] 324type=OpDesc 325issueLat=1 326opClass=SimdFloatAdd 327opLat=1 328 329[system.cpu.fuPool.FUList5.opList12] 330type=OpDesc 331issueLat=1 332opClass=SimdFloatAlu 333opLat=1 334 335[system.cpu.fuPool.FUList5.opList13] 336type=OpDesc 337issueLat=1 338opClass=SimdFloatCmp 339opLat=1 340 341[system.cpu.fuPool.FUList5.opList14] 342type=OpDesc 343issueLat=1 344opClass=SimdFloatCvt 345opLat=1 346 347[system.cpu.fuPool.FUList5.opList15] 348type=OpDesc 349issueLat=1 350opClass=SimdFloatDiv 351opLat=1 352 353[system.cpu.fuPool.FUList5.opList16] 354type=OpDesc 355issueLat=1 356opClass=SimdFloatMisc 357opLat=1 358 359[system.cpu.fuPool.FUList5.opList17] 360type=OpDesc 361issueLat=1 362opClass=SimdFloatMult 363opLat=1 364 365[system.cpu.fuPool.FUList5.opList18] 366type=OpDesc 367issueLat=1 368opClass=SimdFloatMultAcc 369opLat=1 370 371[system.cpu.fuPool.FUList5.opList19] 372type=OpDesc 373issueLat=1 374opClass=SimdFloatSqrt 375opLat=1 376 377[system.cpu.fuPool.FUList6] 378type=FUDesc 379children=opList 380count=0 381opList=system.cpu.fuPool.FUList6.opList 382 383[system.cpu.fuPool.FUList6.opList] 384type=OpDesc 385issueLat=1 386opClass=MemWrite 387opLat=1 388 389[system.cpu.fuPool.FUList7] 390type=FUDesc 391children=opList0 opList1 392count=4 393opList=system.cpu.fuPool.FUList7.opList0 system.cpu.fuPool.FUList7.opList1 394 395[system.cpu.fuPool.FUList7.opList0] 396type=OpDesc 397issueLat=1 398opClass=MemRead 399opLat=1 400 401[system.cpu.fuPool.FUList7.opList1] 402type=OpDesc 403issueLat=1 404opClass=MemWrite 405opLat=1 406 407[system.cpu.fuPool.FUList8] 408type=FUDesc 409children=opList 410count=1 411opList=system.cpu.fuPool.FUList8.opList 412 413[system.cpu.fuPool.FUList8.opList] 414type=OpDesc 415issueLat=3 416opClass=IprAccess 417opLat=3 418 419[system.cpu.icache] 420type=BaseCache
422addr_range=0:18446744073709551615	421addr_ranges=0:18446744073709551615
423assoc=2 424block_size=64 425forward_snoops=true 426hash_delay=1 427is_top_level=true 428latency=1000 429max_miss_count=0 430mshrs=10 431prefetch_on_access=false 432prefetcher=Null 433prioritizeRequests=false 434repl=Null 435size=131072 436subblock_size=0 437system=system 438tgts_per_mshr=20 439trace_addr=0 440two_queue=false 441write_buffers=8 442cpu_side=system.cpu.icache_port	422assoc=2 423block_size=64 424forward_snoops=true 425hash_delay=1 426is_top_level=true 427latency=1000 428max_miss_count=0 429mshrs=10 430prefetch_on_access=false 431prefetcher=Null 432prioritizeRequests=false 433repl=Null 434size=131072 435subblock_size=0 436system=system 437tgts_per_mshr=20 438trace_addr=0 439two_queue=false 440write_buffers=8 441cpu_side=system.cpu.icache_port
443mem_side=system.cpu.toL2Bus.port[0]	442mem_side=system.cpu.toL2Bus.slave[0]
444 445[system.cpu.interrupts] 446type=MipsInterrupts 447 448[system.cpu.itb] 449type=MipsTLB 450size=64 451 452[system.cpu.l2cache] 453type=BaseCache	443 444[system.cpu.interrupts] 445type=MipsInterrupts 446 447[system.cpu.itb] 448type=MipsTLB 449size=64 450 451[system.cpu.l2cache] 452type=BaseCache
454addr_range=0:18446744073709551615	453addr_ranges=0:18446744073709551615
455assoc=2 456block_size=64 457forward_snoops=true 458hash_delay=1 459is_top_level=false 460latency=1000 461max_miss_count=0 462mshrs=10 463prefetch_on_access=false 464prefetcher=Null 465prioritizeRequests=false 466repl=Null 467size=2097152 468subblock_size=0 469system=system 470tgts_per_mshr=5 471trace_addr=0 472two_queue=false 473write_buffers=8	454assoc=2 455block_size=64 456forward_snoops=true 457hash_delay=1 458is_top_level=false 459latency=1000 460max_miss_count=0 461mshrs=10 462prefetch_on_access=false 463prefetcher=Null 464prioritizeRequests=false 465repl=Null 466size=2097152 467subblock_size=0 468system=system 469tgts_per_mshr=5 470trace_addr=0 471two_queue=false 472write_buffers=8
474cpu_side=system.cpu.toL2Bus.port[2] 475mem_side=system.membus.port[2]	473cpu_side=system.cpu.toL2Bus.master[0] 474mem_side=system.membus.slave[1]
476 477[system.cpu.toL2Bus] 478type=Bus 479block_size=64 480bus_id=0 481clock=1000 482header_cycles=1 483use_default_range=false 484width=64	475 476[system.cpu.toL2Bus] 477type=Bus 478block_size=64 479bus_id=0 480clock=1000 481header_cycles=1 482use_default_range=false 483width=64
485port=system.cpu.icache.mem_side system.cpu.dcache.mem_side system.cpu.l2cache.cpu_side	484master=system.cpu.l2cache.cpu_side 485slave=system.cpu.icache.mem_side system.cpu.dcache.mem_side
486 487[system.cpu.tracer] 488type=ExeTracer 489 490[system.cpu.workload] 491type=LiveProcess 492cmd=hello 493cwd= 494egid=100 495env= 496errout=cerr 497euid=100 498executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello 499gid=100 500input=cin 501max_stack_size=67108864 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.membus] 510type=Bus 511block_size=64 512bus_id=0 513clock=1000 514header_cycles=1 515use_default_range=false 516width=64	486 487[system.cpu.tracer] 488type=ExeTracer 489 490[system.cpu.workload] 491type=LiveProcess 492cmd=hello 493cwd= 494egid=100 495env= 496errout=cerr 497euid=100 498executable=/dist/m5/regression/test-progs/hello/bin/mips/linux/hello 499gid=100 500input=cin 501max_stack_size=67108864 502output=cout 503pid=100 504ppid=99 505simpoint=0 506system=system 507uid=100 508 509[system.membus] 510type=Bus 511block_size=64 512bus_id=0 513clock=1000 514header_cycles=1 515use_default_range=false 516width=64
517port=system.system_port system.physmem.port[0] system.cpu.l2cache.mem_side	517master=system.physmem.port[0] 518slave=system.system_port system.cpu.l2cache.mem_side
518 519[system.physmem]	519 520[system.physmem]
520type=PhysicalMemory	521type=SimpleMemory 522conf_table_reported=false
521file=	523file=
	524in_addr_map=true
522latency=30000 523latency_var=0 524null=false 525range=0:134217727 526zero=false	525latency=30000 526latency_var=0 527null=false 528range=0:134217727 529zero=false
527port=system.membus.port[1]	530port=system.membus.master[0]
528	531